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kelvin_xq@hotmail.com (Kelvin Tsai @ Singapore) writes: > Who uses MIPS? I wrote: > People who don't want to pay the license fees for ARM? "B. Joshua Rosen" <bjrosen@polybus.com> writes: > MIPS is proprietary also. Certainly. But it doesn't cost as much to license, or so I've been told.Article: 57126
In article <qhd6h4jb0p.fsf@ruckus.brouhaha.com>, Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: >"B. Joshua Rosen" <bjrosen@polybus.com> writes: >> MIPS is proprietary also. > >Certainly. But it doesn't cost as much to license, or so I've been told. There is always Sparc, which doesn't have a liscence fee to use the ISA, only to use the SPARC trademark. Of course, register windows are a bad idea, but hey, nothing's perfect. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 57127
what are the stratix IO pins during configuration device?in other words,are they tri states?Article: 57128
I have stable 10 MHz. Is it possible to get 27 MHz from this frequency using FPGA(Altera ACEX)?? And if it is then how?? Thanks for your answers!Article: 57129
Hi all, As part of a design I need to transfer data which is arriving on both edges of a 350 MHz clock to a 175 MHz clock. The 175 MHz clock comes from the divided output of the same DCM as the 350, but there could be clock skew. Data is arriving on every edge of the 350 and all of it needs to be transferred. I'm using a Virtex-II -5. It isn't possible to transfer data between opposite edges of the 350 MHz clock (according to TRCE the chip simply won't run that fast - FF to FF needs to be about 1.35 ns and the best I've seen is about 1.38, which is still pretty impressive!). Any suggestions? All the designs I could find in app notes used x1 and x4 clocks, or could transfer data between edges of the same clock because the clock frequency was sufficiently low. The positive 350 to 175 case is solvable but I can't see an obvious solution to the negative 350 to 175 case, because the negative edge of 350 isn't aligned to anything in the 175. Thanks, Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 57130
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3EF7744D.1CF9F6D@yahoo.com>...
> Tauno Voipio wrote:
> >
> > "rickman" <spamgoeshere4@yahoo.com> wrote in message
> > news:3EF744FB.AF2FB36E@yahoo.com...
> > > Tauno Voipio wrote:
> > > >
> > > > "y_p_w" <y_p_w@hotmail.com> wrote in message
> > > > news:591da479.0306230937.42883d68@posting.google.com...
> > > > > Hi-
> > > > >
> > > > > I'm currently in the process of creating a synthesizable Verilog
> > > > > F/S I2C slave, but have little experience with I2C in the real
> > > > > world.
> > > > >
> > > > > I'm reading the specs, and I feel I'm getting a pretty good
> > > > > understanding. If I'm getting this right, the SDA line will only
> > > > > change when the SCL line is low - except when the master is
> > > > > indicating a START or STOP command.
> > > > >
> > > > > So the question I have for those who have really done this is -
> > > > > in the real world, could a master (or series of masters) issue
> > > > > a STOP command followed by a START command - all on the same
> > > > > SCL high period. The latest I2C spec doesn't explain whether
> > > > > or not this could happen.
> > > > >
> > > > > This is key to me, since I'm trying to create an I2C slave that
> > > > > runs solely off the SDA and SCL signals. Whether or not I have
> > > > > to deal with START and STOP on the same SCL high period will
> > > > > impact the design choice I make.
> > > > >
> > > >
> > > > AFAIK, that's normal when the bus is idle in the meantime.
> > > >
> > > > The idle bus has all drivers loose and both lines up. When the master
> ends a
> > > > transmission, the last thing is the STOP condition: SCL up, then SDA up.
> > > > When the next transmission starts, the first thing is the START
> condition:
> > > > SCL still up, SDA down.
> > >
> > > I think he means the other way around, a START followed by a STOP with
> > > no clock transitions inbetween. In essence, this would be an "empty"
> > > frame.
> > >
> > > I have not worked with I2C before, so I don't know the answer. But I am
> > > interested since I will be making one as well.
> > >
> > > I have not checked opencores.org, but it seems likely that they would
> > > have a core for this. It might be a bit larger than you would want to
> > > use however.
> > >
> >
> > An empty frame is expressely forbidden in the specs. However, the logic must
> > still not hang up if such a condition should happen.
> >
> > Tauno Voipio
> > tauno voipio @ iki fi
>
> I guess that is the answer then. The condition should not occur, but if
> it does due to a defect in one component, it should not cause a problem
> in another component.
>
>
> To the OP,
>
> How does this change your design? I would think an empty frame would be
> handled like one that is not addressed to your device, no?
Well - here's my concerns and thinking:
1) It seems that the preferred method is to have a STOP condition
(SDA rising when SCL=1) on the same SCL high period as a START
period (SDA falling when SCL=1). This would look like this:
_________________________
SCL ___| |_____
_________________
SDA _______| |_________
2) As far as I can tell the spec says nothing about SCL changing
between a STOP and START. I wouldn't see any advantage to it,
but I couldn't sense it was illegal. I would suppose any
clock toggling before a START should just be ignored until a
START is detected.
3) I was worried about whether a master could "change its mind"
after issuing a start if it was suddenly occupied with something
considered more important. Fortunately, this doesn't seem to
be a problem.
4) Most of what I'm planning is a straightforward FSM clocked on
the negedge of SCL. The START and STOP logic I'm planning on
using isn't as straightforward. This was the part that would
have been messed up if I had to account for multiple START or
STOP methods. I wanted to create a START detected signal, and
use that to tell the FSM when to start monitoring SDA.
5) I could possibly use a high-speed internal clock. However -
the goal is a low-power design, and I was told that just
toggling the clock tree would create unnecessary power
consumption.
Article: 57131H. Peter Anvin <hpa@zytor.com> writes: > Since I see that some Altera people are reading this group... the > current version of Quartus II has a Linux version, which I have access > to; however, it's a Winelib application and they only formally support Quartus II does not use Wine. It uses a library called mainwin under Linux and Solaris. > RedHat 7.1, which is ancient by now. It does not work on my RedHat 9 > workstation. I have used Quartus II under various Linux releases (Red Hat 7.1, 7.2, several versions of Slackware), but not under RedHat 9. What kind of errors do you get? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 57132
"Kelvin Tsai @ Singapore" <kelvin_xq@hotmail.com> wrote in message news:bf7e7c6.0306230005.17fb2bfe@posting.google.com... > I came across a CPU which uses MIPS instruction set. I know that > current trend is towards ARM, may I know, how was the popularity and > how is prosperity of MIPS? Who uses MIPS? What are the areas that MIPS > processors most likely to use? MIPS is 64 bits. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 57133
"Chris Carlen" <crcarle@BOGUS.sandia.gov> wrote in message news:bd800f$h6s$1@sass2141.sandia.gov... > Hi: > > Just looking for a refresher on the current status of running ISE > Webpack 5.2i on Linux. > > Is a Windows installation needed with Wine, or can vanilla Wine do the job? > > I searched at xilinx.com for "linux" and saw a bunch of tidbits, but is > there any definitive document describing what must be done, or is it > pretty much a no-brainer? Further to this, does anyone know if downloaded WebPack 5.2i can be *installed* under WinME so that the files may be transferred to Linux. I know it won't run properly on WinME. Or, will the downloaded file install on Linux/WINE as the CD-ROM does, supposedly? Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 57134
Leon Heller <leon_heller@hotmail.com> wrote: ... : Further to this, does anyone know if downloaded WebPack 5.2i can be : *installed* under WinME so that the files may be transferred to Linux. I : know it won't run properly on WinME. Installing under wine is preferred. That way, registry entries and such get know to wine. Remember to set wine's version to nt40/win2k/winxp for ISE. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57135
kelvin_xq@hotmail.com (Kelvin Tsai @ Singapore) writes: > I came across a CPU which uses MIPS instruction set. I know that > current trend is towards ARM, may I know, how was the popularity and > how is prosperity of MIPS? Who uses MIPS? What are the areas that MIPS > processors most likely to use? Look at http://www.mips.com and http://www.sgi.com Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 57137
Jim Granville <jim.granville@designtools.co.nz> wrote: > Chain-of-gates delays lines are possible, but need some calibration > scheme as they are process/temp/vcc dependant. > < 1ns step is not a problem > > 1GHz is probably just appearing on FPGA radar - ask Peter A. Actel announced its AX-Techologie to reach 1GHZ internal PLL output. Don't know if the technologie is fast enough to use this output for a counter :). bye ThomasArticle: 57138
> > Thanks for the answer. I actually re-read the spec, and noticed > that a STOP following a START in the same SCL high period is illegal. > I'm going to ignore an illegally applied STOP (i.e. illegal STOP > ignored). I was also worried about the possibility of repeated STOP/ > START/STOP/START sequences. > > However - as a follow-up question, would it be possible to see SCL > toggle after a STOP before the next START command "in the real world"? > None of the timing diagrams in the spec seem to address this > possibility; all diagrams show SDA and SCL staying high for the > foreseeable future. I'd guess that the thing to do is simply put > put the I2C slave in a wait state until a START condition is seen. I > wouldn't see any reason to toggle SCL between a STOP and the next > START, but I haven't seen any real-world designs. > > Again - many thanks for the replies. Hi Well that's what really matters (IHO), "the real world". And in the real world everything is possible. You can have a lousy implemented micro-controller software I2C or even if you are debugging the hardware you can accidentally toggle a line. I know applications where they misuse the spec and by driving the SCL low between STOP and START for a certain time, they signal other devices for example busmaster takeover. Everything is possible. If you are designing this for a real application you have to deal with the real world and you must handle all the situations you can think off. It's very clumsy if your hardware is 'hanging'. Master controllers are build by spec's and slaves by sense. Gerard www.stacktools.comArticle: 57139
Nicholas C. Weaver <nweaver@ribbit.cs.berkeley.edu> wrote: > In article <qhd6h4jb0p.fsf@ruckus.brouhaha.com>, > Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: >>"B. Joshua Rosen" <bjrosen@polybus.com> writes: >>> MIPS is proprietary also. >> >>Certainly. But it doesn't cost as much to license, or so I've been told. > > There is always Sparc, which doesn't have a liscence fee to use the > ISA, only to use the SPARC trademark. sparc licence costs $99 - to use the mark i believe you have to pass certification, which probably costs more. But don't quote me on this > > Of course, register windows are a bad idea, but hey, nothing's > perfect. but with block rams, there are much less problems. of course, everybody can always start from scratch and make a fpga specific one -- Sander +++ Out of cheese error +++Article: 57140
Using EDK3.2 with EDK3.2 pre-compiled libraries I get the following type of error from Modelsim 5.7c " WARNING[1]: C:/temp/Xilinx/MicroBlazeTest/hdl/lmb_lmb_bram_if_cntlr_0_wrapper.vhd(143): Entity C:/Xilinx/EDK/Modelsim/proc_common_v1_00_b.pselect_mask not selected for default binding because entity is out of date and needs to be recompiled # ** Error: C:/Xilinx/EDK/Modelsim/lmb_lmb_bram_if_cntlr_v1_00_a/lmb_lmb_bram_if_cntlr/_primary.dat(54): cannot find expanded name: proc_common_v1_00_b.pselect_mask". Surely all the data on the EDK CD is compatible? Where can I download updated pre-compiled libraries? AnthonyArticle: 57141
y_p_w wrote: > > Well - here's my concerns and thinking: > > 1) It seems that the preferred method is to have a STOP condition > (SDA rising when SCL=1) on the same SCL high period as a START > period (SDA falling when SCL=1). This would look like this: > _________________________ > SCL ___| |_____ > _________________ > SDA _______| |_________ > > 2) As far as I can tell the spec says nothing about SCL changing > between a STOP and START. I wouldn't see any advantage to it, > but I couldn't sense it was illegal. I would suppose any > clock toggling before a START should just be ignored until a > START is detected. > > 3) I was worried about whether a master could "change its mind" > after issuing a start if it was suddenly occupied with something > considered more important. Fortunately, this doesn't seem to > be a problem. > > 4) Most of what I'm planning is a straightforward FSM clocked on > the negedge of SCL. The START and STOP logic I'm planning on > using isn't as straightforward. This was the part that would > have been messed up if I had to account for multiple START or > STOP methods. I wanted to create a START detected signal, and > use that to tell the FSM when to start monitoring SDA. > > 5) I could possibly use a high-speed internal clock. However - > the goal is a low-power design, and I was told that just > toggling the clock tree would create unnecessary power > consumption. I have not given this a lot of thought, but I believe you can use two FFs (with resets) to detect the start/stop conditions and maintain a state of disabled/enabled. The start FF is clocked on the falling edge of SDA with SCL on the D input. This FF will be set on a start condition. The stop FF will be clocked on the rising edge of SDA with SCL on the D input. This FF will be set on the stop condition. The start FF being off will hold the stop FF in reset. The stop FF being set will reset the start FF. So the sequence will be; 1) both FFs clear 2) on start, the start FF is set and the rest of the circuit is enabled 3) on stop, the stop FF is set which clears the start FF 4) the start FF being cleared also clears the stop FF The only issue I can see with this design is that the stop FF will generate a reset pulse determined by the time it takes to reset both FFs plus the routing. Some people would object to this saying it may violate the timing requirements of your logic. If so, you may want to use the LUT or the OR array with the FF to add some extra delay. In general this should work ok since it is basically self timed logic. On the other hand, using a synchronous design should not consume much power. Unless you are going for power below 100 uA, a low power CPLD (like the coolrunner) should be able to run at 1 MHz (fast enough for most I2C chips at 400 kb/s) with power at that level. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57142
hamish@cloud.net.au wrote in message news:<3ef8003c$0$31513$5a62ac22@freenews.iinet.net.au>... > Hi all, > > As part of a design I need to transfer data which is arriving on both > edges of a 350 MHz clock to a 175 MHz clock. The 175 MHz clock comes > from the divided output of the same DCM as the 350, but there could be > clock skew. Data is arriving on every edge of the 350 and all of it > needs to be transferred. > > I'm using a Virtex-II -5. It isn't possible to transfer data between > opposite edges of the 350 MHz clock (according to TRCE the chip simply > won't run that fast - FF to FF needs to be about 1.35 ns and the best > I've seen is about 1.38, which is still pretty impressive!). > > Any suggestions? All the designs I could find in app notes used x1 and > x4 clocks, or could transfer data between edges of the same clock > because the clock frequency was sufficiently low. > > The positive 350 to 175 case is solvable but I can't see an obvious > solution to the negative 350 to 175 case, because the negative edge of 350 > isn't aligned to anything in the 175. Howdy Hamish, What about leaving it in the negative 350 domain a little while longer? IE, make it slower/wider in the negative domain, then transfer it to the 175 domain? Good luck, MarcArticle: 57143
When I implement my design using max effort (=5), and the timing analyser reports no timing errors, the implemented design does not work at all (very buggy!). I am using several clock nets, but I make sure (I hope) that all domains are crossed in a safe way. (The design works fine at effort 4, even if some of the timings are reported bad). I know others have had this problem. (All my small state machines are binary) Does anyone know what the actual problem with effort 5 is: I'd like to try tweaking my design around those problems. Thanks Morten LeikvollArticle: 57144
"Erik Bolton" <erik.bolton@gdds.com> skrev i melding news:vp4efv8hnd592mjtkimsr13gevd1jsjij7@4ax.com... > Hello All: > > I'm working on an old PCB design from a piece of test equipment and > I'm looking to replace a bunch of old logic chips with a single > PLD/FPGA. The only chip I'm having trouble reproducing the behavior > for is the delay line. It's somewhat of a special part. It's a 10 > bit programmable line that steps in 1 ns increments and has an initial > prop. delay of 6 ns. Also, like most delay lines, it isn't clock > driven. I've read about a fairly straight-foward method of using a > counter with an overflow bit to create a delay, but the problem is the > step size. Since I need 1 ns steps I'd have to drive the counter with > a 1 Ghz clock which seems a little impractical for this circuit. If > you guys have any suggestions as to how I might pull this off I'd > really appreciate it. Thanks in advance! > > -Erik Bolton Altera annouces programmable delay of the PLL's (not DLL's) in some of their chips. (Are you sure you need this programmable delay?)Article: 57145
In Xilinx Virtex-II or Spartan3 this is trivial. You just do it inside the Digital Clock Manager in Frequency Synthesis Mode, calling for M=27 and D=10, which causes the clock frequency to be simultaneously multiplied by 27 and divided by 10. Magic :-) Peter Alfke ================ Lelik Bolik wrote: > > I have stable 10 MHz. Is it possible to get 27 MHz from this frequency > using FPGA(Altera ACEX)?? And if it is then how?? Thanks for your > answers!Article: 57146
I would generate a Clock Enable signal that is High for every even 350-MHz clock period, and another CE that is High for every odd period. Now you can clock in data into one flip-flop on the even-rising 350 MHz edge, and into another flip-flop on the even-falling 350 MHz edge, and you have a whole 350 MHz period to send the data to the appropriate 175 MHzflip-flop. A second set of flip-flops takes care of the odd 350 MHz period... Peter Alfke =================== hamish@cloud.net.au wrote: > > Hi all, > > As part of a design I need to transfer data which is arriving on both > edges of a 350 MHz clock to a 175 MHz clock. The 175 MHz clock comes > from the divided output of the same DCM as the 350, but there could be > clock skew. Data is arriving on every edge of the 350 and all of it > needs to be transferred. > > I'm using a Virtex-II -5. It isn't possible to transfer data between > opposite edges of the 350 MHz clock (according to TRCE the chip simply > won't run that fast - FF to FF needs to be about 1.35 ns and the best > I've seen is about 1.38, which is still pretty impressive!). > > Any suggestions? All the designs I could find in app notes used x1 and > x4 clocks, or could transfer data between edges of the same clock > because the clock frequency was sufficiently low. > > The positive 350 to 175 case is solvable but I can't see an obvious > solution to the negative 350 to 175 case, because the negative edge of 350 > isn't aligned to anything in the 175. > > Thanks, > Hamish > -- > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 57147
Hi all, I have the following problem compiling my project with Quartus II on EP1K100QC208-3 (Acex 1K family): resources utilization is under limits (4537/4992 LEs, 34816/49152 mem bits, 84/147 pins) and if I remove all pin assignments the project compiles properly. When I set pin assignments the compilation process can not end successfully, with several error messages like this: "Can't route source node ....". I don't know how I can solve this problem. Any suggestion would be highly appreciated. Thanks in advance, AndreaArticle: 57148
<hamish@cloud.net.au> skrev i melding news:3ef8003c$0$31513$5a62ac22@freenews.iinet.net.au... > Hi all, > > As part of a design I need to transfer data which is arriving on both > edges of a 350 MHz clock to a 175 MHz clock. The 175 MHz clock comes > from the divided output of the same DCM as the 350, but there could be > clock skew. Data is arriving on every edge of the 350 and all of it > needs to be transferred. > > I'm using a Virtex-II -5. It isn't possible to transfer data between > opposite edges of the 350 MHz clock (according to TRCE the chip simply > won't run that fast - FF to FF needs to be about 1.35 ns and the best > I've seen is about 1.38, which is still pretty impressive!). > > Any suggestions? All the designs I could find in app notes used x1 and > x4 clocks, or could transfer data between edges of the same clock > because the clock frequency was sufficiently low. > > The positive 350 to 175 case is solvable but I can't see an obvious > solution to the negative 350 to 175 case, because the negative edge of 350 > isn't aligned to anything in the 175. I dont know the details of the VirtexII-5, but is there a closeby dualport ram wich can handle 350Mhz writing? (one for positive edge and one for the negative (if the setup&hold times match!)). If you configure this ram with double datawidth out, you have the datas at 175Mhz from two ram blocks.Article: 57149
"Peter Alfke" <peter@xilinx.com> wrote in message news:3EF8705C.F4C384D4@xilinx.com... > In Xilinx Virtex-II or Spartan3 this is trivial. You just do it inside > the Digital Clock Manager in Frequency Synthesis Mode, calling for M=27 > and D=10, which causes the clock frequency to be simultaneously > multiplied by 27 and divided by 10. > Magic :-) > Peter Alfke > ================ > Lelik Bolik wrote: > > > > I have stable 10 MHz. Is it possible to get 27 MHz from this frequency > > using FPGA(Altera ACEX)?? And if it is then how?? Thanks for your > > answers! What about the minimal 24 MHz clock frequency for the DCM or does it only apply to the output clock frequency? Regards, Alvin Andries.
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