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Messages from 57550

Article: 57550
Subject: Re: Xilinx ISE drops support for more parts
From: lecroy7200@chek.com (lecroy)
Date: 2 Jul 2003 07:05:32 -0700
Links: << >>  << T >>  << A >>
JoeG <no@where.net> wrote in message news:<3F0219B6.8F56CB33@where.net>...
> I've ask Xilinx the ? about legacy support for years -- I have the same
> problem with XC4005 series -- we have hundreds fielded on MILITARY
> applications. However Xilinx newer tool suites Foundation/Alliance DO NOT
> support these legacy devices. So we are STUCK with maintaining an OLD
> machine with OLD Xilinx XACT software.

I feel for you, and every other company who is now in this trap thank
to Xilinx.  I think with Xilinx dropping Spartan, you really have to
wonder what their long term plans are.  Will we have one "stable"
version of software for each series?  Each version with it's own
interface, bugs and PC requirements?  Is this really what we expect
from a company who claims to be the best?

I had called Xilinx marketing to ask some of these questions, and like
the person I spoke to on the Hotline, they just don't have a clue what
the long term plans are.  Who is driving the ship?

Article: 57551
Subject: Looking for DIMM format FPGA board
From: eholbrook@austin.rr.com
Date: Wed, 02 Jul 2003 14:22:03 GMT
Links: << >>  << T >>  << A >>
I'm looking for a DIMM format FPGA board like Pilchard or the AcB from
(now defunct?) Nuron. I've done several web searches, but found
nothing that both fits the bill, and is from a company that is
apparently alive. I've found a couple of things that are close to what
i want (from mite.cz, and sunrise-systems.de), but they don't return
emails, so i figure they're dead, too.

Has anyone heard of something like this, or do i need to design/build
it myself?

Thanks in advance,
Eric

Article: 57552
Subject: Xilinx Methodology Questions : Unconstrained Paths and DLL output phase alignment.
From: "John Retta" <jretta@rtc-inc.com>
Date: Wed, 2 Jul 2003 08:24:33 -0600
Links: << >>  << T >>  << A >>
Hi
  I have two questions regarding Xilinx designs.

[1] How do I identify which paths the static timing analyzer considers
to be unconstrained?  This has been an ongoing, frustrating task for me.
I am an extreme advocate of synchronous design, and to discover that
I have 97.3% constraint coverage is disconcerting.  That means 2.7% are
unconstrained.  Clearly the tool has identified these paths, and if there
was a way to display them, this would be helplful in isolating problem
areas.

[2]  Where does Xilinx post rules for treating the multiple clock outputs
of DLLs as synchronous?  From various postings to the newsgroup, I
get the impression that an clk0 and clk divide by 2, should not be treated
as synchronous, but either there is a small phase offset which precludes
the assumption of edge alignment, or the PAR/TRC tools can not handle
setup/holdtime from the two domains.  However, I have not read any
formal limitations placed on these outputs appearing in either data sheets
or  application notes.

--
Regards,
John Retta

email : jretta@rtc-inc.com
web :  www.rtc-inc.com





Article: 57553
Subject: Re: Cyclone vs Spartan-3
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 02 Jul 2003 10:44:35 -0400
Links: << >>  << T >>  << A >>
David Brown wrote:
> 
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:3F027B39.A0E8DD68@yahoo.com...
> > "Steven K. Knapp" wrote:
> > >
> > > "rickman" <spamgoeshere4@yahoo.com> wrote in message
> > > news:3F00FDD2.C74022BD@yahoo.com...
> > > > "Nicholas C. Weaver" wrote:
> > > > That is a good point about the tools.  I forget that the XC3S is only
> > > > supported in webpack in the XC3S50 now and I think only up to the
> > > > XC3S400 in the next release.  I honestly don't get the idea of selling
> > > > very low cost chips and not adding them to the free tools.
> > >
> > > Personally, I agree with your statement and have been trying to convince
> the
> > > powers that be to add additional Spartan-3 devices to WebPack.  The
> folks
> > > responsible for WebPack are concerned about the total download size.
> The
> > > larger devices have multi-MB support files.
> >
> > If the size of the download is the issue, there are very simple ways to
> > address that.  One is to split the download into two parts, one for the
> > current configuration and one for the added support for the larger
> > devices.  The other is just to ship the CD as you already do.  I don't
> > think adding all the chips will blow away a CD will it?  As it is, I
> > don't think it is very practical to ask a user to download a 150 MB
> > file.  At least it is not practical for me to download it.
> >
> 
> There's little doubt that multiple optional download parts is the most
> elegant solution - along with the possiblity of getting everything on CD for
> those that want that.  However, the current WebPack is so large that a few
> extra megabytes for extra part support would not make a significant
> difference.  And anyway, are there many companies with the resources to be
> involved in fpga design, but without a permanent internet connection?  Even
> if it's a bit slow, you can always leave a download running overnight.

Overnight does not cut it.  As for the resources, it really does not
take a lot and a high speed internet connection is not even on the list
other than for this sort of download.  These files are so large that the
reliability of the connection becomes a significant factor.  The last
time I actually downloaded webpack, it took me about five trys and over
a week.  

I know there are tools that let you restart an interrupted download, but
even then it is a real chore getting a download completed.  I much
prefer to buy the CD.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 57554
Subject: Re: Cyclone vs Spartan-3
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Wed, 2 Jul 2003 14:45:02 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <omuMa.1725$zn2.469105682@twister1.starband.net>,
Steven K. Knapp <steve.knappNO#SPAM@xilinx.com> wrote:

>Personally, I agree with your statement and have been trying to convince the
>powers that be to add additional Spartan-3 devices to WebPack.  The folks
>responsible for WebPack are concerned about the total download size.  The
>larger devices have multi-MB support files.

Split the download, or switch the devcie files to be
download-on-demand or download-via-miniapp.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 57555
Subject: Combining Distributed RAM and Block RAM
From: muthu_nano@yahoo.co.in (Muthu)
Date: 2 Jul 2003 07:49:36 -0700
Links: << >>  << T >>  << A >>
Hi,

I need to use a memory with 37bits width. If I take a Block RAM
Primitive RAMB16_S36_S36, 36 bits can be utilised for storage (32bits
data + 4bits parity)

But I don't want to instantiate another Block RAM for a Single Bit.

I make it via register array based one. ie., 1 bit memory implemented
via FFs(say for 16 deep, i need 16 Flip-Flops)

I know that, the timings won't match. But it will not be a problem for
me since i am registering the memory output before using it.

Can any one point out any problems if any?

Thanks in advance.

Regards,
Muthu

Article: 57556
Subject: Re: Xilinx ISE drops support for more parts
From: buchty@atbode100.informatik.tu-muenchen.de (Rainer Buchty)
Date: Wed, 2 Jul 2003 14:53:54 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <9297c711.0307020605.49e00d63@posting.google.com>,
 lecroy7200@chek.com (lecroy) writes:
|> I had called Xilinx marketing to ask some of these questions, and like
|> the person I spoke to on the Hotline, they just don't have a clue what
|> the long term plans are.  Who is driving the ship?

Back in 96 I was working for another logic vendor; during that time the
parole was "we're a hardware company!", so the very own and reliable (DOS-)
software was dropped and a third party was hired to write the next
generation software.

They came up with a software which featured a nice, but nevertheless
completely new and unusual language -- and a fitter which was just utter
crap, especially when targeting the new "to be the new star" architecture. 
With the older architectures a similar problem arose, i.e. designs which 
easily fit into a device using the old software, required at least the next 
bigger device of the same series.

My quick hack was to write a translator which mapped the intermediate 
language (containing the flattened hierarchy) of the new software to the
language of the old software -- which in term didn't support all current
devices. Nevertheless, that translator was an instant success among "my"
customers.

About 1, 1.5 years later the new parole was "we're a software company!" as
somebody was struck by the blinding light of truth suddenly discovering that 
the best devices are worth nothing without an appropriate software and that 
at least a set of "reference fitters" should be supplied by the company.

Whoever was driving the ship back then, at least he finally got a clue (about 
1, 1.5 years later than the AEs and FAEs who thought it'd be a dumb idea 
anyway to outsource one of the most viable parts of the business).

Rainer

Article: 57557
Subject: Re: Xilinx ISE drops support for more parts
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 02 Jul 2003 11:06:04 -0400
Links: << >>  << T >>  << A >>
lecroy wrote:
> 
> JoeG <no@where.net> wrote in message news:<3F0219B6.8F56CB33@where.net>...
> > I've ask Xilinx the ? about legacy support for years -- I have the same
> > problem with XC4005 series -- we have hundreds fielded on MILITARY
> > applications. However Xilinx newer tool suites Foundation/Alliance DO NOT
> > support these legacy devices. So we are STUCK with maintaining an OLD
> > machine with OLD Xilinx XACT software.
> 
> I feel for you, and every other company who is now in this trap thank
> to Xilinx.  I think with Xilinx dropping Spartan, you really have to
> wonder what their long term plans are.  Will we have one "stable"
> version of software for each series?  Each version with it's own
> interface, bugs and PC requirements?  Is this really what we expect
> from a company who claims to be the best?
> 
> I had called Xilinx marketing to ask some of these questions, and like
> the person I spoke to on the Hotline, they just don't have a clue what
> the long term plans are.  Who is driving the ship?

It is real simple.  The FPGA marketplace is mainly between two players. 
So a maker can focus on a few aspects of the product to compete well in
the marketplace.  I don't expect that long term support in the tools is
a major issue with the majority of users at selection time and even if
it is, who else can you choose?  Is one really that much better than the
other?  My experience with the A vendor had one very bad example of tool
support for an older product.  It was still in the tool, but they
wouldn't consider a bug fix even when there was no viable work around. 
I don't mean to keep harping on this problem, but it was very signficant
to us and I now realize that there were a lot of ramifications other
than just the technical issue.  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 57558
Subject: Re: defparam LUT_4
From: Steven Elzinga <steven.elzinga@xilinx.com>
Date: Wed, 02 Jul 2003 09:38:35 -0600
Links: << >>  << T >>  << A >>
reposting in plain text

Kris,

The value E4E4 is the hex value in the LUT that is derived from a truth 
table:

inputs  | output
4 3 2 1 | out
-------------
0 0 0 0 | 0
0 0 0 1 | 0
0 0 1 0 | 1
0 0 1 1 | 0
0 1 0 0 | 0
0 1 0 1 | 1
0 1 1 0 | 1
0 1 1 1 | 1
:
:

The first 8 output bits that are listed ->  1 1 1 0 0 1 0 0 is a hex 
value of E4.

Steve


kris wrote:

>Hi all,
>If you look at the mapped netlist then the lut's are defined as
>defparam NameOfLut.INIT=16'hE4E4;
>does anybody know how the INIT defines the functionality of the LUT. In
>other words
>what does E4E4 mean?
>Kris
>
>
>  
>


Article: 57559
Subject: Re: Xlilin xc9572XL Default register values
From: Steven Elzinga <steven.elzinga@xilinx.com>
Date: Wed, 02 Jul 2003 09:42:40 -0600
Links: << >>  << T >>  << A >>
reposting in plain text

Ralph,

Sorry for the delay in my response.  I tried the code below with ISE 
5.2i sp3 targeting a 9572:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity inits is
        Port ( d : in std_logic;
               c : in std_logic;
               q : out std_logic);
    end inits;

    architecture inits_arch of inits is

    signal q_temp : std_logic := '1';

    begin

    process (c) is begin
    if c'event and c = '1' then

    q_temp <= d;

    end if;
    end process;

    q <= q_temp;

    end inits_arch;

The register had the INIT value of '1' attached to it.  I then tried the 
below code with record types:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity inits is
        Port ( d1 : in std_logic_vector (4 downto 0);
               d2 : in std_logic_vector (4 downto 0);
               c : in std_logic;
               q1 : out std_logic_vector (4 downto 0);
               q2 : out std_logic_vector (4 downto 0));
    end inits;

    architecture inits_arch of inits is

    type v_reg_type is record
            -- registers
            IOLatch     :   std_logic_vector(4 downto 0);
            IOLatch2     :   std_logic_vector(4 downto 0);
        end record;

    signal d_temp : v_reg_type;
    signal q_temp : v_reg_type := (IOLatch => "11111", IOLatch2 => "11111");

    begin

    process (c) is begin
    if c'event and c = '1' then

    q_temp <= d_temp;

    end if;
    end process;

    d_temp.IOLatch <= d1;
    d_temp.IOLatch2 <= d2;

    q1 <= q_temp.IOLatch;
    q2 <= q_temp.IOLatch2;

    end inits_arch;

The registers did not get initialized in 5.2i sp3 or in our next version 
of the software.  I will file a bug report on this.

As for your version of webpack not working please try the latest 
version.  If the register is still not initializing as suspected (not 
using record types that is) please contact the hotline.

thanks

Steve


Ralph Mason wrote:

>"Steven Elzinga" <steven.elzinga@xilinx.com> wrote in message
>news:3EFC59CE.8090103@xilinx.com...
>  
>
>>Ralph,
>>
>>Another method (aside from passing an INIT) is to initialize the signal
>>that will be registered:
>>
>>library ieee;
>>ues ieee.std_logic_1164.all;
>>
>>entity ff is
>>port (d, c : in std_logic;
>>      q : out std_logic);
>>end entity;
>>
>>architecture ff_arch of ff is
>>signal q_temp : std_logic := '0';  -- XST will pass the proper INIT
>>value based off of the signal initialization
>>                                   -- This INIT value is the state to
>>which the register will power up
>>                                   -- q_temp is the signal that will be
>>registered
>>begin
>>:
>>:
>>
>>
>>Steve
>>
>>    
>>
>
>Hi Steve,
>
>With webpack 5.1 this doesn't seem to work at all. Doing this and then
>looking at the report file there is no change in the init states of the
>registers do not change at all.
>
>Taking the inferred net names from the synthesis report and using a
>constraints file worked fine though.
>
>Any ideas why your approach wouldn't work for me?  Perhaps I am doing
>something wrong?
>
>Thanks
>Ralph
>
>
>  
>


Article: 57560
Subject: Re: Xilinx Methodology Questions : Unconstrained Paths and DLL output phase alignment.
From: "John_H" <johnhandwork@mail.com>
Date: Wed, 02 Jul 2003 15:45:42 GMT
Links: << >>  << T >>  << A >>
You have the option within the Timing Analyzer tool (I use the GUI, I'm sure
there's a command line switch) to find your unconstrained paths.  Rather
than hitting the square clock-like button labeled "Analyze against Timing
Constraints," use the menu to select "Analyze" and "Against Timing
Constraints..." to bring up the options that you can apply to your analysis.

On the first of the four tabs, you can check the "Report unconstrained
paths" box to get some or all of your unconstrained paths.  No fuss, no
muss.


"John Retta" <jretta@rtc-inc.com> wrote in message
news:bduq1r$o3u$1@slb5.atl.mindspring.net...
> Hi
>   I have two questions regarding Xilinx designs.
>
> [1] How do I identify which paths the static timing analyzer considers
> to be unconstrained?  This has been an ongoing, frustrating task for me.
> I am an extreme advocate of synchronous design, and to discover that
> I have 97.3% constraint coverage is disconcerting.  That means 2.7% are
> unconstrained.  Clearly the tool has identified these paths, and if there
> was a way to display them, this would be helplful in isolating problem
> areas.
>
> [2]  Where does Xilinx post rules for treating the multiple clock outputs
> of DLLs as synchronous?  From various postings to the newsgroup, I
> get the impression that an clk0 and clk divide by 2, should not be treated
> as synchronous, but either there is a small phase offset which precludes
> the assumption of edge alignment, or the PAR/TRC tools can not handle
> setup/holdtime from the two domains.  However, I have not read any
> formal limitations placed on these outputs appearing in either data sheets
> or  application notes.
>
> --
> Regards,
> John Retta
>
> email : jretta@rtc-inc.com
> web :  www.rtc-inc.com
>
>
>
>



Article: 57561
Subject: Re: Why not DDR in FPGAs?
From: "John_H" <johnhandwork@mail.com>
Date: Wed, 02 Jul 2003 15:54:46 GMT
Links: << >>  << T >>  << A >>
The technique has been around for years.  The "dual edge flip-flop" was
introduced (by lattice?  It's been a while) before I even know what DDR was.
The Xilinx CoolRunner also has the dual-edge option that they might refer to
as an integrated clock doubler.

In my personal opinion, while it might be "nifty" to have the capability in
the slices and LEs, the coding required to get that functionality in my HDL
might be too awkward.  While the concept of a verilog

  always @(posedge HalfClk or negedge HalfClk)   or    always @(HalfClk)

might give the conceptual results we desire, getting the synthesis to come
out right could be a completely different matter.  I'd be interested to hear
if there is successful dual-edge synthesis for the existing devices with
dual-edge registers or DDR IOB registers.


"itsme" <itsme@gmx.de> wrote in message
news:bdud1q$enh$02$1@news.t-online.com...
> Hi all,
> here is a quit simple, general question:
> Why do the FPGAs (as fare as I know) not use Double Data Rate on Chip for
> their FlipFlips?
> + This would reduce the power for the clock tree.
> + I could directly use the Data from an external DDR-DRAM
>
>
>



Article: 57562
Subject: Re: ASIC divider in FPGA?
From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Date: Wed, 02 Jul 2003 16:21:20 GMT
Links: << >>  << T >>  << A >>

"H. Peter Anvin" <hpa@zytor.com> wrote in message
news:bdr4h8$2p1$1@cesium.transmeta.com...
> Followup to:  <vfv8tlhpgtpk57@corp.supernews.com>
> By author:    "Jerry" <nospam@nowhere.com>
> In newsgroup: comp.arch.fpga
> > >
> > > I come from the ASIC side, and I have
> > > > something in verilog like: assign Z = (a[15:0] / b[9:0]); and I get
an
> > > > error saying the divisor must be a power of 2.  Looking around, it
> > > > seems that this cannot be implemented into HW??
> > >
> > > The limitation is with your synthesis tool, not the capabilities of
FPGA.
> > >
> > > > Any advice is appreciated.
> > >
> > > Buy a good book on computer arithmetic and implement the
> > > operation yourself
> > > (or alternatively search a bit hardware around the web and you're
bound to
> > > find some example code). Don't expect the resultant hardware to be
small.

> > To expand on what JonB said, there is a trade off between gate count and
> > number of clock cycles required to perform the operation.

> To further expand...

> Something that reads in Verilog like what you have above is
> all-combinatorial logic, meaning no loops and no latches.  Not even
> microprocessors usually have combinatorial dividers, because of the
> sheer amount of area required; you may want to see if you can't use a
> clocked design instead.  Common designs are 1, 2 or 4 bits per clock.

Algorithms like that used in the IBM 360/91 or Cray-1 could be implemented
as combinatorial dividers.   An iterative algorithm like the 360/91, or
fully pipelined like the Cray-1 could also be implemented depending on the
required speed and available clock.

Possibly implemented in combination with the block RAM a reasonably
efficient implementation might be possible.

-- glen



Article: 57563
Subject: Re: Everything need a reset?
From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Date: Wed, 02 Jul 2003 16:21:20 GMT
Links: << >>  << T >>  << A >>

"Jay" <yuhaiwen@hotmail.com> wrote in message
news:bde3rr$rs8gp$1@ID-195883.news.dfncis.de...
> always @ (posedge(clkin))
>         clkout <= ~clkout;
>
> above is a single clk_div module, but when I do simulation, I can't get it
> work.
> I know the reason. without a reset signal to give it a initial value of
'0'
> or '1', the clkout will keep the value 'x' during simulation.
> but there's no 'x' in FPGA or CPLD, the clkout will get whatever a value
> after power up, and it can get work without additional reset.

There are designs that in reality don't need a reset, but do in simulation.
Others need a reset in both cases.

-- glen



Article: 57564
Subject: Re: Does anyone know about hardware implementaions of the SVD ?
From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Date: Wed, 02 Jul 2003 16:21:20 GMT
Links: << >>  << T >>  << A >>

"Aziz AhmedSaid" <a.ahmedsaid@qub.ac.uk> wrote in message
news:bdp4ia$juk$1@news.qub.ac.uk...
> Hi,
> I'm a student in computer science and I'm working on the Singular Value
> Decomposition. I have implementd the Brent Luk Van Loan SVD systolic array
> using HandelC on FPGA and I'm looking for existing FPGA or VLSI
> implementations to compare with.
> Does anyone know about hardware implementaions of the SVD ?

Doing floating point in an FPGA is pretty expensive (in terms of CLBs used).
I do wonder how big your array is?

-- glen



Article: 57565
Subject: Discrepancy in CLB Usage Report
From: Anand P Paralkar <anandp@sasken.com>
Date: Wed, 2 Jul 2003 21:59:06 +0530
Links: << >>  << T >>  << A >>
Hi,

I am using the following flow:

   VHDL - Entry
   Synplify Pro - Synthesis
   Xilinx Design Manager - Post synthesis, place and route, etc.

The target device is Xilinx Spartan XL - XCS20XL.

I am trying to understand the two summaries:

  1. Synthesis Summary
  --------------------
  Logic Mapping Summary:
  FMAPs: 243 of 392 (62%)
  HMAPs: 83 of 196 (43%)
  Total packed CLBs: 173 of 196 (89%)                  <-*-*-*-
  (Packed CLBs is determined by the larger of three quantities:
  Registers / 2, HMAPs, or FMAPs / 2.)

  2. Xilinx Design Manager Summary
  --------------------------------
  Design Summary:
  Number of errors:        1
  Number of warnings:      6
  Number of CLBs:            250 out of   196  127%    <-*-*-*-
  CLB Flip Flops:     346
  CLB Latches:          3
  4 input LUTs:       246
  3 input LUTs:       230 (147 used as route-throughs)
  Number of bonded IOBs:      48 out of   112   42%
  IOB Flops:           34
  IOB Latches:          0
  Number of clock IOB pads:    4 out of     8   50%
  Number of TBUFs:             2 out of   448    1%
  Number of BUFGLSs:           4 out of     8   50%
  32 unrelated functions packed into 31 CLBs.
  (12% of the CLBs used are affected.)
Total equivalent gate count for design: 4178
Additional JTAG gate count for IOBs:    2304
-------------------------------------------------------------------

Why is there a discrepancy between the Number of CLBs reported
by the synthesis tool (173) and the Xilinx design manager (250)?

As you would observe, the design manager reports an error due
to the excess usage of CLBs.  As a result the flow does not proceed
to Place and Route etc.  Any suggestions?

Thank you for your time.

Thanks,
Anand


Article: 57566
Subject: Re: How to get 27MHz from 10 MHz in FPGA???
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 02 Jul 2003 09:33:55 -0700
Links: << >>  << T >>  << A >>
Yes you could "pre-multiply", but that involvs extra circuitry. And a
doubler generates frequency modulation, if it is done by differentiation
both incoming edges. It's much nicer to be able to forget all problems
and have the DCM "just do it".
Peter Alfke
==================
Glen Herrmannsfeldt wrote:
> If you needed a lower frequency couldn't you always generate a power of two
> multiple of it, and then divide that down?
> 
> -- glen

Article: 57567
Subject: Re: Why not DDR in FPGAs?
From: "Erik Widding" <widding@birger.com>
Date: Wed, 02 Jul 2003 16:39:05 GMT
Links: << >>  << T >>  << A >>
"John_H" <johnhandwork@mail.com> wrote in message
news:afDMa.18$C_4.5194@news-west.eli.net...
> The Xilinx CoolRunner also has the dual-edge option that they might refer
to
> as an integrated clock doubler.
>
>.  I'd be interested to hear
> if there is successful dual-edge synthesis for the existing devices with
> dual-edge registers or DDR IOB registers.


I have not tried this with Synplicity yet.  With XST the Coolriunner dual
edge flip flop is inferred with the following VHDL construct:

   process(vclk)
   begin
      if (vclk'event) then
               ...
      end if;
   end process;

Which is exactly as one would expect.  To get this inference to work, if
running XST with a script, the part type has to be set to XBR rather than
XC2C64 (as one would expect from the documentation).  The flow engine sets
the part type correctly.


Regards,
Erik Widding.


---
Birger Engineering, Inc. -------------------------------- 617.695.9233
100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com



Article: 57568
Subject: Re: PCB Problem
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 02 Jul 2003 16:39:23 -0000
Links: << >>  << T >>  << A >>
>The problem is the output of the PBGA seem to be producing a 1HZ pulse
>which is expected when the 28V is on but not expected when the 28V is
>turned off. The 1HZ pulse has a amplitude of 2V when the 28V is off
>but when the 28V is on, the amplitude is 5V.

>I have tested the power supply stand-alone and it works perfectly.
>When the 28V is off, the PBGA power should be zero but in this case,
>the voltage is 1.4V when connected to the PCB.

What's the voltage on your supply rails/planes on the side
that you expect to be off?

My guess is that you have some signals going from the
expect-to-be-on section to the expect-to-be-off section,
and the protection diodes are kicking in and connecting the
energy from the signals to the power rail and there is enough
power getting through for the logic to start to work.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 57569
Subject: Re: why so many problems Xilinx ?
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 02 Jul 2003 09:44:27 -0700
Links: << >>  << T >>  << A >>

rickman wrote:
> Often vendors don't want to seem like they are hawking their wares
> here. 
 
I can guarantee you that neither Xilinx nor Altera harbors this kind of
girlish modesty.
But we must consider the audience, and avoid the BS.

I definitely will hawk the capabilities of the Virtex-II DCM and MGTs if
anybody ever asks for a related functionality. That's my job, and that's
what this ng is for, isn't it?
Peter Alfke

Article: 57570
Subject: Re: Xilinx Methodology Questions : Unconstrained Paths and DLL output phase alignment.
From: Philip Freidin <philip@fliptronics.com>
Date: Wed, 02 Jul 2003 16:54:59 GMT
Links: << >>  << T >>  << A >>
On Wed, 2 Jul 2003 08:24:33 -0600, "John Retta" <jretta@rtc-inc.com> wrote:
>Hi
>  I have two questions regarding Xilinx designs.
>
>[1] How do I identify which paths the static timing analyzer considers
>to be unconstrained?  This has been an ongoing, frustrating task for me.
>I am an extreme advocate of synchronous design, and to discover that
>I have 97.3% constraint coverage is disconcerting.  That means 2.7% are
>unconstrained.  Clearly the tool has identified these paths, and if there
>was a way to display them, this would be helplful in isolating problem
>areas.

If you are using TRCE from the command line, it is the "-u xxx" option.
Also available in the GUI.

This adds a new section to the report (after all the normal timespec
sections), that lists unconstrained paths. You then play whack-a-mole
writing new time specs and re-running place/route/trce to make this
section of the report shorter and shorter, until hopefully you get it
to be empty.

Tragically you can get a situation where this section is empty, but
the coverage is still reported as not 100%. Xilinx waves its hands and
says that these are paths that can't/dont need to be constrained, such as
GND and VCC nets, and not to worry.   ... I do  ...

Sorry, I dont have an answer for your second question.

Philip



Philip Freidin
Fliptronics

Article: 57571
Subject: Re: why so many problems Xilinx ?
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 02 Jul 2003 10:00:05 -0700
Links: << >>  << T >>  << A >>
Paul, nobody would ever claim that it is easy to answer technical
questions in an open forum, be accurate and maintain some decorum with
respect to the competition. 
But I think it's worth the try, and it benefits your employer in the end.

Talking about your employer, I appreciate that you "came out of the
closet" and now sign off (usually, but not this time) as an Altera employee.

Peter Alfke, Xilinx Applications Engineering
====================================
Paul Leventis wrote:
> 
> > I cannot understand that at all. If the question is ventilated in
> > public, it should be answered in public. Unless the answer is very
> embarrassing...
> 
> Embarrassment has nothing to do with it.  I personally think that this
> newsgroup is the wrong place to attack the competitor's products -- in
> general, I think both X & A are pretty well behaved, pointing out our strong
> points instead of directly pointing out weaknesses in our competitor's
> products.  In a personal email, there is much more freedom to say what I
> feel like and to venture off into opinion from fact.  Plus, if I'm not 100%
> sure, I can just say so and follow-up later when I find out the full answer;
> in the newsgroup, you can look pretty silly when you do so (speaking from
> experience...).
> 
> Most of us who post here from Altera are in the R&D side of the company, so
> we're usually unaware of product positioning or the "company line" on
> certain issues.  When in doubt, I rather just reply offline while I wait for
> a response from the apps folks.
> 
> Regards,
> 
> Paul

Article: 57572
Subject: Re: FPGA Editor and Xilinx ISE 5.1i
From: Chen Wei Tseng <chenwei.tseng@xilinx.com>
Date: Wed, 02 Jul 2003 11:44:26 -0600
Links: << >>  << T >>  << A >>
Hi Santi,

Since 5.x version, FPGA Editor no longer support hard macro containing Vcc comps. What you'll have to do is
declear pins that connects to Vcc as external macro pin and connect the pin to Vcc or '1' in your source
code.

Regards, Wei

Santi wrote:

> Hi all!
>
> I'm trying to make a hard macro of a design and I got that error:
>
> FATAL_ERROR:Ncd:basncmacrodef.c:1466:1.19.2.1 - Mangled nmc file
>  start property read <0xffffcacc>
>
> Seems like the FPGA Editor tool has problems with POWER and GND
> connections
> (see former post http://groups.google.com/groups?selm=72480649.0210271033.535836f4%40posting.google.com)
>
> In my case, that gnd/pwr connections are inferred by the synthesis
> tool, and it's not easy to get rid of them.
>
> My question is if this problem is solved in the ISE 5.2 version? Does
> it worth to upgrade the tool? Other ideas of overcome this problem?
> Are there anyone having the same problem?
>
> Thanks,
>
> Santi
>
> ------------------------------------
> Santiago Esteban Zorita
> Electric and Electronic Engineering dept.
> University of Strathclyde
> santi@eee.strath.ac.uk
> ------------------------------------


Article: 57573
Subject: Re: Looking for DIMM format FPGA board
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Wed, 2 Jul 2003 18:07:31 +0000 (UTC)
Links: << >>  << T >>  << A >>

<eholbrook@austin.rr.com> wrote in message
news:874r24dalp.fsf@vole.holby-net...
> I'm looking for a DIMM format FPGA board like Pilchard or the AcB from
> (now defunct?) Nuron. I've done several web searches, but found
> nothing that both fits the bill, and is from a company that is
> apparently alive. I've found a couple of things that are close to what
> i want (from mite.cz, and sunrise-systems.de), but they don't return
> emails, so i figure they're dead, too.
>
> Has anyone heard of something like this, or do i need to design/build
> it myself?

I was thinking of developing one. How about us collaborating?

Leon
-- 
Leon Heller, G1HSM
leon_heller@hotmail.com
http://www.geocities.com/leon_heller



Article: 57574
Subject: Re: Fixed point signed multiplication algorithm
From: Terje Mathisen <terje.mathisen@hda.hydro.com>
Date: Wed, 02 Jul 2003 20:26:18 +0200
Links: << >>  << T >>  << A >>
praveen wrote:

> Hello,
> I am implementating Fixed point signed multiplication. Is there a
> algorithm to implement it. I have done the usual method of
> multiplication i.e partial products ...shift and add method. But its
> very slow. If you know any algorithm which will faster do mention. Any
> reference will be great. How does the signed multipliers in xilinx
> that fast. what algorithm do they use. I need to first implement in on
> MATLAB and see the result.

Do you need the full (double-wide) result, or just the lower N bits of 
an NxN bit imul?

The fastest pure sw method I know (for relatively small values of N) is 
to use branchless conversion to absolute values, do the multiplication 
via a lookup table of squares, and then a branchless fixup of the sign 
at the end.

Terje

-- 
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"




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