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Hello All, I have started using Xilinx Spartan3E 1600E Microblaze Development Board and want to use its RS232 facility in my project. This board has two RS232 connectors but I cannot figure out what UART it uses. I was searching for UART chip on the board (I was actually searching for a MAXIM chip) and have seen none. The Xilinx board's manual (ug257) does not say what particular UART is present on the board and just mention some MAXIM chip but where it is on board? The manual (ug257) also specifies connection between particular FPGA and RS232 pins on this board: for DTE NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ; NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; and for DCE NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ; NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;Article: 145226
Alex <victous@gmail.com> wrote: > I have started using Xilinx Spartan3E 1600E Microblaze Development > Board and want to use its RS232 facility in my project. This board has > two RS232 connectors but I cannot figure out what UART it uses. I was > searching for UART chip on the board (I was actually searching for a > MAXIM chip) and have seen none. It would be unusual to put a UART on an FPGA development board. You should implement one in the FPGA logic. For ethernet, they put the PHY on board, as that is hard to do in the FPGA (too much analog and/or fast circuitry), but the MAC is normally done inside the FPGA. The RS232 level shift/buffers should be on the board, though. -- glenArticle: 145227
On 2 =D1=84=D0=B5=D0=B2, 09:14, glen herrmannsfeldt <g...@ugcs.caltech.edu>= wrote: > Alex <vict...@gmail.com> wrote: > > I have started using Xilinx Spartan3E 1600E Microblaze Development > > Board and want to use its RS232 facility in my project. This board has > > two RS232 connectors but I cannot figure out what UART it uses. I was > > searching for UART chip on the board (I was actually searching for a > > MAXIM chip) and have seen none. > > It would be unusual to put a UART on an FPGA development board. > > You should implement one in the FPGA logic. > > -- glen I also had this thought until had noticed that MAXIM UART device is mentioned on page 61 of ug257: The FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device, which in turn, converts the logic value to the appropriate RS-232 voltage level. Likewise, the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. A series resistor between the Maxim output pin and the FPGA=E2=80=99s RXD pin protects against accidental logic conflicts. I am really puzzled!Article: 145228
General Schvantzkoph <schvantzkoph@yahoo.com> writes: >> just a small decision to make: open up Xilinx USB Cable API, that is all >> that Xilinx would have todo. Yes, this also takes resources as it may I would rather see some standard generic API as I've made an Ethernet based programmer. I can program Xilinx and Altera FPGA's, microcontrollers, flash, etc. directly or indirectly using this programmer, but I can't run SignalTap and ChipScope. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 145229
On 1 Feb., 13:33, "bellatoise" <arianapo...@gmail.com> wrote: > Hi, > > My query is the next: > I'm working with Xilinx Ise Design Suite 11.1. > I need some ROMS with differents values of depth, width and initializatio= n > files that I want to instantiate in one proyect. I need a generic ROM, so= I > created one with Core Generator and I got its HDL code =A0using View HDL > functional Model. > Then I introduced the values of width, depth and initialization file like > generics values. In the proyect, I generated the ROMS intantiating this H= DL > code, each one with differents values. > > When I sintetize the proyect appears some warnings like those: > WARNING:Xst:616 - Invalid property "archivo_inic CUATR.mif": Did not atta= ch > to Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. > WARNING:Xst:616 - Invalid property "depth 3": Did not attach to > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. > WARNING:Xst:616 - Invalid property "width 8": Did not attach to > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int. > > Is there another way to get a ROM with Core Generator so that it can be > instantiated in the proyect and form there I can generate differents ROMs > since te core that I created with differents the values of width, depth a= nd > =A0 initialization file?? > > Thank you > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com don't know whether that helps you, but you can easily generate any ROM using vMAGIC, look at the demo page on http:// vmagic.sf.netArticle: 145230
On 30 Jan., 19:34, "zanaticul" <cosminc...@yahoo.com> wrote: > i was thinking of using this code > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 tmp :=3D number; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 o4 :=3D number mod 10; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 tmp :=3D tmp-o4; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 o3 :=3D number mod 100; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 tmp :=3D tmp-o3; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 o3 :=3D o3/10; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 o2 :=3D number mod 1000; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 tmp :=3D tmp-o2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 o2 :=3D o2/100; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 o1 :=3D number /1000; =A0 =A0 > > but i get an error: ERROR:HDLParsers:808 - > "D:/Work/fpga/projects/stopWatch/nr.vhd" Line 53. * can not have such > operands in this context. And which line is line 53? I can't see any "*" in the code you presented. Kolja SulimmaArticle: 145231
In comp.arch.fpga,
Alex <victous@gmail.com> wrote:
> On 2 фев, 09:14, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
>> Alex <vict...@gmail.com> wrote:
>> > I have started using Xilinx Spartan3E 1600E Microblaze Development
>> > Board and want to use its RS232 facility in my project. This board has
>> > two RS232 connectors but I cannot figure out what UART it uses. I was
>> > searching for UART chip on the board (I was actually searching for a
>> > MAXIM chip) and have seen none.
>>
>> It would be unusual to put a UART on an FPGA development board.
>>
>> You should implement one in the FPGA logic.
>>
>> -- glen
>
> I also had this thought until had noticed that MAXIM UART device is
> mentioned on page 61 of ug257:
>
> The FPGA supplies serial output data using LVTTL or LVCMOS levels to
> the Maxim device,
> which in turn, converts the logic value to the appropriate RS-232
> voltage level. Likewise,
> the Maxim device converts the RS-232 serial input data to LVTTL levels
> for the FPGA. A
> series resistor between the Maxim output pin and the FPGA’s RXD pin
> protects against
> accidental logic conflicts.
>
> I am really puzzled!
That's because you snipped the last line of Glen's reply:
>> The RS232 level shift/buffers should be on the board, though.
The 'Maxim' chip _is_ the level shifter. Should be something like a
MAX232 (google for that). But it will probably be a low voltage version
like the MAX3221 or a simular chip from another manufacturer.
So the UART is in the FPGA, the level shifter ("Maxim") outside. Isn't
there a schematic in the user guide?
--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)
The soul would have no rainbow had the eyes no tears.
Article: 145232Alex <victous@gmail.com> wrote: > On 2 ???, 09:14, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: >> Alex <vict...@gmail.com> wrote: >> > I have started using Xilinx Spartan3E 1600E Microblaze Development >> > Board and want to use its RS232 facility in my project. This board has >> > two RS232 connectors but I cannot figure out what UART it uses. I was >> > searching for UART chip on the board (I was actually searching for a >> > MAXIM chip) and have seen none. >> It would be unusual to put a UART on an FPGA development board. >> You should implement one in the FPGA logic. > I also had this thought until had noticed that MAXIM UART device is > mentioned on page 61 of ug257: It is just a level converter. The MAXIM MAX3232 device is popular as it needs only +3.3V power, not the +/-12V used by most RS232 level converters. The MAX232 I used to know uses +5V, it seems that there is now a 3.3V version. The capacitors are used to generate the required voltages. -- glenArticle: 145233
Stef <stef33d@yahooi-n-v-a-l-i-d.com.invalid> wrote:
> In comp.arch.fpga,
> Alex <victous@gmail.com> wrote:
>>> > I have started using Xilinx Spartan3E 1600E Microblaze Development
>>> > Board and want to use its RS232 facility in my project. This board has
>>> > two RS232 connectors but I cannot figure out what UART it uses. I was
>>> > searching for UART chip on the board (I was actually searching for a
>>> > MAXIM chip) and have seen none.
(snip)
>> The FPGA supplies serial output data using LVTTL or LVCMOS
>> levels to the Maxim device, which in turn, converts the
>> logic value to the appropriate RS-232 voltage level. Likewise,
>> the Maxim device converts the RS-232 serial input data to LVTTL
>> levels for the FPGA.
(snip)
> That's because you snipped the last line of Glen's reply:
>>> The RS232 level shift/buffers should be on the board, though.
> The 'Maxim' chip _is_ the level shifter. Should be something like a
> MAX232 (google for that). But it will probably be a low voltage version
> like the MAX3221 or a simular chip from another manufacturer.
I believe it is the same board as the Spartan3E board, but with
a larger, pin compatible, FPGA.
> So the UART is in the FPGA, the level shifter ("Maxim") outside. Isn't
> there a schematic in the user guide?
See UG230.pdf I believe the MAX3232.
He has the microblaze manual, but that doesn't say much about
the rest of the board.
-- glen
Article: 145234>On 2 =D1=84=D0=B5=D0=B2, 09:14, glen herrmannsfeldt <g...@ugcs.caltech.edu>= > wrote: >> Alex <vict...@gmail.com> wrote: >> > I have started using Xilinx Spartan3E 1600E Microblaze Development >> > Board and want to use its RS232 facility in my project. This board has >> > two RS232 connectors but I cannot figure out what UART it uses. I was >> > searching for UART chip on the board (I was actually searching for a >> > MAXIM chip) and have seen none. >> >> It would be unusual to put a UART on an FPGA development board. >> >> You should implement one in the FPGA logic. >> >> -- glen > >I also had this thought until had noticed that MAXIM UART device is >mentioned on page 61 of ug257: > >The FPGA supplies serial output data using LVTTL or LVCMOS levels to >the Maxim device, >which in turn, converts the logic value to the appropriate RS-232 >voltage level. Likewise, >the Maxim device converts the RS-232 serial input data to LVTTL levels >for the FPGA. A >series resistor between the Maxim output pin and the FPGA=E2=80=99s RXD pin >protects against >accidental logic conflicts. > >I am really puzzled! > > A logic-level <-> RS232 converter is not a UART. It is a PHY. As other posters have said, you put the UART (roughly equivalent to a MAC) into the FPGA, using a process known as "digital design". If you only need one line speed, drop the 'U', and design an 'ART'. HTH! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145235
Alex <victous@gmail.com> writes: > The FPGA supplies serial output data using LVTTL or LVCMOS levels to > the Maxim device, which in turn, converts the logic value to the > appropriate RS-232 voltage level. Likewise, the Maxim device > converts the RS-232 serial input data to LVTTL levels for the FPGA. > A series resistor between the Maxim output pin and the FPGA¢s RXD > pin protects against accidental logic conflicts. > I am really puzzled! Why? What you quoted does not mention a UART, what they describe is a bog standard level shifter. I'm not sure if my board is the same as yours, I have a "Spartan 3E 1600 Board" from Digilent, but I think it's the same. The schematic for it shows a MAX3232 connected to the serial ports, which is exactly that, a level shifter. Not a UART.Article: 145236
On Mon, 1 Feb 2010 23:01:47 -0800 (PST), Alex <victous@gmail.com> wrote: |Hello All, | |I have started using Xilinx Spartan3E 1600E Microblaze Development |Board and want to use its RS232 facility in my project. This board has |two RS232 connectors but I cannot figure out what UART it uses. I was |searching for UART chip on the board (I was actually searching for a |MAXIM chip) and have seen none. |The Xilinx board's manual (ug257) does not say what particular UART is |present on the board and just mention some MAXIM chip but where it is |on board? | |The manual (ug257) also specifies connection between particular FPGA |and RS232 pins on this board: |for DTE | |NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ; |NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | |SLEW = SLOW ; | |and for DCE | |NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ; |NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | |SLEW = SLOW ; | |----------------- The board is made by Digilent Inc for Xilinx and is sold on Digilent's web page also. The Max part is MaX3232 per the schematic. jamesArticle: 145237
Alex <victous@gmail.com> wrote: > I have started using Xilinx Spartan3E 1600E Microblaze Development > Board and want to use its RS232 facility in my project. This board has > two RS232 connectors but I cannot figure out what UART it uses. I was > searching for UART chip on the board (I was actually searching for a > MAXIM chip) and have seen none. The data sheet for the MAXIM MAX3232, MAX3222-MAX3241.PDF gives much detail including a picture of the die of the MAX3222. I believe it includes some fairly large (for modern digital IC) transistors. The total transistor count is 339. Download from maxim-ic.com -- glenArticle: 145238
On Feb 1, 5:38=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Hello, > > is there a way to constrain minimum hold time requirements with ISE? > > I am trying to write to an FT2232H in synchronous FIFO mode. The FT2232H > supplies a 60 MHz clock and specifies 11 ns setup and 0 ns hold. As the > FT2232H supplied clock can stop, using a DCM to retime the clock will at > least require the DCM to stabilize each time and so to wait when the > transmission is initiated. > > So only with the FT2232H on a global clock, all outputs using the PAD > registers and with a XC200A and LVCMOS25/12mA/Fast slew drive TICKOF is 5= .24 > ns and timing can be met (16.666 -5.24 =3D 11.42 > 11). > > However this eats up simultaneous switching margins, and more my test boa= rd > uses 3.3V and the clock is on a LHCLK, not reaching all outputs. > > Another way would be to clock out data on the negative edge with input de= lay > on the clock and a slow drive. If I could constrain half a clock period h= old > time, the 0 ns hold requirement of the FT2232h could be met. > > Is there a way to do so? > > Any other ideas? I'm not clear about your problem exactly. It looks like your system meets the setup time of the FT2232H chip. The hold time requirement is 0, so that is met for sure unless you have clock routing problems. If your clock is on the wrong input, there is not much you can do about that. I am pretty sure you will not find a real way to meet a half clock time hold and not blow the setup time. In fact, I don't really see where you are headed with this. BTW, where did you get the 5.24 ns value? My concern is that the calculation of this time is a bit messy requiring you go add more than one offset to a base value as determined by the I/O modes. Did you do all of that? RickArticle: 145239
james <bubba@bud.u> writes: > The board is made by Digilent Inc for Xilinx and is sold on Digilent's > web page also. > > The Max part is MaX3232 per the schematic. Interestingly, now that I looked, mine actually has an ST3232 :) But undoubtedly functionality is the same as MAX3232.Article: 145240
Uwe Bonnes wrote: > > Any other ideas? > If the FPGA pin driving the FT2232H WR# pin is within your LHCLK domain, how about making WR# the only FAST output pin, and then enable writes on every other clock cycle. This would cut your transfer rate to 30 Mbytes/sec max into the fifo, but give you two clocks of setup for the data lines. ( I've never used the FT2232H; the data sheet mentions a max transfer rate >= 25 MB/s in synchronous mode, and it looks like you have to monitor the TXE# line to stall writes if the FT2232H isn't ready. ) > > Another way would be to clock out data on the negative edge with input delay > on the clock and a slow drive. If I could constrain half a clock period hold > time, the 0 ns hold requirement of the FT2232h could be met. > > Is there a way to do so? I would not recommend this scheme. With a 16.67 ns clock period, starting at the falling edge you'd need to delay the data outputs at least 8.33 ns ( to meet the hold time ) but no more than 8.33 + ( 16.67 - 11 )= 14 ns to meet the next clock's setup time. So you'd need to hold your I/O's switching time to be within a 5.67 ns absolute window, whilst using slow I/O's with no DLL in the clock tree. BrianArticle: 145241
Dear Sir/Madam, I have already tried with the output port, but the result is exactly the same. Thank you. On Feb 2, 10:43 am, Antti <antti.luk...@googlemail.com> wrote: > any designs with NO OUTPUT ports will be considered EMTPY designs > so EVERYTHING is optimized away what leads to error message. > > AnttiArticle: 145242
On Mon, 1 Feb 2010 21:28:38 -0800 (PST), Daku <dakupoto@gmail.com> wrote: ... Before you try to synthesize anything, you should first simulat what you wrote (or what a tool generated for you?) Your module has no outputs (but a port named outtail, typo?) so all logic (including your clock signal) will be removed. If you put this module in a testbench and try to get to what ever it's calculating you will figure this out very quickly. Also the coding style of the module is quite error-prone. Invest some time in learning how to write synthesizable rtl for the time you'll actually do synthesis so that you won't have to revise all your code after you think you're done typing. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 145243
"Anssi Saari" <as@sci.fi> schrieb im Newsbeitrag news:vg3zl3rw5xq.fsf@pepper.modeemi.cs.tut.fi... > james <bubba@bud.u> writes: > >> The board is made by Digilent Inc for Xilinx and is sold on Digilent's >> web page also. >> >> The Max part is MaX3232 per the schematic. > > Interestingly, now that I looked, mine actually has an ST3232 :) But > undoubtedly functionality is the same as MAX3232. Not exactly, the original MAX3232 is capable of transferring up to 1Mbaud, the ST3232 400kbaud only. MIKEArticle: 145244
Hello, Few days back, I got a good help from this forum about CPLD programming. I have succeded in making my own design based on a microcontroller to configure a spartan 2 as well as to program XC95108 CPLD. Now I am moving to Spartan 3 and struggling with it. A very good document from Xilinx about Spartan 2 configuration is XAPP188 (Specifically table 7 on page 11) which lists steps to be taken while configuring Spartan 2. I did not find such clear information about Spartan 3. Does anyone know more details about the steps for spartan 3? I have already referred to their Spartan 3 configuration guide UG332 but it is slightly confusing. I also tried the way XC3Sprog is implemented but it did not work. Please let me know if you know anything about it. I can share information about spartan2 and xc95... Thanks and regards, --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145245
M.Randelzhofer <techseller@gmx.de> wrote: (snip) > Not exactly, the original MAX3232 is capable of transferring > up to 1Mbaud, the ST3232 400kbaud only. According to the Maxim data sheet only the MAX3237 can do megabaud, and only when the MBAUD input is active. Otherwise it is 250kbps. The MAX3232 seems to specify the maximum data rate as MIN 120kbps TYP 235kbps, load of 3k ohms, 1000pF, one transmitter switching. -- glenArticle: 145246
I got it. Spartan 3 needs a Jprogram instruction before config_in instruction. Spartan 3 has a 6 bit IR Vs 5 bit IR of Spartan 2. Rest of the things are almost similar or same. Thanks.. >Hello, > >Few days back, I got a good help from this forum about CPLD programming. >I have succeded in making my own design based on a microcontroller to >configure a spartan 2 as well as to program XC95108 CPLD. > >Now I am moving to Spartan 3 and struggling with it. A very good document >from Xilinx about Spartan 2 configuration is XAPP188 (Specifically table 7 >on page 11) which lists steps to be taken while configuring Spartan 2. > >I did not find such clear information about Spartan 3. Does anyone know >more details about the steps for spartan 3? > >I have already referred to their Spartan 3 configuration guide UG332 but it >is slightly confusing. > >I also tried the way XC3Sprog is implemented but it did not work. > >Please let me know if you know anything about it. > >I can share information about spartan2 and xc95... > >Thanks and regards, > >--------------------------------------- >Posted through http://www.FPGARelated.com > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145247
Hi, I had been learning LVDS as a hobby but I'm having a hard time understanding the pinout orders. Right know I would like to know the precise order of the pinouts of an LCD panel (30 pin I-Pex connector) between the panel and the motherboard (Atom z520 Intel US15w chipset). MB and panel pics: http://www.flickr.com/photos/47170574@N08/ How can achieve this?, via software, oscilloscope, voltage measurements?, what are the risks to mess the LCD panel?. I know that for many of you these are dumb questiosn, but is not easy to find info about this topic. Thanks for nay help, Regards George B. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145248
Hi, I need to implement CRC detection in a Spartan3 Xilinx FPGA. My data stream is coming in one byte at a time, but I do have about 8-10 clock cycles between each byte (still tbd!). If I want to save area, is it better to use a CRC that works byte per byte or bit per bit? Also, any idea where I could find code for the standard polynomials? Thanks! Diego --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145249
On Wed, 03 Feb 2010 07:21:13 -0600, dlopez wrote: > Hi, > I need to implement CRC detection in a Spartan3 Xilinx FPGA. My data > stream is coming in one byte at a time, but I do have about 8-10 clock > cycles between each byte (still tbd!). > > If I want to save area, is it better to use a CRC that works byte per > byte or bit per bit? > > Also, any idea where I could find code for the standard polynomials? > > Thanks! > Diego > > --------------------------------------- Posted through > http://www.FPGARelated.com There is a great polynomial generator on the web, http://www.easics.com/webtools/crctool
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