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John_H wrote:
> Ray, your comments are again right on target with my own feelings about bugs
> and support. The webcase submission issue especially hits home. One minor
> difference for me may be that when I find unusual behavior and have it
> isolated to a functional portion of the design, I may check the (externally
> available) knowledge database for any information relating to my problem
> area before spending a few more days to further isolate the cause. I've had
> several instances where the information is in *a* database, just not one I
> can get to.
>
> For ANYONE who is concerned with whether or not to air the dirty laundry of
> their EDA tools and silicon, PLEASE read through Ray's note and understand
> where designers come from. Our company has had TOO many issues with silicon
> (non-FPGA as well) and EDA tools ("you knew about this for how many
> months?") that when we encounter known bugs that are "hidden" from plain
> view, we are LIVID. There is no excuse to withhold information that WILL
> affect designs if there is a way to communicate the issues externally.
>
> In this instance, there is a way.
>
John, I also search the answers database to see if there are any matches
to the problem at hand. More often than not, even when there is
something that is close in there, it is difficult to find, and then
determine whether it matches your problem or not. The answers database
was once a very useful resource, but it has now grown big enough that
you often can't find the magic incantation to pare down the hits to ones
that match your problem.
Austin,
If it is restricted just to the internal database, it is being withheld.
Unless I am experiencing the problem, debugged and isolated the
problem, I don't even know to look for it. In the case of the
synchronous FIFO, there is no excuse to keep that to the internal
database. A simple statement in the user's guide saying that the FIFO16
is an async FIFO and has these particular limitations when used in an
application where both clocks are the same would have been sufficient to
avoid a heck of a lot of troubleshooting time, and would have put the
onus on me the designer. The way it is now, it is hidden until a
designer trips over it in the lab, and by then you've got many hours in
debug, isolation, talking to xilinx to figure out what is going on, and
redesign to work around it. When I found out that Xilinx internally
already knew this was an issue, I was livid.
Article: 92576Dave Roberts wrote: > Dear all, > > I place a timing constraint on a pair of registers (from, to) either side of > some logic. After I run the ISE 6.3 toolchain, I look at the actual delays > for the constraint in Timing Analyzer. > > The constraint seems to have been applied from the source register which I > specified as my destination, to a register or pad elsewhere in the design. > The constraint is applied to logic other than specified. > > Any suggestions? > > Cheers, > > Dave. > > Can you check the PCF to see if the FROM TO still references the correct register pair? RussArticle: 92577
Ray,
I hear you, and understand your concern.
I also have been in the same situation you were in, and had the same
feelings.
I am not asking forgiveness, but asking for some help in how to deal
with these issues.
If they are really rare, and unusual. Perhaps this isn't so rare and
unusual (now). That is why I am placing it here.
If everytime we think we might have a problem, we shared it, there would
be ten times as much stuff. 9/10's or more of it bogus (not really an
issue).
I'll give you my hot button: NBTI was indicated as an issue with DCMs
in V4. The results were based on HTOL testing at accelerated temps, and
voltages.
Every single device that failed after that torture test that was tested
in my FPGA Lab PASSED the spec. Yet, because the production tester can
not test everything at every corner of voltage and temperature (finite
test time), the tester failed these parts.
Yet despite that I was able to prove that there was never a case where
the part actually failed, the tester folks prevailed. Now I understand
that if that is the only way to determine good, or bad, that if they say
it is bad, I am unable to prove it will never go bad, as I can't test as
many devices as they do.
The NBTI keep alive core, documentation, etc. was a huge effort. Lots
of work. Lots of pain. We contacted hundreds of customers. Made
trips, presentations, etc.
Now, in fairness, it might really be an issue. And if it is, we just
made it a non-issue. But, it never failed to meet specifications on the
bench!
So, we did share it, and in my own humble strange mind (toungue firmly
in cheek), I really believe it is a non-problem, never having occurred
anywhere other than a HTOL test after burnin, with one and only one test
method, and passing when tested using bench equipment (like a scope,
freq generator, etc. rather than an automated pattern run once on a "big
iron" tester).
Austin
Ray Andraka wrote:
> John_H wrote:
>
>> Ray, your comments are again right on target with my own feelings
>> about bugs and support. The webcase submission issue especially hits
>> home. One minor difference for me may be that when I find unusual
>> behavior and have it isolated to a functional portion of the design, I
>> may check the (externally available) knowledge database for any
>> information relating to my problem area before spending a few more
>> days to further isolate the cause. I've had several instances where
>> the information is in *a* database, just not one I can get to.
>>
>> For ANYONE who is concerned with whether or not to air the dirty
>> laundry of their EDA tools and silicon, PLEASE read through Ray's note
>> and understand where designers come from. Our company has had TOO
>> many issues with silicon (non-FPGA as well) and EDA tools ("you knew
>> about this for how many months?") that when we encounter known bugs
>> that are "hidden" from plain view, we are LIVID. There is no excuse
>> to withhold information that WILL affect designs if there is a way to
>> communicate the issues externally.
>>
>> In this instance, there is a way.
>
>
>>
> John, I also search the answers database to see if there are any matches
> to the problem at hand. More often than not, even when there is
> something that is close in there, it is difficult to find, and then
> determine whether it matches your problem or not. The answers database
> was once a very useful resource, but it has now grown big enough that
> you often can't find the magic incantation to pare down the hits to ones
> that match your problem.
>
> Austin,
> If it is restricted just to the internal database, it is being withheld.
> Unless I am experiencing the problem, debugged and isolated the
> problem, I don't even know to look for it. In the case of the
> synchronous FIFO, there is no excuse to keep that to the internal
> database. A simple statement in the user's guide saying that the FIFO16
> is an async FIFO and has these particular limitations when used in an
> application where both clocks are the same would have been sufficient to
> avoid a heck of a lot of troubleshooting time, and would have put the
> onus on me the designer. The way it is now, it is hidden until a
> designer trips over it in the lab, and by then you've got many hours in
> debug, isolation, talking to xilinx to figure out what is going on, and
> redesign to work around it. When I found out that Xilinx internally
> already knew this was an issue, I was livid.
Article: 92578Reza - I should have mentioned that Opencores.org has a SPI module. I've never used it, but it may be educational to look at. In terms of books, I've not seen any Verilog books that I thought were worthwhile. I've given up looking. John ProvidenzaArticle: 92579
I asked about the possibility of LUT output glitches, and Peter Alfke replied: > Good question, often asked: > No glitch, and that behavior is guaranteed by the decoding structure. [...] > I have answered this particular question many times over the past 15 > years. Sorry to bring it up for the umpteenth time, then, but thanks for the answer. Should I have been able to figure this out from the data sheet or other documentation? The description of the Function Generator on page 12 of DS099-2 v1.4 (Spartan 3 functional description) didn't make it clear to me that I could count on a LUT being glitchless. Are the FxMUX multiplexers similarly designed for glitchless transitions? (For those that aren't aware of it, some simple 2:1 mux designs are suceptible to glitches when switching between inputs that are the same state. For instance, if you use two AND gates, an inverter, and an OR, you can have a glitch to 0 when switching between two inputs that are 1. If a CMOS mux is implemented with two transmission gates, this shouldn't occur unless output loading affects the output state while both TGs are open.) EricArticle: 92580
I asked about the possibility of glitches on LUT outputs. Peter gave a definitive response, and Symon wrote: > You got a good answer from Peter. However, my smarty pants response is to > never put yourself in a position where you care what the answer is! You'd > never clock a FF from the output of a LUT. Would you? ;-) I fully agree; my designs are fully synchronous. The reason the whole question came up is that a friend is trying to cram old TTL logic designs into an FPGA without redesigning them to be synchronous, so he has latches, S-R flops, and other horrible stuff. I was wondering whether an S-R flop implemented as two cross-coupled gates using a LUT for each gate could even be guaranteed to function correctly; if LUTs can have output glitches they would not. I'm still trying to convince my friend that his approach is likely to cause him much grief. EricArticle: 92581
Eric, Some comments on glitches: Because the LUT is really more than one stage of multiplexing, the last stage has the fastest response, with the least glitching (or none at all, depending on how such mux'ing is actually accomplished, ie pass gate mux, or logic mux). The FMUX is similar, in that the last stage will always result in the least possibility of changes occuring leading to intermediate states. Last stage is a relative term, as last is what you make it by how you use it. If you never change an input on the real last stage, the 'last stage' becomes the previous one with an input that selects. Earlier product families treated all LUT input delays equal, as the routing couldn't really take advantage of using the more detailed information. I believe now in FPGA Editor for V4 you see the different delays on each input. With more advancements in software, one can use the individual delays to advantage and get better performance, and also less glitch power (power aware routing). Getting all the delays to all stages of mux in the LUT from the previous stages of logic is a nightmare only suitable for a computer to crunch on. How valid it will be over all process/voltage/temperature is another practical matter. Claiming "glitch free" for all corners is something I don't feel comfortable with (as I don't control the inputs nor their possible timing), but claiming minimal glitching is OK (or no glitches while transitioning when input delays are fixed and known). Especially when in a synchronous system, the only penalty of glitches is slightly more power as lines get charged/discharged/charged.... Now how much less power, and how much better performance is something that is often claimed (and disputed) so I won't go into that except to say there is some possibility here for improvements. Those that have hand routed designs to squeeze the most performance (or least glitching power loss) seem to feel that this is worth it. Theoretically it also seems to be valid. Austin Eric Smith wrote: > I asked about the possibility of LUT output glitches, and > Peter Alfke replied: > >>Good question, often asked: >>No glitch, and that behavior is guaranteed by the decoding structure. > > [...] > >>I have answered this particular question many times over the past 15 >>years. > > > Sorry to bring it up for the umpteenth time, then, but thanks for the > answer. > > Should I have been able to figure this out from the data sheet or other > documentation? The description of the Function Generator on page 12 > of DS099-2 v1.4 (Spartan 3 functional description) didn't make it clear > to me that I could count on a LUT being glitchless. > > Are the FxMUX multiplexers similarly designed for glitchless transitions? > > (For those that aren't aware of it, some simple 2:1 mux designs are > suceptible to glitches when switching between inputs that are the same > state. For instance, if you use two AND gates, an inverter, and an OR, > you can have a glitch to 0 when switching between two inputs that are 1. > If a CMOS mux is implemented with two transmission gates, this shouldn't > occur unless output loading affects the output state while both TGs are > open.) > > EricArticle: 92582
Your friend's TTL designs must be really old. As early as 1969 (when I was at Fairchild Applications) we touted synchronous design with 4-bit synchronous counter/registers (the 9310 and 9316, copied by T.I. and called the 74160 and 74161) and other register-oriented logic. Enlightened circles frowned upon making latches out of gates, as early as 1968. BTW, you can build a latch out of one single LUT, by feeding its output back to its input. Then you have 3 control inputs, and you can make them be anything you wish, D, S, R, Enable and even clock... Things for a lazy afternoon, not for serious business... Peter AlfkeArticle: 92583
Hi Okashi, I found the tutorial at XESS.COM very useful when I was just starting out. That was a year or so ago and things change. Seems like you are having trouble with pin IO counts, however, so you should go to the Xilinx site and look for there comparative data. Or just ask the group, we'll size it. Brad Smallridge aivision.com "Okashii" <nordicelf@msn.com> wrote in message news:438e3387$1@news.starhub.net.sg... > Hi there, pardon me but I'm a newbie at fpga and stuff. I was using Xilinx > ISE and vhdl to build some components and no matter what the size of > component I keep getting "number of bonded iob" exceeded. Then after some > observation I finally realized that its the size of bits of the ports of > the top level component :P. May I know where I can find layman information > on fpga online that explains what are "slices, slice flip-flops, LUT, IOB" > and all these? > Thanks in advance! >Article: 92584
Austin Lesea wrote: > Ray, > > I hear you, and understand your concern. > > I also have been in the same situation you were in, and had the same > feelings. > Austin, I think you did the right thing with regards to NBTI. Yes, it apparently is a non-issue, but before you knew it was a non-problem you notified the customers and therefore we were aware of it being a potential problem. It is much better, IMHO, to err on the side of caution (ie, a false positive) rather than to under-report a real problem. Yes, I got caught up in the NBTI thing too, and wound up rewriting the Xilinx macro (long story), but in the end we took it out even before Xilinx scaled back the severity because we never saw any evidence that NBTI was affecting the design. My point with the synchronous FIFO application is that that is a real problem that affects real designs unless it is designed around. I'm pretty sure Xilinx understands that it is a problem, yet there is no public pronouncement warning a designer to look out for it. The time is already past for getting that caution added to the user manual. I'd like to be included on any internal email push list for issues regarding the V4, as I'd rather find out about them from Xilinx than have to discover them on my own after the design is done.Article: 92585
I have a large board which asks for three power supplies, +3V, +3.3V and +-5V. First two can be easily satisfied with two HP power supplies (each has its own GND pin also). Regarding +-5V, can I replace with an HP power supply set to 10V, -5V pin connect to HP's ground and +5V to power?Article: 92586
Frank wrote:
>I have a large board which asks for three power supplies, +3V, +3.3V and
>+-5V.
If I read you correctly, that's four supplies: +3V, +3.3V, +5V, and -5V.
>First two can be easily satisfied with two HP power supplies (each has its own
>GND pin also). Regarding +-5V, can I replace with an HP power supply set to
>10V, -5V pin connect to HP's ground and +5V to power?
No. Doing so would provide zero volts to the board's -5V rail and +10V to
its +5 rail.
You need four supplies.
--
========================================================================
Michael Kesti | "And like, one and one don't make
| two, one and one make one."
mrkesti at comcast dot net | - The Who, Bargain
Article: 92587Michael R. Kesti wrote: > Frank wrote: > >> I have a large board which asks for three power supplies, +3V, +3.3V and >> +-5V. > > If I read you correctly, that's four supplies: +3V, +3.3V, +5V, and -5V. > >> First two can be easily satisfied with two HP power supplies (each has its own >> GND pin also). Regarding +-5V, can I replace with an HP power supply set to >> 10V, -5V pin connect to HP's ground and +5V to power? > > No. Doing so would provide zero volts to the board's -5V rail and +10V to > its +5 rail. > > You need four supplies. > will an ATX supply not do? rwArticle: 92588
Ryan Weihl wrote: > Michael R. Kesti wrote: > >> Frank wrote: >> >>> I have a large board which asks for three power supplies, +3V, +3.3V and >>> +-5V. >> >> >> If I read you correctly, that's four supplies: +3V, +3.3V, +5V, and -5V. >> >>> First two can be easily satisfied with two HP power supplies (each >>> has its own >>> GND pin also). Regarding +-5V, can I replace with an HP power supply >>> set to >>> 10V, -5V pin connect to HP's ground and +5V to power? >> >> >> No. Doing so would provide zero volts to the board's -5V rail and >> +10V to >> its +5 rail. >> >> You need four supplies. >> > will an ATX supply not do? > rw Maybe not. Compound switchers need a load on the main supply in order to come up, and the auxiliary supplies aren't always well regulated. Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 92589
Jerry Avins wrote: > Ryan Weihl wrote: > >> Michael R. Kesti wrote: >> >>> Frank wrote: >>> >>>> I have a large board which asks for three power supplies, +3V, >>>> +3.3V and >>>> +-5V. >>> >>> >>> >>> If I read you correctly, that's four supplies: +3V, +3.3V, +5V, and >>> -5V. >>> >>>> First two can be easily satisfied with two HP power supplies (each >>>> has its own >>>> GND pin also). Regarding +-5V, can I replace with an HP power >>>> supply set to >>>> 10V, -5V pin connect to HP's ground and +5V to power? >>> >>> >>> >>> No. Doing so would provide zero volts to the board's -5V rail and >>> +10V to >>> its +5 rail. >>> >>> You need four supplies. >>> >> will an ATX supply not do? >> rw > > > Maybe not. Compound switchers need a load on the main supply in order > to come up, and the auxiliary supplies aren't always well regulated. > > Jerry They also make more noise than a neo-natal nursery. :-) Regards, SteveArticle: 92590
Steve Underwood wrote: > Jerry Avins wrote: > >> Ryan Weihl wrote: >> >>> Michael R. Kesti wrote: >>> >>>> Frank wrote: >>>> >>>>> I have a large board which asks for three power supplies, +3V, >>>>> +3.3V and >>>>> +-5V. >>>> >>>> >>>> >>>> >>>> If I read you correctly, that's four supplies: +3V, +3.3V, +5V, and >>>> -5V. >>>> >>>>> First two can be easily satisfied with two HP power supplies (each >>>>> has its own >>>>> GND pin also). Regarding +-5V, can I replace with an HP power >>>>> supply set to >>>>> 10V, -5V pin connect to HP's ground and +5V to power? >>>> >>>> >>>> >>>> >>>> No. Doing so would provide zero volts to the board's -5V rail and >>>> +10V to >>>> its +5 rail. >>>> >>>> You need four supplies. >>>> >>> will an ATX supply not do? >>> rw >> >> >> >> Maybe not. Compound switchers need a load on the main supply in order >> to come up, and the auxiliary supplies aren't always well regulated. >> >> Jerry > > > They also make more noise than a neo-natal nursery. :-) If he knows what he's doing, ha can load the 10V supply with a beefy op-amp connected as a follower to a divider across the rails and ground its output. If something goes wrong, it can blow the board unless he uses Zener-cum-fuse protection. There are DC-DC power-supply bricks and chips that can probably supply all the -5 needed from a +5 supply. Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 92591
"Jerry Avins" <jya@ieee.org> wrote in message news:gpKdnbflleKAIhLeRVn-vg@rcn.net... > Steve Underwood wrote: > > Jerry Avins wrote: > > > >> Ryan Weihl wrote: > >> > >>> Michael R. Kesti wrote: > >>> > >>>> Frank wrote: > >>>> > >>>>> I have a large board which asks for three power supplies, +3V, > >>>>> +3.3V and > >>>>> +-5V. > >>>> > >>>> > >>>> > >>>> > >>>> If I read you correctly, that's four supplies: +3V, +3.3V, +5V, and > >>>> -5V. > >>>> > >>>>> First two can be easily satisfied with two HP power supplies (each > >>>>> has its own > >>>>> GND pin also). Regarding +-5V, can I replace with an HP power > >>>>> supply set to > >>>>> 10V, -5V pin connect to HP's ground and +5V to power? > >>>> > >>>> > >>>> > >>>> > >>>> No. Doing so would provide zero volts to the board's -5V rail and > >>>> +10V to > >>>> its +5 rail. > >>>> > >>>> You need four supplies. > >>>> > >>> will an ATX supply not do? > >>> rw > >> > >> > >> > >> Maybe not. Compound switchers need a load on the main supply in order > >> to come up, and the auxiliary supplies aren't always well regulated. > >> > >> Jerry > > > > > > They also make more noise than a neo-natal nursery. :-) > > If he knows what he's doing, ha can load the 10V supply with a beefy > op-amp connected as a follower to a divider across the rails and ground > its output. If something goes wrong, it can blow the board unless he > uses Zener-cum-fuse protection. There are DC-DC power-supply bricks and > chips that can probably supply all the -5 needed from a +5 supply. > > Jerry > -- > Engineering is the art of making what you want from things you can get. > ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ I don't know what you people are talking about. Back to my question, how do I make a +-5V?Article: 92592
"Frank" <Francis.invalid@hotmail.com> wrote in message
news:438fa5a4@news.starhub.net.sg...
>I have a large board which asks for three power supplies, +3V, +3.3V and
> +-5V.
> First two can be easily satisfied with two HP power supplies (each has its
> own
> GND pin also). Regarding +-5V, can I replace with an HP power supply set
> to
> 10V, -5V pin connect to HP's ground and +5V to power?
You might with some caveats.
First, the intended +-5v supply needs to be floating with respect to the
other supplies.
Then the 10v voltage difference can be reference wherever you want in theory
and often in practice.
The challenge is: now that you've floated the supply, how will you reference
it to the ground or 0v point on the board?
Think of the +-5v supply as a 10v battery. A battery "floats" with no
problem.
Unless you do more, the result looks like this:
+------------------------------>+5v
|
|
+----+ +--------------->+3.3v
| 10v| +----+
+----+ |3.3v| +----------+3v
| +-+--++----+
| | |3.3v|
| | +-+--+
| | |
| | |
| +-----+---------> 0v: the reference for +3.3v, +3v
|
|
|
+------------------------------>-5v
With the 10v battery floating, there is no reference to the
other batteries. Current flowing through the circuit board will cause
the +/-5v terminals to go almost anywhere relative to 0v. Depending on
what's on the board,
the +5v terminal could end up at -6v and the =5v terminal at -15v (both
relative to 0v of course).
+------+----------------------->+5v
| |
| | +--------------->+3.3v
+----+ | +----+
| 10v| | |3.3v| +----------+3v
+----+ ++-+ +-+--++----+
| |R1| | |3.3v|
| ++-+ | +-+--+
| | | |
| | | |
| +-------+-----+---------> 0v: the reference for +3.3v, +3v
| +--+
| |R1|
| ++-+
| |
+------+----------------------->-5v
A resistor divider with current much higher than the +/-5v
loads and connected to the 0v reference will refer the +/-5v
to the rest of the batteries.
It's not a very elegant or even practical solution but it makes the
point to address your question.
Fred
Article: 92593http://www.jameco.com/wcsstore/Jameco/Products/ProdDS/212311.pdfArticle: 92594
Just to get back to the original question (which was kind of academic): my answer still stands. The muxing inside the LUT is done by pass transistors, and the internal capacitance holds the value during non-overlapped switching. So: no glitches. Austin describes glitching in a more general sense, and then mentions on the delay differences of different LUT address inputs. Good info, but does not contradict my statement. Peter AlfkeArticle: 92595
Hi All, I haven't seen much replies on My Questions ...? are they too foolish or every body is too busy in there works can anybody please tell me or guide me to some sites documents or books on the implementation of Ethernet Multiplexers KedarArticle: 92596
As of PLDA they are shipping __now__ their XpressFX board that has FX60 chip on board! Interesting though that there is no pricing or direct order for the XpressFX board so maybe PLDA is lying and they are not actually able to ship. http://xilant.com/content/view/18/1/ AnttiArticle: 92597
Hi, I got thinking about recursive design of circuits in VHDL I created a recursive circuit and got it to simulate correctly but then had the thought that the RTL is a binary tree of similar interconnect with each leaf being the same. When this gets synthesized and layed out I guess that the regularity is lost unless layed out by hand. If I were to lay this out by hand, are their any existing papers on packing such regular structures into rectangular spaces? Are there any layout and routing tools designed for such tasks? Thanks in advance, Paddy.Article: 92598
Hi. I'm curious about exactly what sort of things are done with FPGAs.
Is the main reason for their use the additional speed over using a
generic processor, due to clock rate and/or parallelism? Is it mainly
to make cheaper low-run products? What sort of things can be done with
them?
As an example, it would be possible to build a digital reverberation
unit using a *REALLY BIG* FIR filter. If the reverb impulse response
lasted for say 15 seconds requiring M samples to be buffered, then
assuming that x[n] is the current sample and that suitable b[0..M]
coefficients can be found, then the reverb could be calculated as:
reverb[n] = SUM {i=0 to M} x[n - (M - i - 1)] * b[i]
This could be done in fixed point arithmetic.
Given that 15 seconds of 44.1khz sound requires 15 * 44100 = 661500
past input samples to be cached along with the 661500 b[] coefficients,
would this be feasible with current FPGAs?
Cheers,
Ross-c
Article: 92599Hello I am trying to reverse engineer the decimation filter core provided by xilinx core-generator. My requirements are 1. Input data rate : 8.8 M Hz 2. Decimation ratio : 2 3. Number of taps : 32 4. input and coefficeints width:16 5. symmetric filter Xilinx core generator uses One multiplier Two Block ram to store coefficient and input data clock frequency required : 70 MHz How does they achieve this I am not able to find out a structure that can expoit both decimation and symmetry of the filter to reduce the multipliers to 1 and clock frequency to 70 MHz. I want to store the coefficient and input data in block ram so that i can save slice usage. Can any one suggest any ideas ? Thanks bijoy
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