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> there's no need to shout. i said in my original post, in another > thread, that i wasn't a viewsim expert. if you want to correct some of > the fine details of my understanding, then i'm grateful for it. > however, it seems to me that the only difference between my scripts > and yours is that you call other scripts from your script. however, > without parameter passing, this is of little use. I also said that you CAN do VHDL modeling with Viewsim. It DOES support parameter passing. > > (shouting loudly) AND THIS HAS NOTHING TO DO WITH SCHEMATIC OR VHDL AS YOUR > > DESIGN ENTRY TOOL which is what this thread is SUPPOSED to be about! > > i said *nothing* in my post about the relative merits of vhdl entry > and schematic entry. in fact, what i actually said was: This was in response to a post by Jonathan Bromley, NOT in response to a post by you! I do not want to convert my schematics to VHDL to simulate them, period. I DO use VHDL models for simulation. They are two different things. I never said VHDL wasn't a great simulation tool, but converting schematics to VHDL FOR simulation, in my opinion, is a bad idea (for many reasons I won't go into here). > > note that i'm not going > > to pontificate about the relative merits of schematics and vhdl - the > > problem here is only in the simulation part of the cycle. there's no > > reason why you can't simulate a schematic-only design in vhdl. > > and philip originally said: > > > This has NOTHING to do with the VHDL vs Schematic debate, > > which is as pointless big endian vs small endian. > > the issue is simulation. you've mis-quoted me, more than once, and > you're going off topic. the web site says nothing about not being able > to *design* virtexes with schematics; philip also specifically states, > or implies, that you can do it. I did not mentioned the web site. I was informed of this in a meeting with Xilinx, and was told (and I quote) 'Virtex will NOT be supported by schematics, ONLY VHDL". Now, I have subsequently been informed that 'some' of the Viewdraw schematic libraries, incompletely, and missing simulation files, ARE in the M1.5 release. I believe I am trying to keep it ON topic, and the topic (which I started, mind you) IS "Xilinx may not support schematics for Virtex". If YOU don't use ViewDraw schematics for Xilinx work, then why are you even involved in this topic? I appreciate that some people want to suggest other methodologies, but it has been clearly stated that some of us WANT schematic entry for Virtex, period, and that IS the topic. You brought in to this that you believed Viewsim was lame, and I responded by saying your impressions of Viewsim were wrong. > > by the way, i don't give a toss about how anybody else simulates their > designs; they can do what they want. i didn't (and dont) belittle > anybody, Let's see, and I quote: "in short, the term 'mickey mouse' was invented specifically for this sort of simulation. again, please correct me if i've misunderstood viewsim" > ...you'll see that i was giving my opinion that you couldn't > do a good job of simulating a large design with viewsim, and that you > could do a much better job with vhdl. this is, in my opinion, > self-evident. And I stated I can do a very good job of simulating a large design with Viewsim, which supports VHDL modeling anyway, so you are arguing a point that you needn't argue. .... > > OK, how else do you do it, if you don't use your eyes to look to see if the > > simulation is working correctly? The Force? > > no. The Language. what do you need your eyes for? I don't understand. How does a language tell you your simulation is what you expected the FIRST time you run it if you don't physically LOOK at the results to SEE if they are what they should be? Please elaborate. AustinArticle: 12526
Andy Peters wrote: > Erik de Castro Lopo wrote in message <3625244A.6D09@see.sig>... > > >VHDL is great for simulation, it works resonsably well for state machines > >(better than schematics) but there are other areas where it fails miserably > >because there is no way for the synthesizer to read the mind of the > designer. > > Constraints help it understand the designers intent. And if the synthesis > tool is smart enough, it is able to see what the timing constraints are and > choose its topology (say, for your counter example) that'll meet that > constraint. i think for a lot of jobs vhdl and their libraries do quite well. and the synthesizers that i have used seem, for the most part, quite happy to grind away on the design, although sometimes they get sick and, well, die. constraints "help" but the tools aren't always smart enough - having looked at the output of synthesizers with my handy schematic generator [which i hope they don't take away] you can see their limitations and they can't win over a good humanoid. they tend to do some quite stupid things at times, don't have all the tricks a good humanoid has, don't always follow good design practices, and sometimes getting it to do what you want it to do is more work than just doing it and the result is harder to read and modify.while i like the power saw, i still keep and use hand saws. same with cae "tools." just my $0.02, rkArticle: 12527
Evan - >bob - i didn't say it wasn't possible. as you say, i'm sure that >people do it all the time. it would be presumptious of me to say that >it can't be done, it shouldn't be done, or that anyone else should do >it in the way that i prefer to do it. what i actually said was: > >> why >> do i think that you *can't* do a good job of simulating a large >> design, such as a virtex, with viewsim, or aldec's look-a-like, and >> why *can* you do a much better job with vhdl? So it's possible, but it can't be done well. This is a distinction without a difference. My question stands. Bob PerlmanArticle: 12528
An Actel SX device can eaisly handle the speed. http://www.actel.com Will Will Torgerson Actel CorporationArticle: 12529
Hi Pacem, I have been using ED4W-HDL for sometime now and found it to be very good. The latest release which they called ED4W-HDL EXPERT, has all the features you have listed plus more. I was sent a PDF manual of the release and I was quite excited to learn about the new features. Some of the features are smart declaration of signal/port/variable/constant, function/procedure/architecture/entity/process/and even label tagging. The feature that I find most useful is the hierarchy browser which is independent of any simulation and simulation tool. At the moment the manual is not on-line and interested parties would have to send a request to sales@silicon-systems.com but in my last correspondence with them, they will put the manual on their website soon. > I am looking for suggest or recommendation for a VHDL editor. Some of the > features that I would like to have are the following: > > > 1) Color coded keywords > > 2) Test bench generation > > 3) Built-in hierarchy browser > > 4) Auto completion by typing only a few characters > > 5) Independent of any Synthesis or Simulation toolArticle: 12530
Hi, All I'm currently involved with the design that implements image signal processing. And there are some pipeline stages to manipulate one-byte RGB pixel values[0-255] by fixed point arithmetics[multiplication and divide]. The fixed point arithmetic should be implemented with minimum hardware resources in order to be implemented in XILINX FPGA xc40000 series. The problem is that I'm very new to this fixed point arithmetics coding and FPGA implementation. Is there any good web/ftp site related to fixed point arithmetics HDL coding, especially Verilog and FPGA insight. Tutorial and examples would be great. Any help would be greatly appreciated. Thanks in advance. Sungchun -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12531
These might help you out: Field-Programmable Gate Arrays : Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems http://www.amazon.com/exec/obidos/ASIN/0471556653/iversonsoftwarecA Digital Design Using Field Programmable Gate Arrays http://www.amazon.com/exec/obidos/ASIN/0133190218/iversonsoftwarecA FPGAs and Programmable LSI: A Designer's Handbook http://www.amazon.com/exec/obidos/ASIN/0750628839/iversonsoftwarecA Programmable Logic Handbook http://www.amazon.com/exec/obidos/ASIN/0070578524/iversonsoftwarecA Good luck! On Tue, 13 Oct 1998 09:40:25 +0200, Arthur Agababyan <arthura@sun52a.desy.de> wrote: >Hello, > >I want to start to design my own digital systems usind FPGA. >So far I have been mostly engaged in software design. So, >which books you could advise me to read. I have no experience >of either PLD or FPGA. I shall be very thankful if you mention >a few good books on digital design too. > >Thank you. Arthur. > >Arthur Agababyan >DESY >Notkestrasse 85 >22607 Hamburg >Germany > >arthura@sun52a.desy.de Kind regards, Jeff Iverson -- The Directory of Computer Consultants & Developers http://www.iversonsoftware.com/service.html 38 Downtown Plaza #3 - Fairmont MN 56031 507-235-9209 - j5rson@iversonsoftware.comArticle: 12532
Has anyone tried to build up a library of boards for the PC which can all fit onto a reconfigurable card. For example you could have just one card in the back of your PC to do graphics acceleration, network access etc *if* you had enough logic on a board to do it and that logic was fast enough. You could then upgrade your hardware when the design improved by downloading (or buying) the new design. Is this just a pipe dream given the current technology, or has no-one got around to it yet, or is this sort of thing starting to take off. -- Dave Braendler Centre for Intelligent Systems Swinburne University dbraendler@swin.edu.auArticle: 12533
Hi all, first, we had a similar problem if we placed some pads in lower level schematics. There is a bug in the M1.4xx version. I got the recommendation from the Xilinx hotline to use the M1.3 software or XACT 6.x. This problem is fixed in M1.5xx. Second, I built also my own VHDL VSPROM model and had to fight against the out of macrocell problem using M1.4xx. I had to disable the feature "Use Advanced Fitting" in the Options->Edit Template->Optimization menu. Best regards, Holger Venus DLR Institute of Space Sensor Technology e-mail: Holger.Venus@dlr.de Andy Peters schrieb: > > > Actually, I had the same problem, but using ABEL. I implemented the VSPROM > design (using a 9536 CPLD and an EPROM rather than one of the serial PROMs > for XC4K configuration) and the P+R tools threw away the pin assignments, > which were in the source code. Haven't tried it with 1.5 to see if it still > works; nor did I go and put the pin assignments in the .UCF. Maybe later > this week, when I have to finish the schematic for the board... > > As an aside, I tried to implement the VSPROM design using VHDL and ran out > of macrocells, and for the life of me, I can't figure out why. > > -andy > > -- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > 520-318-8191 > apeters@noao.eduArticle: 12534
I have a 600 logic cell design with many bound test of counter done in parallel. I use VHDL tools. The design reaches only 30 MHz. How could I optimize the fpga? (I have already tried to use the maximum of Vendor's function for the target). Michel.Article: 12535
test 1 test 2Article: 12536
Peter wrote: > > I have some old appnotes from Thomson-CSF from ~ 15 yrs ago when they > used to make the 9365/9367 CRT controller chip. > > This implemented line drawing with the standard Bresenham algorithm, > and the appnotes contained details of what they called the Horn > algorithm for drawing circles; the alg. actually generated the y > value for incrementing x, for an octant, and then one swapped x/y > values round in the obvious way to draw the complete circle. One could > always tell if some (slow!) graphics system used this algorithm > because circles were drawn starting in 8 places at once. Don't know if it's the same, but I have an appnote for the NS 32CG16 which describes an algorithm attributed to Bresenham for drawing circles - once again, it only does one octant and you get the remaining seven by symmetry. It's amazingly neat! But beware: it's a tangent calculator, really - since one of the coordinates is incremented linearly - you never get to find out the angle (argument) of the point you are currently drawing. I still say that CORDIC is the best way to go for most purposes. Jonathan BromleyArticle: 12537
Erik de Castro Lopo wrote: > There are some things that no synthesizer can do as well as a > clueful designer with schematic entry. I won't dispute that, but I think synthesis can do a much better job than you suggest. < snip sensible examples and comments on cost tradeoffs > > because there is no way for the synthesizer to read > the mind of the designer. I think the good folk at Synplicity would disagree somewhat. They claim that Synplify infers behaviour from RTL code so that the tool can then instantiate whatever macro is needed to get the desired effect. So your example about a 32-bit counter with the carry propagation split into four pipelined chunks should be reasonable for the tool to infer. By and large I have found Synplify to be amazingly good at inferring sensible designs from obscure RTL. Other tools are just as good, I am sure, but I just happen to know Synplify fairly well. Jonathan BromleyArticle: 12538
> We are developing a high bandwidth switch architecture and we need to >test each switch interface at maximum speed of 100MB/s, which with an >8-bit interface requires a clock of 100MHz. Is there any FPGA out >there that would be able to sustain pumping data at this rate? I >thought of using a slower clock and a 32-bit interface from the FPGA >and then probably use a CPLD to multiplex the data to the switch 8-bit >interface. But there are problems associated with this. Any >suggestions? > In a Xilinx 4010XL-2, we built a 106.25MHz 8B/10B encoder/decoder which has a 2x10bit interface with an external component running at 106.25MHz. With carefull pipelined design and proper timing constraints, this design even autoroutes without placement. And if this is not enough there are the brand new XLA devices, starting at 0.9 speed grades. Regards, BrunoArticle: 12539
Hi all, I am trying to configure a Xilinx XC4000XL part through boundary scan using the JTAG programmer. I was wondering if anyone has been able to do this succesfully. I never see the "DONE" signal going high. I would really appreciate it if someone could give me some guidelines. Sucharita Hardware Engineer, Atto Technology -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 12540
We succeed to program Xilinx CPLD 's using JTAG port only after we disconnect the clock (50MHz) which was connected to one of the pins.This is also written in one of the documents as an advice.May be you have the same problem.Article: 12541
And if you wanted it to be one card, enough connector space... David Braendler <dbraendler@swin.edu.au> wrote in article <3625903E.E81DE33B@swin.edu.au>... > > > Has anyone tried to build up a library of boards for the PC which can > all fit onto a reconfigurable card. For example you could have just one > card in the back of your PC to do graphics acceleration, network access > etc *if* you had enough logic on a board to do it and that logic was > fast enough. You could then upgrade your hardware when the design > improved by downloading (or buying) the new design. > > Is this just a pipe dream given the current technology, or has no-one > got around to it yet, or is this sort of thing starting to take off. > > -- > > Dave Braendler > Centre for Intelligent Systems > Swinburne University > dbraendler@swin.edu.au > > >Article: 12542
This is a multi-part message in MIME format.
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I tried to post this a while ago, my newserver
wouldn't let me, second try:
Here's a post from 07 Jul 1997 by Marc 'Nepomuk'
Heuler(marc@aargh.mayn.de):
While digging the books, one could find
sin(A+B) = sin(A) * cos(B) + cos(A) * sin(B)
cos(A+B) = cos(A) * cos(B) - sin(A) * sin(B)
So if you can tolerate 4 MULs and 2 ADDs per iteration,
you can hardcode sin(B) and cos(B) for the desired
frequency, and start off at sin(A)=0 and sin(B)=1.
Each iteration of the formula (4xMUL 2xADD) gives the next
sin/cos pair for your frequency.
They run indefinitely.
There's another technique, a sinusodial oscillator,
which requires only one multiplication and
an ADD per iteration.
Init: y(-1)= 0
y(-2)= -A * sin W
with A= Amplitude of Sinus
W= 2*pi* Frequency / Samplerate
Each sinus output is calculated as y(n) = 2* cos W * y(n-1) - y(n-2)
I have not made a detailed comparison yet, but from first tests it seems
that the first method is more exact, when using 16 bit fixed point
arithmetic.
End of Marc's post.
The second technique can be quite compact _if_ cosW is a 'nice'
number, i.e. the multiplication can be done in one or two adds, but
this requires that F/S = (2^k)/pi, not necessarilly convenient
frequencies.
As several posted, CORDIC is good too, check
Ray Andraka's site to start: http://users.ids.net/~randraka
For smaller sample rates, the ROM is really not a bad approach.
Yves Vandervennet wrote:
> Hi everybody,
>
> does anybody know how to digitally realize a sine generator
> other than sampling a sine period and storing it in a ROM ?
> We have to integrate it in an FPGA. If anybody knows book references
> on this subject, we would be happy for a very long time.
>
> See you soon on the Web,
>
> Yves.
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Article: 12543I was introduced to a small startup called Prototype Solutions. These people had a prototyping system they offered. They also introduced the concept of library cards. Their system was pretty expensive (around 40K) but the concept looked pretty neat. Here is one of their emails: donb@protosol.com In article <3625903E.E81DE33B@swin.edu.au>, David Braendler <dbraendler@swin.edu.au> wrote: > > >Has anyone tried to build up a library of boards for the PC which can >all fit onto a reconfigurable card. For example you could have just one >card in the back of your PC to do graphics acceleration, network access >etc *if* you had enough logic on a board to do it and that logic was >fast enough. You could then upgrade your hardware when the design >improved by downloading (or buying) the new design. > >Is this just a pipe dream given the current technology, or has no-one >got around to it yet, or is this sort of thing starting to take off. > >-- > >Dave Braendler >Centre for Intelligent Systems >Swinburne University >dbraendler@swin.edu.au > >Article: 12544
I have designed a PCI board like this at work. It very useful but as things get faster and faster custom solutions are usually the way to go. ASICs still have the upper hand for graphics and sound processing. For fairly low tech. apps Programmable hardware is definitely a viable solution. The problem is that if the quantities are large then ASIC is difintely worth it as FPGAs (especially large densities) are quite expensive. When prices come down on the FPGA front (>1M gates) this is definitely one of my "want's". Again this may be, as you say, a pipedream as the ASIC densities will go up as well. ------------------ Gareth Baron David Braendler wrote in message <3625903E.E81DE33B@swin.edu.au>... > > >Has anyone tried to build up a library of boards for the PC which can >all fit onto a reconfigurable card. For example you could have just one >card in the back of your PC to do graphics acceleration, network access >etc *if* you had enough logic on a board to do it and that logic was >fast enough. You could then upgrade your hardware when the design >improved by downloading (or buying) the new design. > >Is this just a pipe dream given the current technology, or has no-one >got around to it yet, or is this sort of thing starting to take off. > >-- > >Dave Braendler >Centre for Intelligent Systems >Swinburne University >dbraendler@swin.edu.au > >Article: 12545
Holger Venus wrote in message <362597AD.D025BEF1@dlr.de>... >Hi all, > >first, we had a similar problem if we placed some pads in lower level >schematics. >There is a bug in the M1.4xx version. I got the recommendation from the >Xilinx hotline to use the M1.3 software or XACT 6.x. This problem >is fixed in M1.5xx. OK, will try that. >Second, I built also my own VHDL VSPROM model and had to fight against >the out of macrocell problem using M1.4xx. I had to disable the feature >"Use Advanced Fitting" in the Options->Edit Template->Optimization menu. I'll try that too! Sounds like 1.4 was, uh, buggy... -- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 520-318-8191 apeters@noao.eduArticle: 12546
Many thanks to all who responded. For my application, a fast carry binary counter followed by a registered xor array to convert binary to gray code will work beautifully. I didn't realize the conversion from binary to gray code was so simple: q0(gray) = q0(bin) XOR q1(bin) q1(gray) = q1(bin) XOR q2(bin) q2(gray) = q2(bin) XOR q3(bin) . . . qn-1(gray) = qn-1(bin) XOR qn(bin) qn(gray) = qn(bin) Next question: Is there a similar relationship to convery the gray code back to binary? Dan Kuechle <dan_kuechle@i-tech.com> wrote in article <01bdf6cf$53cc4100$1f38d926@dank.i-tech.com>... > Anybody know if its possible to do a gray code counter in a Xilinx 4000xl > fpga using the fast carry? > > I would like a 100mhz, 24 bit free running counter, but might be able to > live with 50mhz. > Maybe at 50mhz I wouldn't need fast carry??? > > > Thanks > Dan >Article: 12547
>Next question: >Is there a similar relationship to convery the gray code back to >binary? Yes, there is. All right, I'm being a smart aleck. I'll post the algorithm tomorrow unless someone beats me to it. - Regards.Article: 12548
Andy Peters wrote: > milostnik@my-dejanews.com wrote in message > <702h0n$db2$1@nnrp1.dejanews.com>... > > >This has always been the dark side of schematics. Using HDL has his > >cavetas too. What if the design has used librareis that your tool > >doesnt have? Portability is gone too. > > If you have a good synthesizer, you shouldn't have to instantiate > vendor/device specific components in your HDL code. Admittedly, there are > things that you'd have to instantiate as black-boxes (Xilinx RAMs come to > mind), but that's not the HDL's fault, is it? In the case of RAM (Only RAM not special functions like OSC4 ) I would say that really the blame should not fall on Xilinx or the HDL language it's self rather it should fall on the synthesis tool makers. Exemplar has proved it is possible to infer CLB RAM, and why should it not be? RAM is a Read/Write array with some control logic to make sure that the reads and writes happen at the right time. To code up such an array in HDLs is totally possible with out violating a single rule of the language it's self. So all that has to happen it that the synthesis engine be smart enough to see one of these read/write arrays and say "Ahh Ha that is RAM!!" and make it so. This is not X's problem or the problem of the HDL. My 2 cents Have FUN!! Nick I am sure that anybody who actually writes syth tools will say "You make it sound so easy, why don't you do it?". Obviously there is something that is hard about the infering of RAM or it would be fully availible now. It sure does seem easy on the first glance, so synth tool writers what is the problem? > > > -a > -- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > 520-318-8191 > apeters@noao.eduArticle: 12549
Austin Franklin wrote: > Try doing a functional simulation....I believe the underlying simulation > libraries are not there.... >>I believe that is because the Virtex timing files were not in place when they shipped F1.5 however, the timing models are coming. Have FUN!! Nick > > > And, yes, I was referring to Viewlogic support mostly anyway... > > Austin > > Nick Hartl <"nhartl[no_spam]"@earthlink.net> wrote in article > <361F9457.4093397C@earthlink.net>... > > Well now I do see Virtex library symbols in the Foundation Schematic > Editor and > > have placed a Virtex chip using Foundation schematics only (No HDL). So > where > > is this no schematic support? > > > > I did here that at this time there is some question if ViewLogic will > support > > Virtex in schematics. I am not sure if this is a decision made by Veiw > or by > > Xilinx. > > > > Have FUN!!! > > Nick > > > > > It appears that Xilinx may not be supporting Viewlogic Viewdraw > schematic > > > entry for Virtex (or any other schematic entry tool for that matter). > > > SOMEhow, SOMEone, interviewed SOME people, and these people were > apparently > > > taken by the Xilinx decision making tree as the 'golden' cross section > of > > > 'important' users. These SOME people said they did not want > schematics, > > > that HDLs would do fine. > > > > > > Now, nothing against HDLs, as I do use them, and they are fine...BUT > there > > > are some things just done better in schematics. Let's not get into > that > > > subject, as we all have bantered this issue of schematics v HDLs about, > but > > > for Xilinx to dictate what my design methodology is to be is not OK. > > > Personally, I think this, what I would call, a quite 'uneducated' > decision, > > > is a very bad decision.... > > > > > > ANYone else know ANYthing more about this? > > > > > > Austin Franklin > > > darkroom@ix.netcom.com > > > > > > > >
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