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John Larkin wrote: > On Sun, 26 Nov 2006 22:12:16 GMT, "Homer J Simpson" > <nobody@nowhere.com> wrote: > > > > >"John Fields" <jfields@austininstruments.com> wrote in message > >news:qiujm21qpbvceoc58lf9epg4hhf8rt4jjg@4ax.com... > > > >>>> Kind of like > >>>> a "Will and Grace" arrangement, get it? > >>> > >>>No. Never watched it. I've heard a lot of gays do. > > > >> Then you'd probably enjoy it. > > > >Why don't you tell us all about it from the gay perspective which you know > >so well? I'll stick to my preference for shows for heterosexuals. > > > > > > Gosh, don't you guys ever get bored with this ritual cycle of juvenile > insults? > > And what's with the homosexual obsession? > > John [Can't post the a.b.s.e. from google which is what I am limited to until tomorrow night] I get tired of the insult <-> insult phase of threads (usually found in any thread exceeding 40 posts, so this one started early) but I am reminded of Godwin's law ;) These folk are armed with keyboards and a news account; do not attempt to approach them; call the authorities and stay well clear ;) Cheers PeteSArticle: 112626
Jim Thompson wrote: > On 25 Nov 2006 15:05:26 -0800, "PeteS" <PeterSmith1954@googlemail.com> > wrote: > > >Jim Thompson wrote: > > > [snip] > >> > >> You have it wrong, it's... > >> > >> Those that can, do. > >> > >> Those that can't, flip burgers. > >> > >> Those that can't flip burgers, work check-out at Fry's Electronics. > >> > >> Those that can't work check-out at Fry's Electronics, teach. > >> > >> Those that can't teach, become managers. > >> > >> Those that can't manage, they hang out on S.E.D hiding behind some > >> hideous nom de plume. > >> > >> ...Jim Thompson > > > >Amusing > > > >I was actually being serious for a moment. Teachers (as opposed to > >lecturers) must have a fire inside if they are actually _teachers_. The > >best teachers _are_designers, for that reason. I was not always the > >most popular, but I was always the most respected. > > > >I happen to respect your abilities (not that I always say so) because I > >know what design takes; indeed I am a designer, of boards not chips. Do > >you know what it takes to _really_ teach? (that's not a rhetorical > >question). > > > >Cheers > > > >PeteS > > I taught at a school for technicians from around 1964 until 1974. > > And I've given numerous lectures and seminars (I wrote AND taught all > the ICE analog stuff years ago). > > I even substituted for Barry Gilbert, when he took ill in 1986 (?, > yep, checked my old passport)), teaching a week-long seminar at the > Royal Melbourne Institute of Technology, teaching bipolar chip design > alongside Willy Sansen, who taught the CMOS stuff. > > I offered to teach for free at Scottsdale Community College, but was > turned down... no "teacher's certificate" :-( > > And I agree with you, teachers have the "fire". I am where I am now > because of teachers with "fire"... I particularly still fondly > remember Evelyn Truchovesky, my 8th grade Algebra teacher ;-) > > ...Jim Thompson > -- > | James E.Thompson, P.E. | mens | > | Analog Innovations, Inc. | et | > | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | > | Phoenix, Arizona Voice:(480)460-2350 | | > | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | > | http://www.analog-innovations.com | 1962 | > > I love to cook with wine. Sometimes I even put it in the food. I have taught technicians (two year programs and 9 month programs - no, not that sort of 9 month program) professionally, and the reason they were successful (at least in part) was because I had (still have) a fire inside, or so I like to think. My point about teaching in general is we are (whether we want to or not) teaching whoever works for us ;) Let's make sure it's a good education :) Cheers PeteSArticle: 112627
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:tp4km2hko06v6g187t6rlvt5sruvrsn091@4ax.com... >>Why don't you tell us all about it from the gay perspective which you know >>so well? I'll stick to my preference for shows for heterosexuals. > Gosh, don't you guys ever get bored with this ritual cycle of juvenile > insults? > > And what's with the homosexual obsession? Didn't you start it? You two seem to have some sort of gay obsession.Article: 112628
On 26 Nov 2006 16:14:31 -0800, "PeteS" <PeterSmith1954@googlemail.com>
wrote:
>Jim Thompson wrote:
>
[snip]
>>
>> And I agree with you, teachers have the "fire". I am where I am now
>> because of teachers with "fire"... I particularly still fondly
>> remember Evelyn Truchovesky, my 8th grade Algebra teacher ;-)
>>
>> ...Jim Thompson
[snip SIG for non-compliant news client :-]
>
>I have taught technicians (two year programs and 9 month programs - no,
>not that sort of 9 month program) professionally, and the reason they
>were successful (at least in part) was because I had (still have) a
>fire inside, or so I like to think.
>
>My point about teaching in general is we are (whether we want to or
>not) teaching whoever works for us ;)
>
>Let's make sure it's a good education :)
>
>Cheers
>
>PeteS
There can be a side benefit... I hired my best technician-class
student. He ended up working for me for 30 years, changing employers
every time I did, worked for Widlar for a few months in 1968 when I
moved from Cupertino back to Phoenix... best technician I've ever
seen, plus he acted as my secretary, cleaning up all my hand-scrawled
drawings, and I still have them to this day ;-)
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Article: 112629On Mon, 27 Nov 2006 00:15:36 GMT, "Homer J Simpson" <nobody@nowhere.com> wrote: > >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:tp4km2hko06v6g187t6rlvt5sruvrsn091@4ax.com... > >>>Why don't you tell us all about it from the gay perspective which you know >>>so well? I'll stick to my preference for shows for heterosexuals. > >> Gosh, don't you guys ever get bored with this ritual cycle of juvenile >> insults? >> >> And what's with the homosexual obsession? > >Didn't you start it? You two seem to have some sort of gay obsession. > > Well, I started this thread, if that's what you mean, but it wasn't about any kind of sex. And who is "you two"? JohnArticle: 112630
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:n4ekm218lkea0s3m8bghc98t84b7mbq8h4@4ax.com... > Well, I started this thread, if that's what you mean, but it wasn't > about any kind of sex. And who is "you two"? You and Fields.Article: 112631
I am using altera quartus s/w.i want to constraint 12 similar timing paths to have same timing in post fitting.How to do that in quartus s/w.I am in great needful for that kumarArticle: 112632
On Mon, 27 Nov 2006 01:29:29 GMT, "Homer J Simpson" <nobody@nowhere.com> wrote: > >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:n4ekm218lkea0s3m8bghc98t84b7mbq8h4@4ax.com... > >> Well, I started this thread, if that's what you mean, but it wasn't >> about any kind of sex. And who is "you two"? > >You and Fields. > > Please check the posts. You are clearly confused. JohnArticle: 112633
Hi all, Thanks a lot for all the comments! I always think is there any methodology to find the first meanful "xxxx". And I conclude the methods recommended in previous posts. Please add the list if I miss the idea you write or you think there are some methods else, thanks! By tool feature: I don't know the feature. Or by language feature: [1] default: signal = 8b'x; (maybe adopted by most people) [2] default: $display Error; (Alex) [2] default: set a debug register; (Alex) [4] elsex: do something; (Sharp) Best regards, Davy sharp@cadence.com wrote: > Petter Gustad wrote: > > > > I wish simulators could have a switch or similar to make sure that if > > you had something like: > ... > > would case ALL assigned vars in BOTH if branches to become x. Same > > thing for the ? operator. > > The ?: operator does that already. In fact, it is significantly > smarter than that. If the condition is x, it only produces an x at the > outputs for bits that don't match between the two selected values. > That keeps the result from being overly pessimistic. > > This cannot be generalized to if-statements, because you can do > arbitrarily complex things in an if-statement, not just assign to > variables. How do you maybe-display something? How do you maybe-call > a task? How do you maybe-disable a block? How do you maybe-execute > more nested conditionals that would only assign to some variables but > not others? If you assume the worst, the result could be far too > pessimistic. > > It could be so pessimistic that you cannot make any progress in > simulation. If an outer condition is X, but a nested condition is > false, you would be Xing out a variable that could not actually have > been assigned. Or the design might only assign to some bits of a vector > or array, but you end up Xing out the whole thing because it was > potentially assigned. It might be impossible to simulate your design > being initialized. You could waste a lot of time tracking down > problems that turned out not to be real problems on closer examination, > eventually giving up and turning off this special switch. > > The over-optimism of Verilog if-statements with X conditions is a > problem in the language, but I don't think that this frequently heard > suggestion would provide a viable solution. > > Another possible approach would be to add an optional elsex to the > if-statement syntax, to allow the user to specify the behavior to take > on an X (similar to using a default in a case). Then the user could > use their better understanding of the situation to decide what to do, > and avoid over-pessimism.. The problem with this is that it is not > automatic. The user has to remember to do it for each if-statement, > and correctly figure out what result they want. > > Note that switching if-statements containing assignments into > assignment statements containing ?: where possible would give better > results, but at the cost of making the code harder to read. > > I have yet to hear a good solution to this if-statement problem, which > is probably why it works the way it does, even though it is flawed.Article: 112634
John Larkin wrote: > On Mon, 27 Nov 2006 00:15:36 GMT, "Homer J Simpson" > <nobody@nowhere.com> wrote: > > > > >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message > >news:tp4km2hko06v6g187t6rlvt5sruvrsn091@4ax.com... > > > >>>Why don't you tell us all about it from the gay perspective which you know > >>>so well? I'll stick to my preference for shows for heterosexuals. > > > >> Gosh, don't you guys ever get bored with this ritual cycle of juvenile > >> insults? > >> > >> And what's with the homosexual obsession? > > > >Didn't you start it? You two seem to have some sort of gay obsession. > > > > > > Well, I started this thread, if that's what you mean, but it wasn't > about any kind of sex. And who is "you two"? Maybe he is referring to the mouse you keep in your pocket? BTW, the people who are only reading this in alt.binaries.schematics.electronic have to miss all my wit. Google won't let me post there.. :^(Article: 112635
Jim Thompson wrote: > ...Jim Thompson > -- > | James E.Thompson, P.E. | mens | > | Analog Innovations, Inc. | et | > | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | > | Phoenix, Arizona Voice:(480)460-2350 | | > | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | > | http://www.analog-innovations.com | 1962 | You seem to have some analog credentials. Maybe you could divert some of this thread to answer a question about switched cap voltage converters. Where I am currently working we need to convert a wide battery voltage range to typical circuit voltages, such as 5, 3.3, etc. volts. The battery voltage varies from 7 to 17 typically. We can used inductive switchers for this, but it is in a radio and we prefer not to use these. They are also not so efficient when running at low currents, at least the ones we can buy as chips. By low I mean <100 mA. Remembering a chip I had almost used once, it had occured to me that a switched cap regulator could efficiently convert in a variety of exact ratios down to a voltage just above the required output and an LDO could properly regulate to the final voltage for an overall efficiency that could be a lot better than an inductive switcher. I outlined some of the capacitor and switch topology to get the various ratios and determined the input voltage ranges and calculated efficiencies. It looked pretty good on paper. But then I tried to consider the power required to drive the various FETs to make the circuit operate and it looked like it would require a lot of current to drive the gates. Am I right in thinking that this is where the circuit looses efficiency? I did my calcs based on the capacitance of the gate. This seemed to be roughly constant over a lot of parts I looked at that could handle 100 ma to 1000 ma. Could this be dealt with better in an ASIC with on chip FETs? The chip I had seen that did this was a part from TI that only worked with input voltages up to 5.5 or so. I have not found anything that works with the higher voltages we need. Any ideas?Article: 112636
Hi How to make the FPGA to download the file from QPROM when ever the FPGA is ON Thanks and Regards BODDU LokeshArticle: 112637
Kumar,
It will help if you give more details. Are these I/O paths (Tsu or
Tco)?, or core paths? Same clock? or Different clock?
Basically, you first need to figure out what type of constraint (Tsu,
Tco, Max Delay) you can use. Once you have that, you can either use
wildcards to group all sources and all destinations, or you can use
assignment groups (also known as timing groups) to group names you
cannot group with simple wildcards (see "Using Assignment Groups" in
http://www.altera.com/literature/hb/qts/qts_qii52001.pdf).
A few examples:
* Assuming ina, inb and inc driving rega, regb and regc:
set_instance_assignment -from in* -to reg* -name TSU_REQUIREMENT
5ns
* Assuming rega, regb, and regc driving outa, outb, and outc:
set_instance_assignment -from reg* -to out* -name TCO_REQUIREMENT
5ns
* Assuming rega[3..0] to regb[3..0]
set_instance_assignment -from rega* -to regb* -name MAX_DELAY 5ns
(note that you can also use SETUP_RELATIONSHIP instead of
MAX_DELAY. See online help for difference)
Hope this helps.
- David Karchmer
Altera
On Nov 26, 5:37 pm, "ram" <vsrpku...@rediffmail.com> wrote:
> I am using altera quartus s/w.i want to constraint 12 similar timing
> paths to have same timing in post fitting.How to do that in quartus
> s/w.I am in great needful for that
> kumar
Article: 112638I have 12 paths starting from a clock and some combinational logic including delay chain .These logic goes to output port of FPGA.My board engineer did mistake by connecting them some output to pins of VREF(high capacitive pins).The entire performance was in trouble.I cant change the board also now.I want to contraint from clock to output pin of FPGA so that i can get desired performance kumar dkarchmer@gmail.com wrote: > Kumar, > > It will help if you give more details. Are these I/O paths (Tsu or > Tco)?, or core paths? Same clock? or Different clock? > Basically, you first need to figure out what type of constraint (Tsu, > Tco, Max Delay) you can use. Once you have that, you can either use > wildcards to group all sources and all destinations, or you can use > assignment groups (also known as timing groups) to group names you > cannot group with simple wildcards (see "Using Assignment Groups" in > http://www.altera.com/literature/hb/qts/qts_qii52001.pdf). > > A few examples: > > * Assuming ina, inb and inc driving rega, regb and regc: > set_instance_assignment -from in* -to reg* -name TSU_REQUIREMENT > 5ns > > * Assuming rega, regb, and regc driving outa, outb, and outc: > set_instance_assignment -from reg* -to out* -name TCO_REQUIREMENT > 5ns > > * Assuming rega[3..0] to regb[3..0] > set_instance_assignment -from rega* -to regb* -name MAX_DELAY 5ns > (note that you can also use SETUP_RELATIONSHIP instead of > MAX_DELAY. See online help for difference) > > Hope this helps. > > - David Karchmer > Altera > > On Nov 26, 5:37 pm, "ram" <vsrpku...@rediffmail.com> wrote: > > I am using altera quartus s/w.i want to constraint 12 similar timing > > paths to have same timing in post fitting.How to do that in quartus > > s/w.I am in great needful for that > > kumarArticle: 112639
I have 12 paths starting from a clock and some combinational logic including delay chain .These logic goes to output port of FPGA.My board engineer did mistake by connecting them some output to pins of VREF(high capacitive pins).The entire performance was in trouble.I cant change the board also now.I want to contraint from clock to output pin of FPGA so that i can get desired performance kumar dkarchmer@gmail.com wrote: > Kumar, > > It will help if you give more details. Are these I/O paths (Tsu or > Tco)?, or core paths? Same clock? or Different clock? > Basically, you first need to figure out what type of constraint (Tsu, > Tco, Max Delay) you can use. Once you have that, you can either use > wildcards to group all sources and all destinations, or you can use > assignment groups (also known as timing groups) to group names you > cannot group with simple wildcards (see "Using Assignment Groups" in > http://www.altera.com/literature/hb/qts/qts_qii52001.pdf). > > A few examples: > > * Assuming ina, inb and inc driving rega, regb and regc: > set_instance_assignment -from in* -to reg* -name TSU_REQUIREMENT > 5ns > > * Assuming rega, regb, and regc driving outa, outb, and outc: > set_instance_assignment -from reg* -to out* -name TCO_REQUIREMENT > 5ns > > * Assuming rega[3..0] to regb[3..0] > set_instance_assignment -from rega* -to regb* -name MAX_DELAY 5ns > (note that you can also use SETUP_RELATIONSHIP instead of > MAX_DELAY. See online help for difference) > > Hope this helps. > > - David Karchmer > Altera > > On Nov 26, 5:37 pm, "ram" <vsrpku...@rediffmail.com> wrote: > > I am using altera quartus s/w.i want to constraint 12 similar timing > > paths to have same timing in post fitting.How to do that in quartus > > s/w.I am in great needful for that > > kumarArticle: 112640
PeteS wrote: > > [Can't post the a.b.s.e. from google which is what I am limited to > until tomorrow night] > > I get tired of the insult <-> insult phase of threads (usually found in > any thread exceeding 40 posts, so this one started early) but I am > reminded of Godwin's law ;) > > These folk are armed with keyboards and a news account; do not attempt > to approach them; call the authorities and stay well clear ;) Just kill file any cartoon character you see posting on a newsgroup. -- Service to my country? Been there, Done that, and I've got my DD214 to prove it. Member of DAV #85. Michael A. Terrell Central FloridaArticle: 112641
On 26 Nov 2006 19:12:31 -0800, "rickman" <gnuarm@gmail.com> wrote: >John Larkin wrote: >> On Mon, 27 Nov 2006 00:15:36 GMT, "Homer J Simpson" >> <nobody@nowhere.com> wrote: >> >> > >> >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >> >news:tp4km2hko06v6g187t6rlvt5sruvrsn091@4ax.com... >> > >> >>>Why don't you tell us all about it from the gay perspective which you know >> >>>so well? I'll stick to my preference for shows for heterosexuals. >> > >> >> Gosh, don't you guys ever get bored with this ritual cycle of juvenile >> >> insults? >> >> >> >> And what's with the homosexual obsession? >> > >> >Didn't you start it? You two seem to have some sort of gay obsession. >> > >> > >> >> Well, I started this thread, if that's what you mean, but it wasn't >> about any kind of sex. And who is "you two"? > >Maybe he is referring to the mouse you keep in your pocket? These sweats don't have pockets, and anyhow I'm surrounded by cats. And why would I keep a USB Logitech in my pocket? > >BTW, the people who are only reading this in >alt.binaries.schematics.electronic have to miss all my wit. Google >won't let me post there.. :^( Ah, wit. Thanks for pointing it out to us. JohnArticle: 112642
PeteS wrote: > On the S3, at least, VccAux powers the JTAG chain, part of the init > setup and the DCMs. I don't believe it powers anything else. It usually supplies input and output buffers for LVDS as well (at least it does in Virtex2 Pro and Virtex 4), even if the bank those IOs are in is supplied with i.e. 3.3V. cu, Sean -- The FROM:-address in this posting is valid until the end of the month only, after that every e-mail sent to this address will bounce. If you want to contact me after that, try figuring out what the next valid address will be...Article: 112643
How to know the values of (Tsu,Tco, Max Delay) in a design.I am using LVTTL I/O standard kumar ram wrote: > I have 12 paths starting from a clock and some combinational logic > including delay chain .These logic goes to output port of FPGA.My board > engineer did mistake by connecting them some output to pins of > VREF(high capacitive pins).The entire performance was in trouble.I cant > change the board also now.I want to contraint from clock to output pin > of FPGA so that i can get desired performance > kumar > > > > > dkarchmer@gmail.com wrote: > > Kumar, > > > > It will help if you give more details. Are these I/O paths (Tsu or > > Tco)?, or core paths? Same clock? or Different clock? > > Basically, you first need to figure out what type of constraint (Tsu, > > Tco, Max Delay) you can use. Once you have that, you can either use > > wildcards to group all sources and all destinations, or you can use > > assignment groups (also known as timing groups) to group names you > > cannot group with simple wildcards (see "Using Assignment Groups" in > > http://www.altera.com/literature/hb/qts/qts_qii52001.pdf). > > > > A few examples: > > > > * Assuming ina, inb and inc driving rega, regb and regc: > > set_instance_assignment -from in* -to reg* -name TSU_REQUIREMENT > > 5ns > > > > * Assuming rega, regb, and regc driving outa, outb, and outc: > > set_instance_assignment -from reg* -to out* -name TCO_REQUIREMENT > > 5ns > > > > * Assuming rega[3..0] to regb[3..0] > > set_instance_assignment -from rega* -to regb* -name MAX_DELAY 5ns > > (note that you can also use SETUP_RELATIONSHIP instead of > > MAX_DELAY. See online help for difference) > > > > Hope this helps. > > > > - David Karchmer > > Altera > > > > On Nov 26, 5:37 pm, "ram" <vsrpku...@rediffmail.com> wrote: > > > I am using altera quartus s/w.i want to constraint 12 similar timing > > > paths to have same timing in post fitting.How to do that in quartus > > > s/w.I am in great needful for that > > > kumarArticle: 112644
i need vhdl source code for I2C Controller urgently...plz help me regarding this..MY email ID is meetpavankumar@gmail.comArticle: 112645
hi, i found that Julien Lochen is having I2C Controller implementation using vhdl.Plz send me the src code(& test benches if u have) of this. i need urgently..My email id is meetpavankumar@gmail.comArticle: 112646
Al wrote: > An errata corrige to my previous post: > > Al wrote: > >> Anyway, based on the datasheet, it looks like that temperature >> derating factor, with 2.5V for VCCA (as it is in our case), will be >> 0.74 at -40 °C and 0.97 at +85 °C (our temperature range), that's why >> I estimated a min-max difference of 20%. >> If all these calculations are wrong (as they can be)then we will see a >> problem! :-) >> > The datasheet reports derating for Junction Temperature, which is > strictly related to the power and is not ambient temperature at all. I > will estimate power consumption from the external current absorption on > my board, which has much more than a simple fpga! > The thermochamber will give much more answers! Depending on what exactly you are using this for, you could also look at 'margining' it - generate a tapped delay, and use a faster tap for your delay, and check the longer one was still (just) OK, which means the faster one was OK with margin. Or, even build a calibrate phase into the tap selection. On the 'going faster' sense, the FPGAs tend to self-compensate : A fast process device will give, and tolerate, faster delays, and a hot device will give, and need, longer delays. Generally the big problems come when the delays run into the next clock edge :) -jgArticle: 112647
"Andrew Holme" <andrew@nospam.com> schrieb im Newsbeitrag news:ek7kv8$shu$1$830fa17d@news.demon.co.uk... > > "Manfred Balik" <manfred.balik@tuwien.ac.at> wrote in message > news:4566d05d$0$11352$3b214f66@tunews.univie.ac.at... >> Is it essential to connect the unused OE and GCLR-Pins of an Altera >> MAX3000A to ground??? >> the Quartus Pin-file shows GND+ for this pins, with the following meaning >> of GND+: >> -- GND+ : Unused input pin. It can also be used to report unused >> dual-purpose pins. >> -- This pin should be connected to GND. It may also be connected to >> a >> -- valid signal on the board (low, high, or toggling) if that >> signal >> -- is required for a different revision of the design. >> Can I turn on/off the usage of this OE-Pins somewhere in Quartus or where >> can I see the usage??? >> >> Thanks, Manfred >> > > The unused inputs do not affect internal logic; but if you leave a CMOS > input floating, there is a risk of charge build-up on the gate capacitance > of the input transistors. If the gate voltage is somewhere in-between Vdd > and Vss, both the N-channel and P-channel transistors conduct, cuasing an > increase in power consumption. Thanks for the answer, but it's still not clear to me: Can I turn on/off the usage of this OE and GCLR-Pins somewhere in Quartus or where can I see the usage??? In the block diagrams of the CPLD the OE is a control signal of the "I/O Controll Block" - in my opinion OE is either in use everytime or I have to turn it on/off somewhere!!! How does these pins work? Thanks, ManfredArticle: 112648
"Sean Durkin" <news_nov06@durkin.de> wrote in message news:456a8e5d$1@news.fhg.de... > PeteS wrote: >> On the S3, at least, VccAux powers the JTAG chain, part of the init >> setup and the DCMs. I don't believe it powers anything else. > It usually supplies input and output buffers for LVDS as well (at least > it does in Virtex2 Pro and Virtex 4), even if the bank those IOs are in > is supplied with i.e. 3.3V. > > cu, > Sean > ...except for the differential termination bit. That seems to be powered from VCCO. Pure genius. Cheers, Syms.Article: 112649
Hi! It is necessary to write one linker script for each ublaze (one "*.elf" for each ublaze). When you add software application project, you have to specify the ublaze in that software works. Saludos
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