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On Sun, 19 Nov 2000 04:14:44 +0000 (UTC), V Ram <ipickledthefigsmyself@mrbourns.com> wrote: >Hello! > >I have a few questions regarding synthesizing VHDL... > >Is there a website or document that describes what parts of VHDL >are/aren't synthesizable? I have the Designer's Guide to VHDL (Ashenden) >but I have no clue how synthesizable his code is... > >Typically the code I've written is simple enough that is has >synthesized(MaxPlus II & FPGA Express), but I might want to use variables >or do a few other things and I don't know what's suggested or not. > >My biggest complaint about Ashenden's book is that he doesn't really give >you clues as to what design method(s) you should take if you want your >designs to be synthesizable. > >Any hints, tips, website or recommended books would be nice to know about. synthesizable subset is usually vendor dependent but there is an effort to standardize the subset; you can get more info here http://www.eda.org/vhdlsynth/. Another option would be to read the definition of one vendor. Synopsys DC is the de-facto standard but getting their docs is not easy. You can download Synplify (from www.Synplicity.com) or Leonardo (from www.exemplar.com) and read their docs. If you ignore the fpga specific stuff from these two, you get a pretty good description of synthesizable vhdl subset. Muzaffer http://www.dspia.comArticle: 27351
hello: I am doing a design for a project.It's function can be implemented,but when it always works,it is not stabilization.who can help me? I may send my source code to you. thanks a lotArticle: 27352
An odd number of bits in error are detected by a CRC as long as x-1 is a factor of the generator. There is no length limit. That is because if the polynomial representing the error pattern has an odd number of nonzero terms, it cannot have x=1 as a root, and therefore is not a multiple of such a generator (patterns accepted as valid are those which, as polynomials, are multiples of the generator). A two-bit error pattern has a polynomial representation of the form x^j ( 1 + x^k). For this to be a multiple of the generator, the generator must divide 1 + x^k (since the generator always has a nonzero constant term, it cannot have common factors with x^j). For CRC-16 and CRC-CCITT, the smallest such k is 32,767. Therefore, 32,767 bits is the length limit beyond which two-bit error patterns may be missed, for these two generators. -Dan On 16 Nov 2000 12:15:37 -0800, Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: >dempson@actrix.gen.nz (David Empson) writes: >> Well, let us start with the well known mathematical properties of a >> correctly implemented 16-bit CRC (e.g. CRC-CCITT or CRC-16), courtesy of >> Tanenbaum. It will detect errors as follows: >> >> - All single bit errors (as does a simple checksum) >> - All double bit errors >> - All errors with an odd number of bits >> - All burst errors of 16 bits or less >> - 99.997% of 17 bit burst errors >> - 99.998% of 18 bit or longer burst errors > >Some of those claims (specifically the double-bit and odd-number-of-bits) >are only true if the block size is below a maximum. I don't know offhand >what the maximum is, but it's under 65536 bits. Proof left as an >exercise to the reader. >Article: 27353
Greetings all,
I'm currently working on a project where I would like to be able to
upload revisions of the FPGA map into the SEEPROM while the circuit is hot.
My question essentially is this:
From what I hear, Xilinx FPGAs (XC4005XL in this case) are SRAM based, is it
possible/do-able providing the circuitry is there, to reprogram the SEEPROM
via the fpga? (Small microcontroller in the core, which could work with such
signals.)
Or is the FPGA pretty well dependant upon the SEEPROM?
And for the record, yes I am aware that if something happens in terms of a
power failure, it would go, "byebye"
Article: 27354I could write a long mail about it, but this link will do just as well : http://www.electronicnews.com/enews/news/5476-322NewsDetail.asp "Rambus’ runaway patent claims could extend even further than just chipsets, to ASICS, programmable logic and graphics chips, according to Jim Handy, chief analyst at the GartnerGroup Inc.’s Dataquest unit. " Rambus's swarm of bogus patents is approaching fast, any thoughs about the "Rambus toll" ? Eric.Article: 27355
Sure, there's no problem with reprogramming the SEEPROM via the FPGA, although you will have to add connections to get to the pins. The SEEPROM is used only while the FPGA is loading,after that it is a useless appendage. The FPGA core doesn't have to be a microcontroller either. Presuming the program is downloading from some external source, all that is required is a fairly simple state machine. I'd leave a connector on the board to allow either a cable download to the FPGA or a direct reprogram of the SEEPROM just in case you give it a bad load, so that you have a recovery path. Akito wrote: > > Greetings all, > > I'm currently working on a project where I would like to be able to > upload revisions of the FPGA map into the SEEPROM while the circuit is hot. > My question essentially is this: > From what I hear, Xilinx FPGAs (XC4005XL in this case) are SRAM based, is it > possible/do-able providing the circuitry is there, to reprogram the SEEPROM > via the fpga? (Small microcontroller in the core, which could work with such > signals.) > Or is the FPGA pretty well dependant upon the SEEPROM? > > And for the record, yes I am aware that if something happens in terms of a > power failure, it would go, "byebye" -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27356
"Muzaffer Kal" <muzaffer@dspia.com> wrote in message
news:cuqe1t82rp7lkc50pudtfrbpec42qvuon0@4ax.com...
> >Is there a website or document that describes what parts of VHDL
> >are/aren't synthesizable? I have the Designer's Guide to VHDL (Ashenden)
> >but I have no clue how synthesizable his code is...
Ben Cohen's books go to some effort to point out which parts of the language
are and are not synthesizable, although as the other poster mentioned, it
varies a little depending on whose synthesis tool you're using.
In general, if it would be impossible or "really hard" to support in
synthesis, the tool won't support it. E.g., no files, no hard-coded delays
("wait for 3.7 ns"), no floating point arithmetic, etc. Things that fall
into the vendor specific category are items such as alias support (Synopsys
has lots of bugs with them, Synplify has a few problems), record support
(support is similar to aliases), configurations (many tools have no support,
Synplify supports "reasonable" usage of them), multiplication and division
(other than with constants of powers of two, which is easy -- better tools
will actually go and build you a multiplier, although you may or may not
like its implementation), etc.
High-end logic synthesis tools tend to contain features such as state
machine re-coding, automatic pipeline generation, and help for logic
partitioning/placement and replication. Unfortunately there's not a lot of
correlation between "high end tool" and "supports a really large portion of
the VHDL language."
---Joel Kolstad
Article: 27357I've just upgraded my NT PC to a 600MHz PIII from a 450MHz PII and, to my surprise, there's no discernable improvement in speed. Synplify is exactly the same and the Xilinx PAR improves by a measly 2-3 min on a run that used to take just over an hour. Am I doing something wrong or are these processes so memory bound that I might as well use anything as long as its got 100MHz SDRAM ? [or an Athlon PC with DDR memory]. Both PCs have 100MHz motherboards & I did remember to set the L2 cache size entry in the registry. With 384MB of memory I'm nowhere near the swapping limit.Article: 27358
You are probably still in the memory bounded part of the curve. I went from a dual PPro 200 w/256MB to a dual PII-800 w/ 1GB, and saw about an 8x improvement in both synplicity and PAR run times, which was much more than I expected. On the other hand, my laptop is a 466 MHz tecra w/ either 64MB or 128 MB RAM (can't remember). It is so much slower (more than 30x slower than the PIII), that it isn't worth even attempting synthesis or PAR on anything much. Rick Filipkiewicz wrote: > > I've just upgraded my NT PC to a 600MHz PIII from a 450MHz PII and, to > my surprise, there's no discernable improvement in speed. Synplify is > exactly the same and the Xilinx PAR improves by a measly 2-3 min on a > run that used to take just over an hour. > > Am I doing something wrong or are these processes so memory bound that I > might as well use anything as long as its got 100MHz SDRAM ? [or an > Athlon PC with DDR memory]. > > Both PCs have 100MHz motherboards & I did remember to set the L2 cache > size entry in the registry. With 384MB of memory I'm nowhere near the > swapping limit. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27359
Hi. Has anyone had success in building their own jtag programmer for use with the "webpack" software from xilinx?Article: 27360
Daniel Nilsson schrieb: > > Hi. > Has anyone had success in building their own jtag programmer for use with > the "webpack" software from xilinx? Not with webpack but with foundation and XABEL CPLD working with Parallel Port. We built about 10 of them for students use, works fine. We used the schematic published by Xilinx greetings, Bertram -- Bertram Geiger, bgeiger@aon.at HTL Bulme Graz-Goesting - AUSTRIAArticle: 27361
Article: 27362
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STILL DON'T BELIEVE??? THAN JUST READ THE ARTICLE.
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2. IS OK WITH THE POST OFFICE OR IS IT MAIL FRAUD?
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Well, everyone who sends me a buck has a good chance of getting A LOT
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SO WHAT DO YOU DO TO MAKE LOADS OF CASH?????
For starters , make sure you print a copy of this article NOW, so you
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than you thought possible by doing something so easy!
Read this entire message carefully! Follow the simple directions and
watch the CASH come in! It's easy. It's legal. And, your investment is
only $6.00 (Plus postage)
Here are the 3 easy steps to success:
STEP 1: Get 6 separate pieces of paper and write the following on each
piece of paper
"PLEASE PUT ME ON YOUR MAILING LIST."
Now get 6 US $1.00 bills and place ONE inside EACH of the 6
pieces of paper so the
bill will not be seen through the envelope (to prevent thievery). Place
one paper in each of the 6 envelopes and seal them. You should now have
6 sealed envelopes, each with a piece of paper stating the above phrase,
your name and address, and a $1.00 bill. Mail the 6 envelopes to the
following addresses:
#1) Danny
Spiegel
22 Nehring Ave.
Staten Island, NY, 10314
USA
#2) G Kraft
66 Davis Tee Drive
Sheridan,WY 82801-6024
USA
#3) J. Bailey
102 Monoponsan Drive
Stevensville MD 21666
USA
#4) J. Masten
180 Willoughby Cannery RD
Queen Anne, MD 21657
USA
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685 W 2050 N
Provo,UT 84604
USA
#6) Angela M
Box 585 Colonel By Drive
Ottawa , Ontario
K1S 5B7
Canada
STEP 2: Now take the #1 name off the list that you see above, move the
other names up (6 becomes 5, 5 becomes 4, etc...) and add YOUR Name
as number 6 on the list.
STEP 3: Change anything you need to, but try to keep this article as
close to original as possible. Now, post your amended article to at
least 200 newsgroups. All you need is 200, but remember, the more you
post, the more CASH you make! Keep a copy of these steps for yourself
and, whenever you need CASH, you can use it again, and again.
DIRECTIONS FOR HOW TO POST TO NEWSGROUPS
Step 1) You do not need to re-type this entire letter to do your own
posting. Simply put your cursor at the beginning of this letter and drag
your cursor to the bottom of this letter, and select 'copy' from the
edit menu. This will copy the entire letter into the computer's memory.
Step 2) Open a blank 'notepad' file or word perfect and place your
cursor at the top of the blank page. From the 'edit' menu select
'paste'. This will paste a copy of the letter into notepad so that you
can add your name to the list.
Step 3) Save your new notepad file as a .txt file. If you want to do
your postings in different settings, you'll always have this file to go
back to.
Step 4) Use Netscape or Internet explorer and try searching for various
newsgroups (on-line forums, message boards, chat sites, discussions.)
Step 5) Visit these message boards and post this article as a new
message by highlighting the text of this letter and selecting paste from
the edit menu. Fill in the Subject, this will be the header that
everyone sees as they scroll through the list of postings in a
particular group, click the post message button. You're done with your
first one! .THAT'S IT!
All you have to do is jump to different newsgroups and post away, after
you get the hang of it, it will take about 30 seconds for each
newsgroup!
**REMEMBER, THE MORE NEWSGROUPS YOU POST IN, THE MORE CASH YOU
WILL MAKE!! BUT YOU HAVE TO POST A MINIMUM OF 200**
You will begin receiving CASH from around the world within days! You
may eventually want to rent a PO Box due to the large amount of mail you
will receive. If you wish to stay anonymous, you can invent a name to
use, as long as the postman will deliver it.
**JUST MAKE SURE ALL THE ADDRESSES ARE CORRECT.**
HOW DOES IT WORK?
If from the 200 postings, you receive only 5 (conservation estimate)
reply, you will make $5.00
If from those 5 people who replied to you make a minimum 200 postings
each, and only 5 respond to each of them, each with your name writing at
#5, you will get $25.
Now those 25 people will make 200 postings with your name at #4 and only
5 reply to each, YOU will receive $125.
Those 125 people will turn around and make a minimum of 200 postings
with your name at #3 and each get 5 replies, YOU will make an additional
of $625.
>>From those 625 people make a MINIMUM 200 postings with your name at #2
and each get 5 replies , YOU will receive $3125.
And still those 3125 people make the minimum postings with your name at
#1 and each get % replies,
YOU WOULD HAVE ACCOMPLISHED TO MAKE $15,625 WITH YOUR ORIGINAL
INVESTMENT OF ONLY $6.
ISN'T THAT AMAZING!?! Remember the five people replying is a very
conservative estimate. Imagine how many people will be responding to you
once you make your minimum of 200 postings.
AMAZING!!!!!!!!!!!!!!!
When your name is no longer on the list, you just take the latest
posting in the newsgroups, and send out another $6.00 to names on the
list, putting your name at number 6 again. And start posting again.
The thing to remember is that thousands of people all over the world
are joining the internet and reading these articles everyday JUST LIKE
YOU are now!! So, can you afford $6.00 and see if it really works?? I
think so...
People have said, "what if the plan is played out and no one sends you
the CASH? So what! What are the chances of that happening when there are
tons of new honest users and new honest people who are joining the
internet and newsgroups everyday and are willing to give it a try?
Estimates are at 20,000 to 50,000 new users, every day, with thousands
of those joining the actual internet.
IMPORTANT:
PLAY FAIRLY and HONESTLY ..
This program remains successful because of the honesty and integrity of
the participants and by their carefully adhering to the directions. Look
at it this way. If you are a person of integrity, the program will
continue and the CASH that so many others have received will come your
way.
This is not a rip-off; it is not indecent; it is not illegal; and it is
virtually no risk - it really works!!!! If all of the following
instructions are adhered to, you will receive extraordinary dividends.
HONESTY IS THE BEST POLICY.
You don't need to cheat the basic idea to make the CASH!! You are using
the Internet to advertise your business. What is that business? You are
creating a mailing list of people who are interested in home based
computer and online business and methods of generating income at home.
Remember, people send you a small fee to be added to your mailing list.
It is legal. what will you do with your list of thousands of names?
That's up to you." So, build your mailing list, keep good accounts,
declare the income and pay your taxes. By doing this you prove your
business intentions. Keep an eye on the newsgroups and when the cash has
stopped coming (that means your name is no longer on the list), you just
take the latest posting at the newsgroups, send another $6.00 to the
names stated on the list, make your corrections (put your name at #6)
and start posting again.
SO WHAT ARE YOU WAITING FOR???
$$$!!!$$$!!!$$$!!!$$$!!!$$$!!!$$$!!!$$$!!!$$$!!!$$$!!!
GOOD LUCK!!!
NOTES:
*1. In some countries, the export of the country's exchange is illegal.
But you can get the license to do this from the post office, explaining
the above statements (that you have an online business, etc. You may
have to pay an extra tax, but that's OK, the amount of the incoming CASH
is HUGE! And as I said, a few countries have that restriction .
*2. You may want to buy mailing and e-mail lists for future CASH. (Or
Database or Spreadsheet software.)
*3. If you're really not sure or still think this can't be for real,
please print a copy of this article and give it to someone who really
needs the CASH, and see what happens.
*4. You will start getting responses within 1-2 weeks, it depends.
Article: 27363longwayhome@my-deja.com writes: > I'm trying to get started in evolutionary hardware experiments as a > hobby. I'm finding it hard to get a handle on what hardware I ought to > buy to get started. Last time I thought I had found a suitable board > (one of the 300 dollar xess boards) someone helpfully informed me that > it was flash ram based and therefore only good for something like 50k > rewrites. You have been falsly (or at least incompletely) informed by that "someone". I will take the "300 dollar xess boards" to be their 84 pin chip boards, the XS95-108+, XS40-005XL+, XS40-005E+, XS40-010XL+, XS40-010E+ and XSP-010+ models (Range $159-239). Of these the XS95-108+ is based on an CPLD (XC9500 series), with is Flash-ROM based, and so subject to limited reprogramming. All other 5 models are based on FPGA (XC4000 or Spartan series) which are SRAM based and so have unlimited reprogrammability. Bigger problem for "evolutionary hardware" (whatever that is) may be that the XC4000 and Spartan series FPGAs only allow reconfiguring of the entire chip, not partial reconfigurability. > Could someone give me suggestions for suitable hardware (i have a 2k > USD max budget for this). That will even allow you to go for the 240 pin chip boards XSV-50 to XSV-800 ($699-1599) which use Virtex series FPGAs (also SRAM based) which are larger and partial-reconfigurable. > I really just want to feed it input and check > its output (input and output as numbers if possible). Here the small 84 pin boards have the problem, that they have no RS232 on them, you need to do PC parallel port programming (at least for input, they have one 7seg LED for output). The 240 pin boards have RS232 and 2 7seg LED on them. For all the boards try Xess-es catalogue: http://www.xess.com/ho04000.html Now if the Virtex boards just had an (36/72 bit) DRAM socket (or at least 18 bit SRAM) and an EIDE interface, they would be the ideal board for me. As it is I am going to have to do some self designed hardware, so I can just as good take an standard no IO hardware board as base of my stuff and save all the IO hardware I do not need. Loses the advantage of an "off the shelf" board. Bummer. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, MysticArticle: 27364
Magnus Homann <d0asta@mis.dtek.chalmers.se> writes: > Philip Freidin <philip@fliptronics.com> writes: > > > While I could make quite a few comments on this, > > I think I will just give you the link: > > > > > > http://www.xilinx.com/prs_rls/xilinxwin.htm Anyone know what features the 2 patents mentioned in the text forbid Altera (and anyone else) from including in their devices? Who else is endangered for being sued off of the market (I assume that Xilinx took on Altera as largest competitor in 1993)? Filing date 1993 suggests something that appeared in XC4000. Dammit, after over 2 months of investigating the various chips, I was just thinking of using Xilinx chips (the do seem to be the best). Now I am going to have to rethink that (I belong to the dying breed of people who think that societies wellfare should stand above maximal individual profit). Eith FLEX (and "its derivative programmable logic devices" = ACEX and APEX?) illegal, what remains? (P.S. does anyone have a statemewnt from Altera, what they are intending of doing?). MAX has not got enough FFs for me, one design I intend needs an 16x36bit register file). Altera has no CPLDs (real product term based devices) with block RAMs). Atmel 40K simply tops out too soon (I may possibly need 100k gates) and Atmel explicitely boasts about its patents on the first page of their data sheets. Actel are anti-fuse, I need SRAM for experimenting. Lucent Orca FPGAs, are they infringing? Tools running on Linux (just after I found some for Virtex). Cypress Delta39K CPLDs, anyone knows what they are like? Tools? > I'm sure this is all in the society's best interest. After all, that's > what patents are for. You can bet your soul on that :-). Hell and Eternal Damnation for all patent lawmakers and lawyers. (Now why can't we get black magic or Voodoo to work? :-)) I suppose this has once again demonstrated that patent law has got to be abolished. Completely. No replacement. The belief it was founded on (patents are better (or less bad) than trade secrets) simply is false. Trade secrets can be reverse engineered, patents are anti-competitive devices that can not be legally circumvented. P.S. Have you signed the "no software patents in Europe" petition? http://petition.eurolinux.org/ -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, MysticArticle: 27365
Ray Andraka wrote: > You are probably still in the memory bounded part of the curve. I went from a > dual PPro 200 w/256MB to a dual PII-800 w/ 1GB, and saw about an 8x improvement > in both synplicity and PAR run times, which was much more than I expected. On > the other hand, my laptop is a 466 MHz tecra w/ either 64MB or 128 MB RAM (can't > remember). It is so much slower (more than 30x slower than the PIII), that it > isn't worth even attempting synthesis or PAR on anything much. > > Just to be clear here - when I say memory bound I meant that execution speed was being limited by memory access & not by raw compute power. Looking at task manager while Synplify & PAR were running I see a max useage of about 70MB during synthesis & 140-180MB during PAR. In fact I can run them both together & still have 100MB of memory free. What you might be seeing on the laptop is the catastrophic collapse in performance that happens when NT starts to swap even slightly. Unix/Linux virtual memory handling and process scheduling is still vastly better than anything MS can produce.Article: 27366
Yes, this is the way to do it. Watch the loading on the add control though. The path from the control flip-flop through 33 loads, up the carry chain to the MSB (in a 16 bit add-mux you have 16 loads for the mult-and, 16 for the luts and 1 for the carry in) is likely the worst case path in your design by a significant margin. Keep the control flip-flop right next to the LSB for best results with a single control. You can substantially reduce the clock period by duplicating the control at the cost of some area. In the case of my FFT macro, I've got a duplicated control flip-flop for every fourth bit on the add-muxes. I got that thing humming along at 153 MHz (16 bits, with upto 19 internal bits)in the slow -4 Virtex 100. Jan Gray wrote: > > Many datapath circuits consist of an adder followed by a mux: > o = add ? a + b : c; > o = add ? a + b : a ~& c; > etc. For example, this structure appears in the PC/adder unit of xr > processors: > addr_nxt = use_ea ? ea : pc + pc_incr; > > I just figured out how to implement this add/mux circuit efficiently, one > LUT per bit, for Virtex family architectures. See > http://www.fpgacpu.org/index.html#001112 for more detail. (Yes, I'm sure > many of you old hands at Virtex have already figured this out.) > > Jan Gray, Gray Research LLC > FPGA CPU News: www.fpgacpu.org -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27367
The EDIF netlist has the LUT primitives. If you refer to the Xilinx Library guide, there is more explanation there as to the operation etc of the primitive. When you assign the INIT= attribute, assigns the bits to combinations of I(3:0) in the manner you'd expect. Beware that the place and route is generally free to rotate those pin assignments however. When it does that, it also permutes the LUT contents to keep the changes transparent to the user.. You don't use LUT primitives for RAM or Shift register mode; instead you use the RAM and SRL16 primitives, also described in the library guide. These elements appear in the edif netlist as RAM and SRL16 primitives, not LUTs. Please look at the Xilinx library guide, which is part of the tools documentation package (which I believe you can also obtain from the website). Any of the primitives in the library can appear in the edif file, and the library guide does a pretty good job of describing the attributes you can/must put on them. Richard Meester wrote: > > Phil and steve, > thanks for the comments. > > Phil James-Roxby wrote: > > > Richard Meester wrote: > > > > > > Hi All, > > > > > > I am looking for some in depth information about LUTS and edif file > > > specs. > > > > > > I know what luts are, and what they can be used for, but is there any > > > information on what equations to use when, and what init strings to > > > provide. I read an article which described some of this by a truth > > > table, but i would much like a xilinx documentation on the technical > > > part of a lut. > > > > > > About the edif specs. I would like to know how to write a valid edif > > > file structure. Do you know of any information about this, except for > > > the $300,00 specs itself. > > > > I've done a fair bit of work involving LUTs and EDIF. I'm not entirely > > sure what you mean in the second paragraph, in terms of equations and > > init strings. The init string for a LUT in a Xilinx piece is simply the > > 1 bit wide 16 entry look-up table. Is this what you mean? > > Yes, the 16*1 lookup table. The articel i read described this lookup table, > but i am not sure which inputs are for which part of the lookup table. I did > what steven and you are suggesting and trying to figure out the edif from > simple vhdl examples. This also gives me lut equations. I.e. for an AND i > qet the equation I0 + I1 and an init string of E. > in a 4lut lookup table i would have something simular. But which input is > connected to which place in the table. This is needed to calculate the init > string. > I.e. > > | 00 | 01 | 10 | 11 -> these are I0 and I1, but which one is I0 > and which one is I1. Is the first one I0? > -------------------------- > 00 | > 01 | > 10 | > 11 | > > above are I2 and I3. But which is which. Is the first one I2? > > Secondly, the luts can also behave as rams, and LFSR. How do you connect > such a lut, and how does the table look like. > > > > > I sussed how to write EDIF by looking at the output of synthesis tools, > > its all ASCII and quite humanly readable. To check the syntax of my > > handwritten EDIF, I used Active VHDL which will tell you the line number > > of your first error and not much else. But its about as good as it > > gets. > > I believe Brad Hutchings and the people at BYU have an EDIF parser > > written in Java which is free. This may be useful for you. > > Phil > > Indeed the parser is for free. But it does just that, it parses, not > generates. But i will look in the generated edifs, and try figuring it out > myself. > > Richard > > > > > -- > > --------------------------------------------------------------------- > > __ > > / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 > > \ \ Staff Software Engineer Fax: Unreliable use email :-) > > / / Loki/DARPA Email: phil.james-roxby@xilinx.com > > \_\/\ Xilinx Boulder > > --------------------------------------------------------------------- > > -- > Quest Innovations > tel: +31 (0) 227 604046 > http://www.quest-innovations.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27368
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Article: 27369On Sat, 18 Nov 2000 01:22:16 GMT, Brian Davis <brian_m_davis@my-deja.com> wrote: >John Larkin wrote: >> >> We recently made a small change to one of the FPGAs, and it wouldn't >> configure. It turns out that the older .RBT files had 283,424 config >> bits, and the new ones (from F3.1 software) have 283,432. >> > > Check out Xilinx answer database record 7318; it looks >like releases 2.1i SP2 and later pad the 4000 series >bitstreams by an extra byte to fix a JTAG startup problem. > >Brian Davis > > >Sent via Deja.com http://www.deja.com/ >Before you buy. Brian, thanks. I guess I'm tool-bit again! JohnArticle: 27370
[Discussing table lookup approach to CRCs.] > Unfortunately, the need for a clocked read out of the > BlockRAMs means this takes two cycles (Peter, here is > another case where the clocked read is a nuisance! Is > there really no way to design these things with flow-thru > address->data? ) Does it really cost another cycle? Why can't you pipeline things? I'm assuming you want to register the address in your register. Why can't you just feed the input to that register (from the previous cycle) into the RAM address pins and use the register in the RAM block. You may need to make another copy if you need that for other uses. -- These are my opinions, not necessarily my employers. I hate spam.Article: 27371
Jan, Interesting. With respect to the interconnect, we have developed several hardware and software functionality, to connect them at high speed, and create a network of these devices, which is scalable not only in the chip, but also between chips and black boxes. Current rates at 200MBit/sec, but with virtex-E parts 600MBit/sec (full duplex) may be achieved. Richard Maybe this is of interest to you. Jan Gray wrote: > Three years ago I wrote here that FPGA-based single-chip MIMD > multiprocessors were becoming feasible. I have now placed-and-routed a > toy/proof-by-example 8-way multiprocessor-on-a-chip. I simply took the > "work-in-progress" GR0000 compact 16-bit RISC core, which is now > floorplanned as 8 rows by 6 columns of CLBs, plus two block RAMs (for a > byte-addressable 16-bit wide 1 KB dual-ported embedded instruction/data > memory), and instanced eight of them as 2 rows by 4 columns of processors > plus memories, in the smallest Virtex-E part, the 16x24-CLB, 4x4 block-RAM > XCV50E. > > More details, including a floorplan diagram, are at www.fpgacpu.org. > > So here's a rule of thumb, approximately correct. Take a Virtex-E data > sheet, look up the number of block RAMs, divide by 2 (4) and that's how many > streamlined 16-bit (32-bit) RISC CPUs will fit in that device. In larger > devices, with 12 columns of CLBs per column of block RAM, it may be possible > to double that number again, or else use the remaining 50% of the > programmable logic for other purposes, like cache control, CPU interconnect, > and custom datapath functions. For example, in an XCV600E, which has 12 > rows x 6 columns of block RAMs, you get 36 16-bit RISCs with 50% uncommitted > CLBs. Whether such a thing can run full out without melting into slag > remains to be seen! > > Looking way ahead, there will be lots of interesting work to come, in memory > architectures, interconnect architectures, programming models and tools, > etc. > > Jan Gray, Gray Research LLC -- Quest Innovations tel: +31 (0) 227 604046 http://www.quest-innovations.comArticle: 27372
> While I could make quite a few comments on this, > I think I will just give you the link: > > > http://www.xilinx.com/prs_rls/xilinxwin.htm Alteras response is here: http://www.altera.com/html/new/pressrel/pr_litigation1.html DinesArticle: 27373
>hello: > I am doing a design for a project.It's function can be implemented,but when it always works,it is not stabilization.who can help me? I may send my source code to you. > thanks a lot I think the problem concerned timing issue. you should give a very careful post-simulation before fabricating it. where are you?lian tang or nan shan.Article: 27374
http://www.delphion.com/details?pn=USRE034363__ http://www.delphion.com/details?pn=US04642487__ The second patent by William S. Carter contains claims for configurable logic arrays in general and therefore could be attacked with publications in the field of cellular automata from the sixties and seventies. (von Neuman, Schaffner, Minnik, ...) The claims are for a logic array that contains a general interconnect structure as well as a special interconnect structure. Most work from the sixties will have only one or the other, but one might be able to find some weird publication that proposes to use both. The other patent is not as vulnerable to this attack, because it restricts itself to integrated circuits. Although one could try to attack on the basis that the restriction to integrated circuits is not relevant to the invention. I hope that Altera succeeds in attacking these patents. In article <8van4k$t66$1@news.inet.tele.dk>, "Dines Justesen" <dcj_k@rescom.dk> wrote: > > While I could make quite a few comments on this, > > I think I will just give you the link: > > > > > > http://www.xilinx.com/prs_rls/xilinxwin.htm > > Alteras response is here: > > http://www.altera.com/html/new/pressrel/pr_litigation1.html > > Dines > > Sent via Deja.com http://www.deja.com/ Before you buy.
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