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There is a book called "VHDL and AHDL Digital System Implementation", ISBN=0138570876. http://www.amazon.com/exec/obidos/ISBN%3D0138570876/optimagicsprograA/002-52 16702-7732604 There are significantly more programmable logic books listed on The Programmable Logic Jump Station at http://www.optimagic.com/books.html. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- D. Polo wrote in message <7glbgn$qi0$1@talia.mad.ttd.net>... > Hi, I'm a student and I'm trying to learn about AHDL. > > Does anybody know a good book about AHDL and max plus II software?? > > >Thanks in advance (and sorry for my english) > >D.Polo >mallacan@teleline.es > > >Article: 16176
Hi, Where can I find a good explanation on the differences between these. I know VHDL(ahdl) and have programmed all types but don't know the differences (pretty pathetic huh). Thanks-Uday -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 16177
I have heard of people who used a cooking oven to apply BGA parts.
They aligned the chip with a bit of glue and preheated the oven
and put the board in. Supposedly it worked.
I would suspect that your yeild wouldn't be that high and it would
really suck to have an $50+ part wasted.
Bill
>>>>> "Ray" == Ray Andraka <randraka@ids.net> writes:
Ray> BGA devices are definitely not for the home builder. Even
Ray> the adapters that are available require the BGA to be
Ray> soldered to them. There is simply no reliable way to connect
Ray> to a BGA other than properly mounting it to a pwb. There are
Ray> vendors that will attach small quantities of BGAs to adapters
Ray> such as those made by ironwood and emulation technologies.
Ray> Even then, the cost of that service is not all that cheap.
Ray> Waveflow soldering doesn't work for BGAs either. You need to
Ray> use IR techniques.
--
Brave New Waves, "http://www.radio.cbc.ca/programs/bnw/"
Article: 16178On 6 May 1999 16:52:20 -0400, elh@vu-vlsi.ee.vill.edu (Edward L. Hepler) wrote: >In article <3731c513.698195@news.wxs.nl>, hhk <hhk@wxs.nl> wrote: >>The big problem is: What are PLD gates, ASIC gates an what are FPGA >>gates. And above all: What is the DIFFERENCE between these types of >>gates. > >ASIC gate counts are traditionally given in terms of "equivalent 2-input >nands"... When looking at the cells (gates) that make up a standard >cell library, usually the area of a 1X drive 2-input nand is used >as the "area" of 1 gate. [...] > Most FPGA >vendors base the gate counts that they can accomodate by estimating >the number of gates that it might take to replace the look-up table >and flipflops... I don't think this is true. Some weight the "gate count" towards a mixture of gate-only cells and cells containing flip-flops. Whether or not this is accurate depends on both the weighting factor, and your design style. >But consider a large decoder. It may be primarily combinatorial and not >need the 4 flipflops attached to each cell. Further, it may need many >cells to produce the desired combinatorial result(s). [...] >this means that each LUT is only giving me the equivalent of about 3 gates! Equally, consider the same large decoder, pipelined for high speed operation. Now the ASIC requires many more gates, to build the pipeline registers, whereas the FPGA practically gives them away for free. Or a design that requires even a small amount of internal RAM... the FPGA may well have a RAM mode where a single LUT gives 16 or 32 bits of storage (100-200 gates in an ASIC). >The overall design synthesizes to about 24,000 (equivalent 2-input nands) >when targeting a standard-cell library, but requires an FPGA that claims >to be capable of 80,000 to 100,000 gates when targeting the FPGA... Another data point - a pipelined design that would take 57600 "ASIC gates" used only 60% of a "62000 gate" FPGA. In this case the FPGA vendor was pessimistic, selling themselves short... >So, to summarize, the definition of a gate for ASICs is pretty well defined, >but the gate count for FPGAs and the way a gate is defined for them is >pretty much a spec-man-ship game that the marketing folks play! That's one way of looking at it - another way would be to say (and they do) that a "gate count" for FPGA is HIGHLY approximate and depends on design style as much as anything else. The moral might be: design to the architecture you will be using. If you will be using both FPGA and ASIC, it is probably better to design to the FPGA (since it is smaller). The result will port to ASIC, maybe requiring more gates than you expect, being (e.g.) more heavily pipelined than a pure ASIC design, but that is unlikely to increase cost by much. (It may also be faster!) Whereas if you design to ASIC you may find, as Dr. Hepler did, a pathological case where you lose greatly on portability. (This may not matter if you see the FPGA as merely a prototyping tool - or if a few pennies on the ASIC part cost is a serious consideration) - BrianArticle: 16179
Take a look at http://tkt.cs.tut.fi/~havu/pci/models.html rene >Article: 16180
--------------5AF2AA759D17D947CB6F5D24 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Sorry, the correct link is http://www.tkt.cs.tut.fi/~havu/pci/models.html Rene Becker wrote: > Take a look at > > http://tkt.cs.tut.fi/~havu/pci/models.html > > rene > > > --------------5AF2AA759D17D947CB6F5D24 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Sorry, the correct link is <p><a href="http://tkt.cs.tut.fi/~havu/pci/models.html">http://www.tkt.cs.tut.fi/~havu/pci/models.html</a> <br> <p>Rene Becker wrote: <blockquote TYPE=CITE>Take a look at <p> <a href="http://tkt.cs.tut.fi/~havu/pci/models.html">http://tkt.cs.tut.fi/~havu/pci/models.html</a> <p>rene <p>></blockquote> </html> --------------5AF2AA759D17D947CB6F5D24--Article: 16181
In article <7guras$7vc$1@info3.fnal.gov>, husby@fnal.gov (Don Husby) writes: > One thing we're considering is putting a through-hole under each pad. > For prototypes, this appears to be a better solution than using a socket > because it gives access to every pin without introducing much extra > capacitance or inductance which can be significant at 200 MHz. The > worry here is that the BGA will not seat well into a donut-shaped solder > bump, or that the through-hole will drain the solder away. One solution > to this would be to pre-fill each hole with a high-temperature solder. > Obviously, for production we would re-do the boards to eliminate the holes. > When we first came to make a board with a BGA device, the sub-contracter who manufactures our boards suggested that we put a via under every pad. Apparently, providing the via has a very small diameter (I think < 25 thou was specified), there is no problem with solder being sucked into the via. This proved very useful. The BGA device was a VME - PCI bridge. On the prototype board the VME side was working, but absolutely nothing was happening on the PCI side. Eventually, in desperation, I stuck a bit of thin wire down the via for the PCI bus grant signal, heated it up with the soldering iron, and waggled it up and down a bit. That fixed the problem. It also proved handy during the debugging phase. Again a bit of thin wire down the via gives you a convenient test point for attaching probes. Admittedly we haven't manufactured many of these boards, but we haven't seen any other problems with the BGA devices. I would be inclined to keep the holes for production unless there was any evidence that they were reducing reliability - the ability to rework the occasional bad joint is well worth having. MartinArticle: 16182
In article <3732CDD0.D37175E4@Sun.COM>, roman pollak <roman.pollak@Sun.COM> wrote: > I guess you don't have the whole waveflow soldering >machine at home, don't you ? Usually you have! An electrical powered cooking oven works reasonably well for prototyping once you have all parameters set (like with professional equipment). After applying solder paste to the pads of the conventional SMDs you can place them into the paste. BGAs only need some flux paste whose "glueiness" (is that a legal english word?) helps to keep them in place. The balls melt during the soldering process and adhesive forces center the BGA on the pads (even if they are off to the next row...!) Worked well for several boards with MPC860 and quite some conventional SMDs. To fine tune your process get ahold of the recommended thermal curves of the manufacturers and use a thermo element thermometer. Hot air guns (even the professional SMD ones using nitrogen to avoid scorching) aren't good for BGAs since they tend to blow the parts from the pads. Good luck! -- Stefan Wimmer Cellware Broadband Email sw@cellware.de Rudower Chaussee 5 WWW http://www.cellware.de/ 12489 Berlin, Germany Visit my private Homepage: Love, Electronics, Rockets, Fireworks! http://www.geocities.com/CapeCanaveral/6368/Article: 16183
Lars Fomsgaard wrote: > Hello world > > I have the following problem with the netlister in the Foundation software > from Xilinx: > > In my VHDL-code I have defined an input as an 8 bit bus, but in the design > I only use the 7 most significant bits (at least after the last > modification). During syntax check and synthesis I get no warnings or > errors, during implementation the program terminates due to an unused > input. > > Of course I could change my entity, and modify the design all the way > through the design hierarchy, but I would prefer if someone could inform me > on a more elegant solution. If I se this from a "documentational" point of > wiev this would also be prefered, as the formulas, I try to implement > contains a divide by 2. > > Thanks > Lars Hi Lars, first of all some questions? - Do you use Foundation 1.5i ? - When you generate a version report the version of conv_acs.dll is 5.53h or smaller? => When you can answer both questions with yes I can help you! So send me an email and I send you a newer version! cul8r, AS (Andreas)Article: 16184
Young- I would agree Emil Blaschek wrote. Namely, the Altera VHDL compiler is ok for simple stuff. However, using Design Compiler is overkill. I recommend you look at the commercially available FPGA synthesis tools: FPGA Express, which is engineered by Synopsys and sold and supported by Viewlogic, Synplify from Synplicity, or Leonardo from Exemplar. If you go to the Viewlogic, Synplicity, and Exemplar web sites you can get free evaluations of each of these tools. Regards, -Jim ymlee wrote: > Dear fellows, > > I am trying to implement an interface module between > the 8 bits ISA bus standard and a modified version of 32 bits > 80386 CPU bus. > > Currently I use the MAXPLUS II 9.01 patched to 9.04 to compile > my VHDL design of the target interface module. > > I have lots of troubling in implementing the bus interface since > the MAXPLUS II 9.01 for PC reports so many internal error(which > means their bugs unhandled). > > Many of the errors are related to bit slice handling and 32 bit > bidirectional data bus handling etc. > > Do you recommend the Altera MAXPLUS II 9.01 as a VHDL compiler for Altera > FPGA implementation of your VHDL design? > (I use Altera's EPF10KA50VBC356-2 FPGA) > > If not, what else can you recommend? > > I'd like to hear from you. > > With regards, > > Young -- -------------------------------------------------------- James R. Kipps FPGA Marketing Manager jkipps@viewlogic.com Phone: (508) 303-5246 --------------------------------------------------------Article: 16185
Altera should be happy to provide you with an AHDL "manual". It is their publication # P25-04802-02 (number in corner on back cover). There is also a MAX+II GETTING STARTED book, # P25-04803-03 I can't imagine Altera's reps charging you for these books. As for running and using the MAX+II software, a pretty decent base package is available (free) for download from the ALTERA website. I've used A, X, and L FPGAs and software, and MAX+II/AHDL is far and away the easiest package to learn. If you start playing with the SW, I don't think you'll need the manuals at all. The online help (help menu, that is) is pretty good. The learning curve from dead start to "I compiled a real design" is the fastest and easiest of any of the vendors' packages. Don't be intimidated, your chances of success are very good. -- Bob Elkind "D. Polo" wrote: > > Hi, I'm a student and I'm trying to learn about AHDL. > > Does anybody know a good book about AHDL and max plus II software?? > > Thanks in advance (and sorry for my english) > > D.Polo > mallacan@teleline.esArticle: 16186
I have an undergrad student working on an independent project to
design a game that drives a VGA monitor using a Xilinx 4005XL. He's
doing the design with the Prentice-Hall student edition of Xilinx
Foundation. The book with the software seems less than comprehensive,
and he asked me to post the following question for him.
Please reply to jangjus@eng.auburn.edu.
Yours
Richard Chapman
------------------------------------------------------
Below is an excerpt from my logfile of the synthesis of one of my
projects using Xilinx Design Manager. I need to know what these
warnings and errors mean (as precisely as possible). Thanks! -
Justin Jang
This project has a single ABEL (not VHDL) source which was synthesised
into a netlist using the "Macro" option. This was then updated in the
schematic editor to make it into a component, which was placed and
wired with signals. This schematic was then converted to a netlist,
which was simulated successfully. The problem arose when trying to
synthesise all the way to a .bit file. The log file follows:
ngdbuild -p xc4000xl -uc D:\Justin\XCproj\CLKTEST2\Clktest2.ucf
d:\justin\xcproj\clktest2\clktest2.edn xc4000xl.ngd
ngdbuild: version M1.3.7
Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -p xc4000xl -uc D:\Justin\XCproj\CLKTEST2\Clktest2.ucf
d:\justin\xcproj\clktest2\clktest2.edn xc4000xl.ngd
Launcher: Using rule EDN_RULE
Launcher: clktest2.ngo is up to date
Reading NGO file "D:/Justin/XCproj/CLKTEST2/xproj/ver1/clktest2.ngo" ...
Reading component libraries for design expansion...
Launcher: Using rule EDN_RULE
Launcher: VIDTEST.ngo is up to date
Loading NGO design "D:\Justin\XCproj\CLKTEST2\xproj\ver1\VIDTEST.ngo"...
Annotating constraints to design "CLKTEST2" from constraint file
"D:/Justin/XCproj/CLKTEST2/Clktest2.ucf"...
Constraints specified from "D:/Justin/XCproj/CLKTEST2/Clktest2.ucf" can
override design file constraints.
Running Timing Specification DRC...
Timing Specification DRC complete with no errors or warnings.
Running Logical Design DRC...
WARNING:basnu - Attribute "LOC" on "CLOCK" is on the wrong type of object.
Please see the "Attributes, Constraints, and Carry Logic" section of the
Libraries Guide for more information on this attribute.
WARNING:basnu - logical net "U1/VCC_net" has no load
WARNING:basnu - logical net "U1/GND_net" has no load
Logical Design DRC complete with 3 warning(s).
NGDBUILD Design Results Summary:
There were 3 Logical Design DRC warnings.
409 total blocks expanded.
Writing NGD file "xc4000xl.ngd" ...
Writing NGDBUILD log file "xc4000xl.bld"...
NGDBUILD Done.
map -p xc4005xl-1-pc84 -o map.ncd -u ../xc4000xl.ngd clktest2.pcf
map: version M1.3.7
Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
Reading NGD file "../xc4000xl.ngd"...
Using target part "4005xlpc84-1".
MAP xc4000xl directives:
Partname="xc4005xl-1-pc84".
Do not remove unused logic.
No Guide File specified.
No Guide Mode specified.
Covermode="area".
Coverlutsize=4.
Coverfgsize=4.
Perform logic replication.
Pack CLBs to 100%.
Processing logical timing constraints...
Running general design DRC...
WARNING:basnu - Attribute "LOC" on "CLOCK" is on the wrong type of object.
Please see the "Attributes, Constraints, and Carry Logic" section of the
Libraries Guide for more information on this attribute.
WARNING:baste:267 - The OPTIMIZE attribute located on VIDTEST symbol `U1' does
not have a corresponding OPT_EFFORT property. The default effort (NORMAL)
will be used.
Verifying F/HMAP validity based on pre-trimmed logic...
Processing global clock buffers...
Before logic optimization BEST
Number of nodes = 479
After logic optimization BEST
Number of nodes = 170
TIME in milliseconds = 10050
Number_of_levels = 5
Optimizing...
ERROR:x45ma:2 - An invalid component appears to be driving the clock buffer
BUFFCLK symbol `$I3' (output signal=$Net00002_). It is illegal to drive this
BUFFCLK fast clock buffer with anything other than an IPAD. This includes
trying to drive the BUFFCLK with internal logic.
ERROR:x45ma:22 - BUFFCLK symbol `$I3' (output signal=$Net00002_) can only drive
IOB pins. Therefore, BUFFCLK symbol `$I3' (output signal=$Net00002_) is not
a legal load.
Errors have been found in this design. No output files have been written.
Article: 16187I actually prefer Ironwood Electronics to Emulation Technology. http://www.ironwoodelectronics.com/ I find Ironwood to be less expensive, more responsive, and provide shorter lead times. Everything I have ordered so far (about seven different part numbers) have been from stock for at least part of the order quantity. The back orders have typically been filled in two weeks. For BGA's, they have two basic solutions. One is a BGA-to-PGA with the same land patteren as the BGA. The other is a much larger adapter on 10 mil spacing.Article: 16188
Richard and 'jangjus', Go to http://support.xilinx.com and search for 'buffclk'. This should return a Xilinx Answer that will address your error. Instead of using a BUFFCLK, try using a BUFGLS as your global clock buffer. Search for 'VCC_net' on http://support.xilinx.com and the resulting Answer should give you information on that warning as well. Finally, you should be sure to place your pin locking constraint on the IPAD or the pad net (i.e., not on the net driving your FFs or memories). Answers to most of these types of questions can be found on http://support.xilinx.com. Regards, Hobson Frater Xilinx Applications Richard Chapman wrote: > I have an undergrad student working on an independent project to > design a game that drives a VGA monitor using a Xilinx 4005XL. He's > doing the design with the Prentice-Hall student edition of Xilinx > Foundation. The book with the software seems less than comprehensive, > and he asked me to post the following question for him. > > Please reply to jangjus@eng.auburn.edu. > > Yours > Richard Chapman > ------------------------------------------------------ > > Below is an excerpt from my logfile of the synthesis of one of my > projects using Xilinx Design Manager. I need to know what these > warnings and errors mean (as precisely as possible). Thanks! - > Justin Jang > > This project has a single ABEL (not VHDL) source which was synthesised > into a netlist using the "Macro" option. This was then updated in the > schematic editor to make it into a component, which was placed and > wired with signals. This schematic was then converted to a netlist, > which was simulated successfully. The problem arose when trying to > synthesise all the way to a .bit file. The log file follows: > > ngdbuild -p xc4000xl -uc D:\Justin\XCproj\CLKTEST2\Clktest2.ucf > d:\justin\xcproj\clktest2\clktest2.edn xc4000xl.ngd > ngdbuild: version M1.3.7 > Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. > > Command Line: ngdbuild -p xc4000xl -uc D:\Justin\XCproj\CLKTEST2\Clktest2.ucf > d:\justin\xcproj\clktest2\clktest2.edn xc4000xl.ngd > > Launcher: Using rule EDN_RULE > Launcher: clktest2.ngo is up to date > Reading NGO file "D:/Justin/XCproj/CLKTEST2/xproj/ver1/clktest2.ngo" ... > Reading component libraries for design expansion... > > Launcher: Using rule EDN_RULE > Launcher: VIDTEST.ngo is up to date > Loading NGO design "D:\Justin\XCproj\CLKTEST2\xproj\ver1\VIDTEST.ngo"... > Annotating constraints to design "CLKTEST2" from constraint file > "D:/Justin/XCproj/CLKTEST2/Clktest2.ucf"... > Constraints specified from "D:/Justin/XCproj/CLKTEST2/Clktest2.ucf" can > override design file constraints. > > Running Timing Specification DRC... > Timing Specification DRC complete with no errors or warnings. > > Running Logical Design DRC... > WARNING:basnu - Attribute "LOC" on "CLOCK" is on the wrong type of object. > Please see the "Attributes, Constraints, and Carry Logic" section of the > Libraries Guide for more information on this attribute. > WARNING:basnu - logical net "U1/VCC_net" has no load > WARNING:basnu - logical net "U1/GND_net" has no load > Logical Design DRC complete with 3 warning(s). > > NGDBUILD Design Results Summary: > There were 3 Logical Design DRC warnings. > 409 total blocks expanded. > Writing NGD file "xc4000xl.ngd" ... > > Writing NGDBUILD log file "xc4000xl.bld"... > > NGDBUILD Done. > > map -p xc4005xl-1-pc84 -o map.ncd -u ../xc4000xl.ngd clktest2.pcf > map: version M1.3.7 > Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. > Reading NGD file "../xc4000xl.ngd"... > Using target part "4005xlpc84-1". > MAP xc4000xl directives: > Partname="xc4005xl-1-pc84". > Do not remove unused logic. > No Guide File specified. > No Guide Mode specified. > Covermode="area". > Coverlutsize=4. > Coverfgsize=4. > Perform logic replication. > Pack CLBs to 100%. > Processing logical timing constraints... > Running general design DRC... > WARNING:basnu - Attribute "LOC" on "CLOCK" is on the wrong type of object. > Please see the "Attributes, Constraints, and Carry Logic" section of the > Libraries Guide for more information on this attribute. > WARNING:baste:267 - The OPTIMIZE attribute located on VIDTEST symbol `U1' does > not have a corresponding OPT_EFFORT property. The default effort (NORMAL) > will be used. > Verifying F/HMAP validity based on pre-trimmed logic... > Processing global clock buffers... > Before logic optimization BEST > Number of nodes = 479 > After logic optimization BEST > Number of nodes = 170 > TIME in milliseconds = 10050 > Number_of_levels = 5 > Optimizing... > ERROR:x45ma:2 - An invalid component appears to be driving the clock buffer > BUFFCLK symbol `$I3' (output signal=$Net00002_). It is illegal to drive this > BUFFCLK fast clock buffer with anything other than an IPAD. This includes > trying to drive the BUFFCLK with internal logic. > ERROR:x45ma:22 - BUFFCLK symbol `$I3' (output signal=$Net00002_) can only drive > IOB pins. Therefore, BUFFCLK symbol `$I3' (output signal=$Net00002_) is not > a legal load. > Errors have been found in this design. No output files have been written. > >Article: 16189
Hi Roman, Have you looked at Advanced Interconnect's BGA to PGA adapters? I believe that you could use them for both prototyping and lower volume production. I would suggest sending the chip and adapter to a house that can mount the devices as opposed to the BGA 'socket' type adapters since there may be issues with the socket type adapters, especially if they are used in a production product. GL, -Chris > I'm looking for some kind of socket or other tool for bga device. > Actually, I'm wondering how other people deal with BGA devices as well. > > > regards roman >Article: 16190
craig_jacobs@asl-tk.com wrote: > > In article <373197BB.7986C450@Sun.COM>, > roman pollak <roman.pollak@Sun.COM> wrote: > > Hi, > > > > I'm looking for some kind of socket or other tool for bga device. > > Actually, I'm wondering how other people deal with BGA devices as well. > > > > regards roman > > > > I've never used the following product, but I am looking for bga prototyping > devices also and I found a few web sites. You may want to check out this web > site. > > http://www.emulation.com/catalog/off-the-shelf_solutions/prototyping_adapters/ > > I remember coming across a few other web sites but I disremember the addresses Its _too_ expensive. udv CsabaArticle: 16191
Hi all, I have some very eager experts in CPLD and FPGA technology at my disposal! Come visit our web-site for more info! -- Mark Tootell Field Sales Engineer Eurodis Bytech MTootell@Bytech.eurodis.com 0410 726497 Visit our website at:- http://www.eurodis-bytech.ltd.ukArticle: 16192
Hallo, I am working on a PCI slave..... There a cores available from several vendors. Xilinx, Altera etc. with PCI cores to promote their ICs and purchase a lot of ICs volumes for commercial products. See also http://www.plda.com for a company where cores and several ready PCI boards you can buy... Do not forget the effort to modifiy driver software e.g. under Windows NT, what might be possible to adapt in special cases. Kind Regards Juergen Otterbach, Alcatel Telecom Pete Zaitcev schrieb: > > Hi everybody: > > I am sorry if this is an FAQ or if I am not doing my homework. > Basically I am a software guy who tries to size up a small hardware > project (does it send shivers up your spine?). > > Can someone tell me if it is possible to purchase a shrink > wrapped design which has PCI on one side and 8 bit bus > on other side? (I think it is called a "macro"). > I have no idea about attainable size in contemporary > FPGAs... PCI looks awfuly complex to me. > > If such a thing exists, where can I find one? And how much that may cost? > A million $$? A hundreed thousand? > > An option which I would be eager to find is a GPL-ed FPGA design > for a PCI slave. I heard there is a guy named J. H. Allen who made > a design (a CPU) under a sort of GPL (LGPL). That sounds wonderful for a > software person, so that I can change stuff myself, and contribute > it back. This is not a requirement though. > > Thanks, > --PeteArticle: 16193
rk wrote: > > hi, > > no, i don't have a waveflow soldering iron machine at home. nor am i very good > with a regular soldering iron. > > but there's one company who makes bga sockets with an array of pins on the > bottom. this is bolted down to the board (carefully) and all those little > contacts are made. i do have one such socket but don't recall the vendor's name > off-hand - home today - but can look it up if anyone's interested. i haven't > actually tried it out yet as it's for a board that i have planned in the next > month or so. > > rk > > _________________________________________________________ > > roman pollak wrote: > > > Pascal Dornier wrote: > > > > > > Stephen Maudsley wrote in message <7gsd3h$sei$1@plutonium.btinternet.com>... > > > > > > > >roman pollak <roman.pollak@Sun.COM> wrote in message > > > >news:373197BB.7986C450@Sun.COM... > > > >> Hi, > > > >> > > > >> I'm looking for some kind of socket or other tool for bga device. > > > >> Actually, I'm wondering how other people deal with BGA devices as > > > >well. > > > > > > > >Haven't used sockets since PGA. Solder them direct and get the board > > > >right first time. > > > > > > Amen. BGA, it takes balls... > > > > When you can do it with soldering iron, that's ok for you. But I got a > > problem with it. I guess you don't have the whole waveflow soldering > > machine at home, don't you ? > > > > regards roman I think the socket you mention sounds like the one from OZTEK we used on a small module a while ago. It was to allow post-package testing of a new CPU. It works fine but is insanely expensive - about $1200 AND you had to pay another $400 if you wanted the metal heatspreader that goes under the top cover instead of the standard plastic one.Article: 16194
comp.arch.fpgaUSB standardAnyone know who publishes the current standard for USB? We need both the hardware spec and the protocol.Hul hytuts@iglou.comPath: ix.netcom.com!chippy.visi.com!news-out.visi.com!newspeer.monmouth.com!newsfeed.mad.ttd.net!telefw1.teleline.es!usenet@teleline.esArticle: 16195
Se vende finca rústica de 3,2 hectáreas en el término municipal de Sevilla
la Nueva (Madrid), a 200 metros de urbanización "Los Cortijos", abierta a la
sierra de Guadarrama. ¡¡GRAN OCASIÓN!!.
*E-Mail: lezcanov@teleline.es
*Teléfono: 629 92 93 54
Article: 16196In article <373197BB.7986C450@Sun.COM>, roman pollak <roman.pollak@Sun.COM> wrote: >Hi, > >I'm looking for some kind of socket or other tool for bga device. >Actually, I'm wondering how other people deal with BGA devices as well. EMULATION TECHNOLOGIES (1-800-ADAPTER?) makes BGA sockets. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 16197
Visit www.usb.org - you can download the complete standard with a lot of additions, white papers and application notes from there. Rune Baeverrud Hul Tytus wrote in message <3734600f.0@news.iglou.com>... >comp.arch.fpga >USB standard > >Anyone know who publishes the current standard for USB? We need both the >hardware spec and the protocol. > >Hul hytuts@iglou.comArticle: 16198
Hello:
I realize that the APEX FPGA was just recently released but does
anyone know of any PCI prototyping boards that use this chip? I am
looking to prototype some new graphics algorithms and need a board with
preferably several such devices along with the ability to add RAM (SDRAM
etc.) and a RAMDAC for video out. Thanks in advance.
Atif Zafar
Indiana University
Regenstrief Institute
Zafar_A@regenstrief.iupui.edu
Article: 16199
This is a multi-part message in MIME format.
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This daisy.c program might be useful to generate a combined bitstream.....
to be downloaded as a single bitstream.....
Code is pretty self explainatory....Reply back if you should have problems...
-Sandeep
Rolf Aengenendt wrote:
> We have the following problem concerning configuring Xilinx FPGA's
> (XC4000E):
>
> We have a pcb using one main LCA Xc4010 and an additional (optinonal) LCA
> device, which is only used and mounted in special cases. The devices are
> configured in slave daisy chain mode by a microcontroller, so the "dout" of
> the main LCA is connected to the "din" of the optinonal LCA and the other
> controll-lines (done, prog, cclk) are connected together and routed to one
> port of the mic.
>
> Until now, only the main LCA was placed on the pcb and so the mic saw only
> one device. However, when you use two devices in chain, the xilinx prom
> formatter builds *one* program mcs-file. But what we want to have are two
> independent files, so while the system startup is going on, the mic could
> decide weather to program only the main LCA, or -when present- build the
> data stream for the main and the optional LCA on its own and program the
> both devices.
>
> So we would link two independent mcs or binary LCA-files to our mic-code
> (firmware)
>
> Does anybody have an idea how to create the combined bitstream?
>
> Thx a lot
>
> Rolf Aengenendt
>
> _______________________________________________________________
> Rolf Aengenendt, Lumino GmbH, Krefeld, Germany
> fon: +49-2151-8196-76 fax: +49-2151-8196-6676
> mailto:raengen@lumino.de
> internet: http://www.lumino.de
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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
extern char *ctime ();
static int reversebits ();
main (argc, argv)
int argc;
char *argv[];
{
int checksum;
int length;
int bits;
int i, j;
static unsigned char data[19*9000]; /* big enough for 3195 */
/* There are 5 xilinxes on the AVD Board */
/*ifil.rbt is xilinx_0 to be programmed*/
length = readrbt ("fir20tap.rbt", data, 77);
/*qfil.rbt is xilinx_1 to be programmed*/
length = readrbt ("compare1.rbt", data, length);
length = readrbt ("compare2.rbt", data, length);
bits = length * 8;
data[0] = reversebits (0x00);
data[1] = reversebits (0x09);
data[2] = reversebits (0x0f);
data[3] = reversebits (0xf0);
data[4] = reversebits (0x0f);
data[5] = reversebits (0xf0);
data[6] = reversebits (0x0f);
data[7] = reversebits (0xf0);
data[8] = reversebits (0x0f);
data[9] = reversebits (0xf0);
data[10] = reversebits (0x00);
data[11] = reversebits (0x00);
data[12] = reversebits (0x01);
data[13] = reversebits (0x61);
data[14] = reversebits (0x00);
data[15] = reversebits (0x0d);
data[16] = reversebits (0x63);
data[17] = reversebits (0x6f);
data[18] = reversebits (0x75);
data[19] = reversebits (0x6e);
data[20] = reversebits (0x74);
data[21] = reversebits (0x65);
data[22] = reversebits (0x72);
data[23] = reversebits (0x33);
data[24] = reversebits (0x2e);
data[25] = reversebits (0x6c);
data[26] = reversebits (0x63);
data[27] = reversebits (0x61);
data[28] = reversebits (0x00);
data[29] = reversebits (0x62);
data[30] = reversebits (0x00);
data[31] = reversebits (0x0a);
data[32] = reversebits (0x33);
data[33] = reversebits (0x31);
data[34] = reversebits (0x39);
data[35] = reversebits (0x35);
data[36] = reversebits (0x50);
data[37] = reversebits (0x51);
data[38] = reversebits (0x32);
data[39] = reversebits (0x30);
data[40] = reversebits (0x38);
data[41] = reversebits (0x00);
data[42] = reversebits (0x63);
data[43] = reversebits (0x00);
data[44] = reversebits (0x09);
data[45] = reversebits (0x39);
data[46] = reversebits (0x34);
data[47] = reversebits (0x2f);
data[48] = reversebits (0x30);
data[49] = reversebits (0x32);
data[50] = reversebits (0x2f);
data[51] = reversebits (0x31);
data[52] = reversebits (0x31);
data[53] = reversebits (0x00);
data[54] = reversebits (0x64);
data[55] = reversebits (0x00);
data[56] = reversebits (0x09);
data[57] = reversebits (0x31);
data[58] = reversebits (0x38);
data[59] = reversebits (0x3a);
data[60] = reversebits (0x35);
data[61] = reversebits (0x36);
data[62] = reversebits (0x3a);
data[63] = reversebits (0x32);
data[64] = reversebits (0x39);
data[65] = reversebits (0x00);
data[66] = reversebits (0x65);
data[67] = reversebits (0x00);
data[68] = reversebits (0x00);
data[69] = reversebits (0x2e);
data[70] = reversebits (0x62);
data[71] = reversebits (0xff);
data[72] = reversebits (0xf2);
data[73] = reversebits (bits >> 16);
data[74] = reversebits (bits >> 8);
data[75] = reversebits (bits >> 0);
data[76] = reversebits (0xff);
data[length++] = 0xff; /* loads 12 extra bits (?) */
data[length++] = 0xff;
/*
(void) printf ("unsigned char otto_xilinxdata[] = {");
for (i = 0; i < length; i += 8) {
(void) printf ("\n\t");
for (j = i; j < length && j < i+8; j++) {
if (j + 1 == length) {
(void) printf ("0x%02x", data[j]);
} else {
(void) printf ("0x%02x, ", data[j]);
}
}
}
for (i = 0, checksum = 0; i < length; i++) {
checksum += data[i];
}
(void) printf ("\n};\nint otto_xilinxdatalen = %d;\n", length);
(void) printf ("int otto_xilinxchecksum = %d;\n", checksum);
*/
for (i = 0; i < length; i += 8) {
/*(void) printf ("\n\t");*/
for (j = i; j < length && j < i+8; j++) {
if (j + 1 == length) {
/* (void) printf ("0x%02x", data[j]);*/
data[j] = reversebits(data[j]);
(void) printf ("%c", data[j]);
} else {
/* (void) printf ("0x%02x, ", data[j]);*/
data[j] = reversebits(data[j]);
(void) printf ("%c", data[j]);
}
}
}
exit (0);
}
static int reversebits (x)
int x;
{
int y;
y = ((x & 0x55) << 1) | ((x & 0xaa) >> 1);
y = ((y & 0x33) << 2) | ((y & 0xcc) >> 2);
y = ((y & 0x0f) << 4) | ((y & 0xf0) >> 4);
return (y);
}
int readrbt (filename, data, length)
char *filename;
unsigned char *data;
int length;
{
struct stat info;
char *timeStamp;
FILE *rbt;
int c;
int current, i;
int bits;
if ((rbt = fopen (filename, "r")) == NULL) {
perror (filename);
exit (2);
}
if ((fstat (fileno (rbt), &info))<0) {
perror (filename);
exit (2);
}
current = 0;
bits = 0;
/* Skip header lines. */
while ((c = getc (rbt)) != EOF && !isdigit (c)) {
while (c != '\n' && c != EOF) {
c = getc (rbt);
}
}
/* Discard length line. */
while (c!='\n') {
c = getc (rbt);
}
while ((c = getc (rbt)) != EOF) {
switch (c) {
case '0':
break;
case '1':
current |= (1 << bits);
break;
case '\n':
continue;
default:
(void) fprintf (stderr,
"Unknown character: \'%c\', %x\n", c, c);
exit (4);
};
bits++;
if (bits == 8) {
data[length++] = current;
current = 0;
bits = 0;
}
}
(void) fprintf (stderr, "%6d bits, ", length*8 + bits);
if (bits != 0) {
printf ("(%d extra) ", bits);
while (bits < 8) {
current |= (1 << bits);
bits++;
}
data[length++] = current;
}
(void) fprintf (stderr, "%5d bytes", length);
(void) fclose (rbt);
timeStamp = ctime (&info.st_mtime);
(void) fprintf (stderr, ", %.24s.\n", timeStamp);
return (length);
}
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