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"Symon" <symon_brewer@hotmail.com> wrote in message news:44f72a50_1@x-privat.org... > I think you've missed the point I'm trying to make. I'm trying to point > out > that small planes do not have a bypass resonance problem. > 1) With a tiny plane, the resonance between it and the bypass caps is at a > very high frequency. > 2) At this frequency, the bypass caps have a high ESR. > 3) This damps the resonance so much that you don't have a any problem at > all. > > At no point did I say that a 1uF cap had a SRF of 3GHz. (BTW, you're quite > correct that it's at about 10MHz) I did mention its ESR at 3GHz to give an > example of how the ESR increases with frequency. The frequency we are > talking about is the resonant frequency between the plane and the bypass > caps. > > HTH, Syms. You mentioned an ESR at 3 GHz. ESR is important near SRF and at resonance points, not much use elsewhere. as for your points 1) your cap/board resonance problems are just moved with smaller planes, not removed. Another problem is resonance either between caps with SRFs far enough apart (given the associated Qs) or caps that are inductively far apart, forcing the different SRFs to the perspective of a specific noise source. 2) an ESR of 1 ohm isn't so bad if you have a dozen caps "nearby" but 83 mOhms still isn't that great for high power problems 3) Ah, life with no problems. Resonance between the cap and plane might not be such a problem if the Q drops as the frequency increases, but what impedance solution are you achieving? If you need more high-SRF caps to bring down the impedance beyond the SRF, the effective ESR of the "solution" is lower and resonance is still a consideration. Isn't it? I'd suggest that most of the folks in this forum don't need the 3GHz performance because the packaged digital logic is loally bypassed in the package and the silicon so they don't "feel" much above many 10s of MHz, at least according to the recent Howard Johnson talk. It's the other discretes on board - the unpackaged or "low package" devices that feel the brunt of the plane problems. ...and EMI.Article: 107726
Hi, I am new to Xilinx ISE webpack 8.2. Occationally, I selected "none" selection among (simulation, synthesis/implementation only, etc.) to a test bench VHDL file. I cannot add the test bench to make a simulation anymore. When I add existing file, it says that file has been added, it is not necceary to add it. How to make it reappear in the source tab? Thank you very much.Article: 107727
I've reversed engineer the CableServer communication with Impact and written from scratch a brand new CableServer. Currently only Parallel III cable is implemented, but new cables can be added very easily. I will post the project on sourceforge.net next week. Antti wasn't really helpful to come up with a name for the project, so it will be called "cblsrv" :) I've uninstalled windriver from Win32 and Impact seems to work without it if only "cblsrv" is used. I guess the same is true for Linux as well. ZoltanArticle: 107728
zcsizmadia@gmail.com wrote: > I've reversed engineer the CableServer communication with Impact and > written from scratch a brand new CableServer. Currently only Parallel > III cable is implemented, but new cables can be added very easily. I > will post the project on sourceforge.net next week. Awesome :)Article: 107729
On a sunny day (31 Aug 2006 13:00:28 -0700) it happened "zcsizmadia@gmail.com" <zcsizmadia@gmail.com> wrote in <1157054428.957257.6810@m73g2000cwd.googlegroups.com>: >I've reversed engineer the CableServer communication with Impact and >written from scratch a brand new CableServer. Currently only Parallel >III cable is implemented, but new cables can be added very easily. I >will post the project on sourceforge.net next week. > >Antti wasn't really helpful to come up with a name for the project, so >it will be called "cblsrv" :) > >I've uninstalled windriver from Win32 and Impact seems to work without >it if only "cblsrv" is used. I guess the same is true for Linux as >well. > >Zoltan P cable 3 in Linux? Was on my site already: http://panteltje.com/panteltje/fpga/p3j-0.2.tgz Does direct IO, you need to be root. And you do not need impact at all. What am I missing in your idea?Article: 107730
"Tommy Thorn" <tommy.thorn@gmail.com> wrote in message news:1156988022.907422.112710@i3g2000cwc.googlegroups.com... > Roger wrote: >> Is it possible to revert to a Webpack license once the full 60 day >> evaluation license has expired on ISE? If so how is it best done? There's >> nothing obvious in ISE so is it a question of re-installing to get the >> licensing screen back to allow the Webpack code to be inserted? > > Yes (AFAIK, this will require a reinstallation). Be sure to note that > WebPACK supports only a subset of the features of the full ISE. If you > need fx. to program Virtex 5 devices, then WebPACK won't do you any > good. > > Tommy > Thanks Tommy, I'll reinstall when the evaluation runs out. I know WebPack only supports a subset but I think I can get by for now. The full ISE is very expensive so I need to. Rog.Article: 107731
Steve Underwood wrote: > fpga_toys@yahoo.com wrote: >> pomerado@hotmail.com wrote: >> >>> As a general rule, the more complicated the HR form is, the less useful >>> it is for evaluating technical people. >> >> >> By that rule, a blank page of paper is best .... I think we have a >> scaling problem. >> > Well, I guess they should leave the boxes for "Name" "Job grade" and > "Employee number" :-) And make the box by "sex" big enough to contain "Occasionally". Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 107732
Thius is like a programmer cable SDK for Impact. Some advanteges: 1. All devices supported which are supported by Impact. 2. 3rd part programmer cables can be used with Impact (e.g. USB) I have another project www.sourceforge.net/projects/xilprg, which supports multiple Xilinx devices and no need for any driver on Linux. BTW xc3sprog does the same. 1.For example USB programmer cables can be implemented easily. Jan Panteltje wrote: > On a sunny day (31 Aug 2006 13:00:28 -0700) it happened "zcsizmadia@gmail.com" > <zcsizmadia@gmail.com> wrote in > <1157054428.957257.6810@m73g2000cwd.googlegroups.com>: > > >I've reversed engineer the CableServer communication with Impact and > >written from scratch a brand new CableServer. Currently only Parallel > >III cable is implemented, but new cables can be added very easily. I > >will post the project on sourceforge.net next week. > > > >Antti wasn't really helpful to come up with a name for the project, so > >it will be called "cblsrv" :) > > > >I've uninstalled windriver from Win32 and Impact seems to work without > >it if only "cblsrv" is used. I guess the same is true for Linux as > >well. > > > >Zoltan > > P cable 3 in Linux? > Was on my site already: > http://panteltje.com/panteltje/fpga/p3j-0.2.tgz > Does direct IO, you need to be root. > And you do not need impact at all. > > What am I missing in your idea?Article: 107733
Hi John, I interspersed some comments. "John_H" <newsgroup@johnhandwork.com> wrote in message news:h8HJg.175$za1.32@news02.roc.ny... > > You mentioned an ESR at 3 GHz. ESR is important near SRF and at resonance > points, not much use elsewhere. > Agreed, but ESR is a bad thing at the SRF. It's a good thing at parallel resonance, e.g. between bypass caps and plane. That's what I'm addressing here. > > as for your points > 1) your cap/board resonance problems are just moved with smaller planes, not > removed. > Agreed, so if this parallel resonance moves to a point where one of the resonant parts, in this case the bypass cap, has a large ESR, the resonance can't happen as it's damped away. > > Another problem is resonance either between caps with SRFs far > enough apart (given the associated Qs) or caps that are inductively far > apart, forcing the different SRFs to the perspective of a specific noise > source. > > 2) an ESR of 1 ohm isn't so bad if you have a dozen caps "nearby" but 83 > mOhms still isn't that great for high power problems > I'm not suggesting that decoupling at 3GHz is useful. In my opinion, any decoupling at frequencies above a few hundred MHz is useless because of the package impedance at these frequencies. > > 3) Ah, life with no problems. Resonance between the cap and plane might not > be such a problem if the Q drops as the frequency increases, but what > impedance solution are you achieving? If you need more high-SRF caps to > bring down the impedance beyond the SRF, the effective ESR of the "solution" > is lower and resonance is still a consideration. Isn't it? > To repeat myself, I don't care what the impedance is above a few hundred MHz. This 'threadlet' starting with Martin's post is addressing mini-plane resonance issues, not bypassing. I wish I'd never mentioned 3 bloody GHz now! :-) > > I'd suggest that most of the folks in this forum don't need the 3GHz > performance because the packaged digital logic is loally bypassed in the > package and the silicon so they don't "feel" much above many 10s of MHz, at > least according to the recent Howard Johnson talk. It's the other discretes > on board - the unpackaged or "low package" devices that feel the brunt of > the plane problems. > > ...and EMI. > > Agreed! Cheers, Syms.Article: 107734
On a sunny day (31 Aug 2006 13:51:56 -0700) it happened "zcsizmadia@gmail.com" <zcsizmadia@gmail.com> wrote in <1157057516.099489.131960@b28g2000cwb.googlegroups.com>: >Thius is like a programmer cable SDK for Impact. > >Some advanteges: >1. All devices supported which are supported by Impact. >2. 3rd part programmer cables can be used with Impact (e.g. USB) > >I have another project www.sourceforge.net/projects/xilprg, which >supports multiple Xilinx devices and no need for any driver on Linux. >BTW xc3sprog does the same. One uses the ioctl() calls IIRC, mine does direct IO. And the ioctls did not work on my box for some reason or other IIRC. All these kernel versions.... just upgraded to 2.6.17.9 #1 PREEMPT... And had to modify some driver too. Yes you are right, if you have impact working in command line mode, then it could do some more. Or maybe write something for USB that uses libusb too..... Well, the more programs the more choice, the better :-) Always nice to find soft that works.Article: 107735
fl, I believe you'll find your source file in the Libraries tab (probably under the work library), where you should be able to right-click on it and select properties. From there, you can choose the correct association and the source should then be back in the Sources tab. I hope that helps. -Kamal fl wrote: > Hi, > I am new to Xilinx ISE webpack 8.2. Occationally, I selected "none" > selection among (simulation, synthesis/implementation only, etc.) to a > test bench VHDL file. I cannot add the test bench to make a simulation > anymore. When I add existing file, it says that file has been added, it > is not necceary to add it. How to make it reappear in the source tab? > > > Thank you very much.Article: 107736
Symon wrote: >> Switchers are good for noise-tolerant high-power circuits but linears >> will remain necessary for low-noise low-power stuff like reference > voltages. >> As for the actual topic of linear being necessary for MGTs, on top of >> inherent switcher supply noise, there will be multi-tone noise from >> switching inputs on input rails and heaps of other potentially nasty >> stuff across the whole spectrum. Given the price of V2P and V4FX parts, >> I would opt for not taking any chances and go with power -> LC -> LDO -> >> C -> MGT... and read Xilinx's MGT power decoupling appnote a few times. >> >> >> Symon wrote: >>> Hi Heiner, >>> I'd be interested in the response you get for this question. As linear >>> regulators have a bandwidth of a 100kHz or so, I fail to see how they >>> provide an advantage over a filtered switcher. > Hi Daniel, > Thanks for your post, but I'm still somewhat confused. I agree that linear > regulators only work well at removing noise at low frequencies, and that > passive filtering is more effective at high frequencies. So, why not use a > fast switcher, say switching at a few MHz, and passive filter its output. > The passive filter wouldn't have a problem with "potentially nasty stuff > across the whole spectrum". > Are you saying that the MGTs are mostly adverse to low frequency noise? That > seems somewhat strange for a multi-GHz device. > BTW, I always make sure to defeat any burst modes in switcher circuits to > reduce low frequency ripple. > Thanks, Syms. Using a high-speed switching regulator helps the power filtering requirements and the switcher's ~25kHz sense circuit bandwidth may be able to do a decent job for line-load regulation too but this still leaves a gap in the 25-100kHz area where passive filters are cumbersome. BTW, when output drivers and internal logic switch, they too will generate noise on the power rails and this noise can span a very wide range depending on switching patterns. If I drive a video DAC with alternating black and white lines, I can generate some (barely measurable) noise down to half of what my horizontal sync frequency is. Every single-ended will generate similar noise on the power rails in addition to high-frequency transition spikes. Since MGTs have dedicated power pins, it is reasonable to presume some special requirements have to be met. I looked at the XUP-V2P schematics, the MGTs on this board are powered using an LDO, bulk output capacitor and 1uH inductors between bulk and each MGT power pin... looks like the MGT circuits on these dedicated power pins are primarily constant-current. Now, which frequency band are MGTs most sensitive to? I have no idea. But given that voltage variation will induce jitter and mess up thresholds in the clock recovery circuit, I would stick with LC to eliminate high-frequency noise down to ~75kHz followed by a linear to remove everything else. Spending $5 more to avoid junking a $100+ PCB and a $300+ FPGA sounds like a good deal to me - at least for smal-scale productions and prototypes. -- Daniel Sauvageau moc.xortam@egavuasd Matrox Graphics Inc. 1155 St-Regis, Dorval, Qc, Canada 514-822-6000Article: 107737
Symon wrote: > I'm not suggesting that decoupling at 3GHz is useful. In my opinion, any > decoupling at frequencies above a few hundred MHz is useless because of the > package impedance at these frequencies. Which is a real design issues as we have FPGA's which have the ability to clock internally above a few hundred MHz, and the VCCINT pins have strong frequency components spaced at multiples of the LUT propagation delay, and the short inter-CLB interconnects. And, with each generation, they move higher up the scale. > To repeat myself, I don't care what the impedance is above a few hundred > MHz. This 'threadlet' starting with Martin's post is addressing mini-plane > resonance issues, not bypassing. I wish I'd never mentioned 3 bloody GHz > now! :-) All the issues are related, particularly since Austin started this thread in response to my posting that I stacked caps as a secondary check that there was enough bulk capacitance in proto layout, in a case where I thought that the chip/package was unable to handle worst case designs.Article: 107738
blisca wrote: > hi to all the ng > > for practicing vhdl at home 3 months ago i builded a modified cable 3 and i > tried to make my pc communicating with various xilinx ic's; > > with cpld no problems,the cable reads and programs correctly; > > but there is no way to communicate with xcv200 ,today i had the same with > an xcv150,TDO looks always low. > > meanwhile last time i wrote in this ng for help and today ,i bought a demo > board and a cheap cable by Digilent, > > with the Digilent cable(said able to work down to 1.8 V) my pc works fine > with the spartan 3 on the demo board > > but i am still having no result when i try to comunicate with the virtex > fpgas > > in this last attempt with xcv150 (PQ240,not easy to play and solder on it's > pin)the fpga is mounted on a scraped board,there is a linear voltage > regulator stage..i enter in it with 3.3 V > > and it gives to the fpga core the 1.8 v needed > > i set M0 M1 M2 at 101 to disable other modes than boundary scan(but boundary > scan should be always active,in every MODE(correct?)),i cutted the tracks of > the jtag so to have no conflicts > > i verified that the supplies are correctly applied > > PROGRAMS appears always high > > anyway during boundary scan check i only see TMS and TDI high and a signal > on TCK,TDO is always low :-( > > any hint will be appreciated > thanks to you all > Diego > Italy Look at your part number. Is it Virtex E, XCV200E... or original Virtex XCV200... (no E). The original virtex needs 2.5 volts core, not 1.8 HTH GaborArticle: 107739
Symon wrote: > I think you've missed the point I'm trying to make. I'm trying to point out > that small planes do not have a bypass resonance problem. > 1) With a tiny plane, the resonance between it and the bypass caps is at a > very high frequency. > 2) At this frequency, the bypass caps have a high ESR. > 3) This damps the resonance so much that you don't have a any problem at > all. > > At no point did I say that a 1uF cap had a SRF of 3GHz. (BTW, you're quite > correct that it's at about 10MHz) I did mention its ESR at 3GHz to give an > example of how the ESR increases with frequency. The frequency we are > talking about is the resonant frequency between the plane and the bypass > caps. I misunderstood. It is getting a bit pointless to continue to discuss this as the only thing that is important is how it works. We can get info on how we expect it to work by doing simulations and analysis, but measurement is the only way to be sure. But I don't think we even agree on what constitutes the requirement in terms of impedance. A tiny plane will have nearly no capacitance. The resulting resonance is not important since the plane will not be doing much good as a capacitor. I don't understand what problem is being solved by using a small power plane. A large power plane is useful when used with a combination of values of caps with low Q values. This arrangement can work well with three values of ceramic caps and one value of tantalum cap and give a relatively flat, low impedance from 1 kHz to well above a GHz. But if you cut up your power plane so that it is very small, the upper end will be limited to a few hundered MHz which is not fast enough for many applications with fast edge rates. Using a single value of ceramic cap will never provide a low impedance above 100-200 MHz and without a sizable plane will result in a high impedance that will cause edge rates to slow and potentially induce excessive bounce lowering your noise margin. With a full power plane closely coupled to the ground plane you are likely to have a resonance causing a high peak in the impedance around 100-200 MHz. Sure you can use 4 or 5 times the number of caps to lower this peak, but why do that when you can do it more easily with fewer caps?Article: 107740
John_H wrote: > I'd suggest that most of the folks in this forum don't need the 3GHz > performance because the packaged digital logic is loally bypassed in the > package and the silicon so they don't "feel" much above many 10s of MHz, at > least according to the recent Howard Johnson talk. It's the other discretes > on board - the unpackaged or "low package" devices that feel the brunt of > the plane problems. I am not aware of the HJ talk on packages limiting the need for high frequency decoupling. But I seriously doubt that this is an accurate statement if it was made. If a chip can produce a rise time of 0.5 nS then clearly the power plane is providing enough current at very high frequencies to drive the transmission line. I don't see how the chip could possibly provide enough coulombs to drive the line without the power coming from the power plane. Is it possible that HJ was referring to the packages with higher lead inductance (any type of leaded package such as SSOP, TSSOP or QFP) compared to BGA and CSP?Article: 107741
fpga_toys@yahoo.com wrote: > > >>Know what? What really bad typos indicate? Pretty clear, if someone >>affords his or her resume that little attention to detail I assume it'll >>be the same for a design. Can't use that. > > Or the person is dyslexic with a foriegn native tounge, language > impaired, but with experience and genuis in design that can easily be > offset by using good clerical assistant to help the designer with > writing, editing, and other written language issues. > Wouldn't you then expect that genius to be smart enough to have a friend critique and correct their resume? Or at least click Tools -> Spell Check? That ain't rocket science... -- Regards, Joerg http://www.analogconsultants.comArticle: 107742
Hello Joel, >>Or the person is dyslexic with a foriegn native tounge, language >>impaired, but with experience and genuis in design that can easily be >>offset by using good clerical assistant to help the designer with >>writing, editing, and other written language issues. > > > Presumably they'd mention that -- or anything else that would make them > "unusual" -- on their resume? In general, if you know you're going to be > needing "clerical" assistance in your job, presumably you'd also obtain such > assistance on your resume? > Yep. I wouldn't expect disclosure of a disability but anyone in that situation who wants to be an engineer should be smart enough to seek help writing a resume. Or at least figure out how to use the spell checker. > Joerg seems like a nice guy, I'm sure he'd give people the benefit of the > doubt. > Thanks. Yes, I would. Never had a problem hiring older folks who had health issues or disabilities. Language or anything else didn't matter either. The funniest experience: One of the guys had such a thick Vietnamese accent that sometimes folks would call on me to discuss a highly technical matter with him (and I grew up speaking German...). He was BTW an excellent technician. -- Regards, Joerg http://www.analogconsultants.comArticle: 107743
> >> Is it possible to revert to a Webpack license once the full 60 day > >> evaluation license has expired on ISE? If so how is it best done? There's > >> nothing obvious in ISE so is it a question of re-installing to get the > >> licensing screen back to allow the Webpack code to be inserted? > > > > Yes (AFAIK, this will require a reinstallation). Be sure to note that > > WebPACK supports only a subset of the features of the full ISE. If you > > need fx. to program Virtex 5 devices, then WebPACK won't do you any > > good. Just to make sure there's no misunderstanding: There's no difference (AFAIK) between installing WebPACK on a brand new computer and installing it on a box that used to have an eval version of ISE, but which have now been uninstalled. I'm not sure what happens if you try to install WebPACK while the ISE eval version remains installed, but I wouldn't recommend it. As a cautious example: I botched up an install of Altera's Nios II (deleted some files accidentally) and now I can neither uninstall nor reinstall it. It hangs during the installation. Sigh. TommyArticle: 107744
John_H wrote: > Digital circuits are clocked, extremely wideband devices. RF is typically > narrowband. Also, the power supplies are typically filtered in stages on > the receive side such that the highest level output (IF amplifier out, > perhaps) is closest to the "main" rails while the next stage down is > filtered from that filtered rail. This goes down until you're at the Low > Nois Amplifier attaches to the antenna where the power has passed through > several filter stages. If everything was connected to one power/ground > sandwich, the circuit would be losing its lunch. No sensitivity at all. This is a GPS module. The you are talking about the power normally delivered to the analog portion of a receiver design. This filtering was put on the digital section of the GPS module. The LDO accomplished *nothing* since there was no reason to suspect noise in the bandwidth the LDO could filter. Since the digital section would make its own noise, I see no point to adding an inductor to the path from the switcher to the digital LDO. The only inductor he put in the path to the RF was the ferrite which was only effective in the hunderds of MHz. There are lots of frequencies in the noise that can easily get into the RF section and mess things up. Noise does not have to be on the carrier frequency. This is a poor design and leaving off a power plane just compounds the problem. > About the only way to filter 1.5 GHz for a digital circuit - extremely > wideband by nature - is with distributed plane capacitance. > > I still suggest that RF is a different beast where power planes are no help. Isn't 1.5 GHz RF? If the noise is present on the power rail at this frequency it will be radiated by every part that is connected. This will be picked up by any other circuitry in the area and possibly even the antenna. So instead of providing power planes to prevent the high freq current from creating EMI, they are adding cans around the various circuits. The GPS module already has a can on it. Our digital design has not one, but three to isolate each section of the circuit!!! I am totally convinced that this guy is winging it and has no concept of how to deal with EMI. Basically he has been working at this place for the last 10 years (where cost is often not an issue) and has not learned much about how to best deal with EMI. Instead he has learned a handful of "tricks" that work as long as you don't care about how much your solution costs and you don't mind tweeking the design after it is built.Article: 107745
On 31 Aug 2006 09:49:04 -0700, in sci.electronics.design fpga_toys@yahoo.com wrote: > >Joerg wrote: >> Know what? What really bad typos indicate? Pretty clear, if someone >> affords his or her resume that little attention to detail I assume it'll >> be the same for a design. Can't use that. > >Or the person is dyslexic with a foriegn native tounge, language >impaired, but with experience and genuis in design that can easily be >offset by using good clerical assistant to help the designer with >writing, editing, and other written language issues. hehe, I walked into the local language school, here in spain, having problems translating my CV. The average tranlator cannot comprehend technical terms like "Video Post Production facility engineer" martinArticle: 107746
> I am exploring the possibility to use the npi(native port interface) towards the MPMC2(multi port memory controller). > I will use the BRAM as FIFO on the write side of the RAM > > Does anyone have any experience with this I am about to start testing a NPI periperal, so soon I will have some experience :) /MikhailArticle: 107747
"Tommy Thorn" <tommy.thorn@gmail.com> wrote in message news:1157062043.825946.184620@m73g2000cwd.googlegroups.com... >> >> Is it possible to revert to a Webpack license once the full 60 day >> >> evaluation license has expired on ISE? If so how is it best done? >> >> There's >> >> nothing obvious in ISE so is it a question of re-installing to get the >> >> licensing screen back to allow the Webpack code to be inserted? >> > >> > Yes (AFAIK, this will require a reinstallation). Be sure to note that >> > WebPACK supports only a subset of the features of the full ISE. If you >> > need fx. to program Virtex 5 devices, then WebPACK won't do you any >> > good. > > Just to make sure there's no misunderstanding: There's no difference > (AFAIK) between installing WebPACK on a brand new computer and > installing it on a box that used to have an eval version of ISE, but > which have now been uninstalled. > > I'm not sure what happens if you try to install WebPACK while the ISE > eval version remains installed, but I wouldn't recommend it. > > As a cautious example: I botched up an install of Altera's Nios II > (deleted some files accidentally) and now I can neither uninstall nor > reinstall it. It hangs during the installation. Sigh. > > Tommy > Thanks, I'll uninstall the eval version first. Rog.Article: 107748
We have the same problems and have traced it to the IOB not latching valid read data back, from the working DDR memory IC, in the rise and fall registers. We can see the read data enter the Xilinx part correctly and never exit the capture registers. All clocks and resets, tap calibration, etc look great. We believe the read data is not getting through the Idelay block so it never gets captured and Comp_Done fails. My partner wants to switch to an Altera chip after he stops screaming ... BobArticle: 107749
martin griffith wrote: > On 31 Aug 2006 09:49:04 -0700, in sci.electronics.design > fpga_toys@yahoo.com wrote: > >> Joerg wrote: >>> Know what? What really bad typos indicate? Pretty clear, if someone >>> affords his or her resume that little attention to detail I assume it'll >>> be the same for a design. Can't use that. >> Or the person is dyslexic with a foriegn native tounge, language >> impaired, but with experience and genuis in design that can easily be >> offset by using good clerical assistant to help the designer with >> writing, editing, and other written language issues. > > hehe, I walked into the local language school, here in spain, having > problems translating my CV. The average tranlator cannot comprehend > technical terms like "Video Post Production facility engineer" You need to pre-translate first. What in English is "The Paris Conservatory Concert Society Orchestra" is in French, the literal translation of "The Orchestra of the Society of Concert of the Conservatory of Paris". Spanish is similar. They probably could have translated "Engineer for facilitating video after production". Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ
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