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Hi, In the Xilinx databook 1999 it is stated that carry logic in the Virtex can be used to cascade function generators for implementing wide logic functions (3-8). When looking at the detailed view of the Virtex Slice (3-9), it does not become clear to me how this works. Does anyone know how a wide logic function can be implemented on a low level (JBits) using the dedicated carry path in Virtex ? Thanks, Johan Ditmar Ericsson Telecom SwedenArticle: 17526
This is a multi-part message in MIME format. --------------140A91CDFEE0C0110D0E083B Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit By the way, I have already another serial-bit multiplier realizations in my designs: 3 serial-bit multiplier 24x8 bit . The accumulators and registers I use, are generated with logiblox (area optimized). Now I have also wrote the same components in VHDL and have got 4% (56% instead of 60% with logiblox) less CLB (XILINX 4020E) ! I use exact the same multiplication algorithm! Any comments will be appreciated. P.S. I will also realize this multiplier with your (Mr. Andraka) algorithm with LogiCore of scaled accumulator. And than I will write the short summary here (about timing and area with LogibloX, logicore and VHDL ). Ray Andraka wrote: > Look at the multiplier page on my website (under the DSP page). The first > multiplier discussed is a scaling accumulator multiplier. There is a drawing > with it. That example is unsigned. To make it signed, you need to subtract > the partial product corresponding to the MSB of the serial input instead of > adding it. You'll see that you really don't need the logicore piece, as all > it is is an accumulator (registered adder with output fed back to one input) > with the feedback path shifted by a bit. > > Ilia Oussorov wrote: > > > Hello, > > Does somebody know, how one can build serial multiplier with LogiCore > > scaled by 1/2 acc. > > Xilinx writes, that this module is typical for bit serial multiplier but > > > > I miss something as write_enable or shift input for the accumulator > > register (to add only if current factor bit ='1' or to only shift and > > not add if current factor bit ='0' ). > > > > Any usefull comments will be appreciated. > > > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka --------------140A91CDFEE0C0110D0E083B Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Ilia Oussorov Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Ilia Oussorov n: Oussorov;Ilia org: Robert Bosch GmbH, FV/FLI adr: P.O.Box 10 60 50;;;Stuttgart;;D-70049;Germany email;internet: fliser6@fli.sh.bosch.de tel;work: +49-(0)-711-8117057 tel;fax: +49-(0)-711-8117602 x-mozilla-cpt: ;0 x-mozilla-html: TRUE version: 2.1 end: vcard --------------140A91CDFEE0C0110D0E083B--Article: 17527
Hi, I am just now beginning a design with several FPGAs. At this point I am trying to pick the most suitable FPGA for the 3.3V, 50MHz design. 1) What technical criteria should I use in selecting between various FPGA vendors i.e. logic, gates? 2) Which FPGA is the determined "fastest" one available on the market in the 3.3V technology? 3) Does anyone have any preferences for a particular FPGA? 4) What are the advantages/disadvantages of Xilinx FPGAs? 5) What are the advantages/disadvantages of Lucent FPGAs? Thank you, -Regena Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17528
The synthesizer is probably optimizing the VHDL design more. The logiblox macros are treated as block boxes, so there is no opportunity to combine logic. Synplicity (and I'm sure the others do too) usually does at least as good as logiblox when it recognizes the need for a carry chain in the logic. It sometimes doesn't do so well if there is combinatorial logic in front of the adder, especially if the logic is different for different bits (for example a counter that has segments loaded by different signals). For a scaling accumulator, it does just fine. 60% of a 4020 seems pretty big for 3 serial by parallel multipliers. The multiplier should consist of a 32 bit (24bits + 8 bits) accumulator (registered adder) with AND gates on one set of inputs. The accumulator has to be fitted with a clear or load input as well, so each bit has 5 inputs. (clear/load, Q<<1, ser-in, par-in, carry). Additionally, if the serial input is signed, you need a conditional inversion of the parallel input, for a total of 6 inputs. You should be able to do that in 32 CLBs (16 rows by 2 columns), which is only 4% of an XC4020. If you need only the upper product, it can be made even smaller by allowing the lsb to shift off on each cycle. BTW, The scaling accumulator is not *my* algorithm; I just spread the information :-) Ilia Oussorov wrote: > By the way, > > I have already another serial-bit multiplier realizations in my designs: > 3 serial-bit multiplier 24x8 bit . > > The accumulators and registers I use, are generated with logiblox (area > optimized). > Now I have also wrote the same components in VHDL and have got 4% (56% > instead of 60% with logiblox) less CLB (XILINX 4020E) ! > I use exact the same multiplication algorithm! > > Any comments will be appreciated. > > P.S. I will also realize this multiplier with your (Mr. Andraka) algorithm with > LogiCore of scaled accumulator. > And than I will write the short summary here (about timing and area with > LogibloX, logicore and VHDL ). > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17529
What is your application? What is your intended design flow? These are important factors in selecting the "best" or even the "fastest" FPGA. That said, any of the current FPGAs are quite capable of 50 MHz designs, even the slowest speed grade Xilinx Spartan parts. For architectural criteria, you want to make sure your design maps comfortably onto the FPGA architecture. If you have arithmetic functions, you want to look at the carry chain structure (for example Altera 10K forces the design to two levels of logic for arithmetic functions with more than two inputs like an accumulator with clear). If you need delays or small memories, you'll want to look for CLB RAM capability. If you have a need for larger tables, you'll want an FPGA with block memories. For lots of "random logic", you want a device that isn't as sensitive to placement (altera's routing structure makes placement considerably less of an issue than xilinx). Also, you'll want to look at the I/O cell structure to see if the structure in the device will meet your timing. If you have lots of bidirectional pins that you want registered (advisable), then Altera may not be a good choice since it only has one register per IOB. Design flow also is a consideration, since the degree of control over the design implementation and placement can markedly influence the result. Altera is more synthesis friendly than xilinx, especially xilinx 4k, mostly because it is less sensitive to placement. For lots of "random logic", I'd probably select altera over xilinx, but for something that is heavily arithmetic, requires registered bidirectional I/O, or has many delay queues or small memories, I'd pick xilinx. I haven't really used Lucent parts, so I can't comment too much there. The Lucent architecture is closer to the xilinx 4K architecture. With careful design, you probably don't need to be in the "fastest" 3.3v part. Any of the 3.3v parts are capable of a 50 MHz design. I've got Xilinx 40xxXLA-07 designs running at around 150 MHz doing 12-14 bit arithmetic, and spartanXL-4 designs well over 100 MHz. raderrl@my-deja.com wrote: > Hi, I am just now beginning a design with several > FPGAs. At this point I am trying to pick the most > suitable FPGA for the 3.3V, 50MHz design. > > 1) What technical criteria should I use in > selecting between various FPGA vendors i.e. > logic, gates? > > 2) Which FPGA is the determined "fastest" one > available on the market in the 3.3V technology? > > 3) Does anyone have any preferences for a > particular FPGA? > > 4) What are the advantages/disadvantages of Xilinx > FPGAs? > > 5) What are the advantages/disadvantages of Lucent > FPGAs? > > Thank you, > -Regena > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17530
The carry can be viewed as a wide AND gate. Since it follows the LUT in Virtex, you end up with one layer of 4 input logic feeding an AND gate that is as wide as the number of bits in the carry chain. Johan Ditmar wrote: > In the Xilinx databook 1999 it is stated that carry logic in the Virtex > can be used to cascade function generators for implementing wide logic > functions (3-8). When looking at the detailed view of the Virtex Slice > (3-9), it does not become clear to me how this works. Does anyone know > how a wide logic function can be implemented on a low level (JBits) > using the dedicated carry path in Virtex ? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17531
Hi, I have a Problem with a XILINX 4010E. I have written a source code in VHDL, synthesized it with LEONARDO, placed and routed with ALLIANCE and then tried to implement this on a XILINX 4010E (download with XCHECKER cable ). After all these steps, I simulated the design with MODELSIM, and up to the placed design it all works fine, but the implementation on XILINX makes troubles. e.g. I have a shiftregister in my design, all control-logic-signals (clk, enable) are ok, the timing of the signals is ok, the input data are ok, but the final content of the register is not, what it should be. an other example is a "memory", when a learn-signal is high, there is a register where a given input-data should be written into: the learn signal and the input data are ok, what is stored in the registers afterwards is completely different from the original input-data The whole design is synchronous and the clk works at about 1 MHz (seems not too high). has anyone some idea, what could be the reason for this strange behaviour ? THANX, Sandra Dominikus.Article: 17532
Ray Andraka wrote: > The carry can be viewed as a wide AND gate. Since it follows the LUT in > Virtex, you end up with one layer of 4 input logic feeding an AND gate that > is as wide as the number of bits in the carry chain. > And, courtesy of Mr DeMorgan, it can also be a very wide NOR gate. Peter AlfkeArticle: 17533
In article <37AB0D62.A9945A29@xilinx.com>, Peter Alfke <peter.alfke@xilinx.com> wrote: > > >Ray Andraka wrote: > >> The carry can be viewed as a wide AND gate. Since it follows the LUT in >> Virtex, you end up with one layer of 4 input logic feeding an AND gate that >> is as wide as the number of bits in the carry chain. >> > >And, courtesy of Mr DeMorgan, it can also be a very wide NOR gate. > The carry mux can also be used as a wide OR gate as well, which of course gives you a NAND gate. To create a wide-AND the first MUXCY has a 1 attached to the CI (carry in) pin and a 0 attached to the DI (direct in) pin. All subsequent MUXCY cells have the CI pin feed from the previous MUXCY output and a 0 attached to the DI pin . To create a wide-OR the first MUXCY has a 0 attached to the CI (carry in) pin and a 1 attached to the DI (direct in) pin. All subsequent MUXCY cells have the CI pin feed from the previous MUXCY output and a 1 attached to the DI pin. The output function of the MUXCY is O = (S and CI) or (not S and DI). The S in both cases is sourced from the 4-input LUT associated with the MUXCY cell. Ed McGettigan PS: I have parameterized 64-bit address decoder examples in VHDL and Verilog if anyone is interested.Article: 17534
Nicolas Matringe wrote in message <379EE65C.D4D21308@dot.com.fr>...
>Hi
>
>I tried to put a "hardwired" version number in a design but it is
>impossible to read.
>The simulation runs OK (and the number is readable), but the FPGA won't.
>The returned value is always zero.
>Is my code OK, therefore indicating that Max+plus is nothing but junk,
>or is my code wrong (but then, why would the simulation work?)
>Or maybe the Flex 10k doesn't support such fixed values?
I used the following for a 10k design, with maxplus2, it worked. On the
other hand, I tend to code very defensively with FPGA synthesizers. I
create a
lot of intermediate signals that I can look at. QA seems pretty LAX for
FPGA synthesis (I am used to ASIC synthesis where it is a serious
matter to synthesize wrong).
So, my advice is to bring some signals out of the chip and look at them
in simulation.
I use maxplus2 as a fallback from Synplify. Altera catches some things
that go through Synplify. I consider maxplus2 to be pretty accurate
in the result. My complaint with Altera synthesis is that it is behind
others in following syntax correctly and progressing to VHDL '93.
--Rob Anderson
-- ********* TMB DATA BUS: *************
-- tmb is only driven when sysclk='0'
tmb<=tmb_d when ((rd_regs='1') and (sysclk='0')) else (others=>'Z');
process (dqq,sreg_en,sreg,sd_addr,sd_ovr)
begin
if (sreg_en='0') then tmb_d<=dqq;
elsif (sreg_en='1') then
tmb_d<= (others=>'0');
tmb_d(127 downto 112)<= tb_version;
tmb_d(57 downto 32)<=sd_addr;
tmb_d(58)<=sd_ovr;
tmb_d(7 downto 0)<=sreg;
end if;
Article: 17535Hi all, Iam implementing a Adaptive Filter (Widrow-Hoff LMS) on a Xilinx 4000 FPGA chip for my Masters' thesis. I would like to know how to observe the outputs from the chip. Any info is welcome. Thanks, Gopal.Article: 17536
Access to a leading cancer detection technology is being threatened because of an intellectual property dispute and there is a new website, www.factsaboutolympus.com, which tells you why. This threat arises from a legal dispute concerning trade secrets between two companies, which has the potential to put a halt to important research in the area of early detection of lung cancer and gastrointestinal cancer. And, there’s something you can do about it. Please visit www.factsaboutolympus.com. If you have a website, I would urge you to provide a link to the page. Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17537
R. Mehler <rmehler@dropzone.tamu.edu> wrote:
>Shardendu Pandey (pandey@my-deja.com) wrote:
>> I am trying to compare a data stream to check if its
>> xxxx so I say
>>
>> if (data==16'hxxxx)
>>
>> compiler warns me saying this is redundant comparison
>> which leaves me stranded as to how I look for xxxx
>> condition which leaves me grounded
>
>Comparison to any x or z cases requires use of the
>case equality operator, ===.
>
>Note that this construct is not supported for synthesis.
Tell me exactly how you'd made hardware to test for the 'xxxx'
condition, and I make sure this info makes it to those who
make and sell synthesis tools. :^)
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
============================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 6000+ other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
Article: 17538You want to use the case equality operator, if(data === 16'hxxxx) Josh > R. Mehler <rmehler@dropzone.tamu.edu> wrote: > >Shardendu Pandey (pandey@my-deja.com) wrote: > >> I am trying to compare a data stream to check if its > >> xxxx so I say > >> > >> if (data==16'hxxxx) > >> > >> compiler warns me saying this is redundant comparison > >> which leaves me stranded as to how I look for xxxx > >> condition which leaves me grounded > > > >Comparison to any x or z cases requires use of the > >case equality operator, ===. > > > >Note that this construct is not supported for synthesis.Article: 17539
Registration is Open and Program - 1999 MAPLD International Conference
September 28-30, 1999
Kossiakoff Conference Center
The Johns Hopkins University- Applied Physics Laboratory
Laurel, Maryland
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/MAPLDCon99.html
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Registration.html
The 2nd annual Military and Aerospace Applications of Programmable
Devices and Technologies International Conference will address
devices, technologies, usage, reliability, fault tolerance,
radiation susceptibility, and applications of programmable devices
and adaptive computing systems in military and aerospace systems.
The program will consist of approximately 60 oral and poster technical
presentations and close to 20 industrial exhibits. This international
conference is open to US and foreign participation and is unclassified.
There will be one classified session at the secret level, for U.S.
citizens only. For additional conference information, please see the
Programmable Technologies Web Site (http://rk.gsfc.nasa.gov).
------------------------------------------------------------------
MAPLD 99 Program
Military and Aerospace Applications of Programmable Devices and
Technologies International Conference
Welcome
Rich Katz - NASA Goddard Space Flight Center
Dr. Stamatios Krimigis - Head, Space Department
Johns Hopkins University/Applied Physics Lab
Technical Sessions:
A. Military & Aerospace Applications
Session Chair: Marty Fraeman - JHU/APL
Invited Speaker: Dr. Ralph McNutt - JHU/APL
"Space Exploration Beyond 2020"
B. Devices, Elements, and Technologies
Session Chair: Rich Katz - NASA Goddard Space Flight Center
Invited Speaker: John McCollum - Actel Corp.
"Programmable Elements and Their Impact on FPGA Architecture,
Performance and Radiation Hardness"
C. Radiation Environments and Effects
Session Chair: Ken LaBel - NASA Goddard Space Flight Center
Invited Speaker: Rich Katz - NASA GSFC
"FPGAs in Space Environment and Design Techniques"
D. SoC, Synthesis, and IP
Session Chair: Hans Tiggeler - University of Surrey, UK
Invited Speaker: Sandi Habinc - ESA
"Designing Space Applications Using Synthesizable Cores"
E. Adaptive Computing
Session Chair: John McHenry - National Security Agency
Invited Speaker: Brad Hutchings - Brigham Young University
"Configurable Computing: Past, Present, and Future"
F. Classified Session
Session Chair: Al Hunsberger - National Security Agency
Invited Speaker: Mark Dunham - DOE/Los Alamos National Labs
Gigasample Image and Signal Processing via Reconfigurable
Computing
P. Poster Session
Session Chair: Christina Gorsky - SGT, Inc.
Dinner Speaker (Tuesday Evening)
Dr. Don DeVoe, University of Maryland at College Park
"Micro Electro Mechanical Systems (MEMS)"
Panel Session: (Wednesday Evening)
"Architecture, Technologies and Design Methodologies for 2005
and Beyond"
Panel Moderator: Ann Garrison Darrin - JHU/APL
---------------------------------------------------
Technical Committee
===================
Ray Andraka - The Andraka Group
Neil Bergmann - Queensland University of Tech, Australia
Ben Cohen - Hughes Aircraft/Raytheon
Lew Cohn - Defense Threat Reduction Agency
Marco Figueiredo - SGT, Inc.
Marty Fraeman - JHU/Applied Physics Lab
Ann Garrison Darrin - JHU/Applied Physics Lab
Creigh Gordon - Air Force Research Lab/VSSE
Christina Gorsky - SGT, Inc.
Al Hunsberger - National Security Agency
Brad Hutchings - Brigham Young University
Richard B. Katz - NASA GSFC
Ralph Kohler - Air Force Research Laboratory
Ken LaBel - NASA GSFC
John McHenry - National Security Agency
Robert Reed - NASA GSFC
Michael Regula - Dornier Satellitensysteme GmbH
Frank R. Stott - Jet Propulsion Laboratory
Hans Tiggeler - University of Surrey, UK
Tanya Vladimirova - University of Surrey, UK
The conference is sponsored by:
- NASA Goddard Space Flight Center
- JHU/Applied Physics Laboratory
- National Security Agency
- NASA Radiation Effects Program
- Military & Aerospace Programmable Logic Users Group
- American Institute of Aeronautics and Astronautics
Late news poster papers will be accepted on a first-come, first-served,
space-available basis. Abstracts should be approximately 2 pages long
and should be sent to maplug@pop700.gsfc.nasa.gov. Include first author
information (name, affiliation, phone number, and email address) and
whether an open or classified presentation is desired. If you can not
submit an unclassified abstract, please contact Al Hunsberger.
Industrial exhibit reservations will be accepted on a first-come,
first-served, space-available basis. Requests should be sent to
maplug@pop700.gsfc.nasa.gov and should include company name and
contact information (name, phone and email).
For more information see http://rk.gsfc.nasa.gov or contact:
Richard Katz
NASA
rich.katz@gsfc.nasa.gov
Tel: (301) 286-9705
Alan W. Hunsberger
NSA
awhunsb@afterlife.ncsc.mil
Tel: (301) 688-0245
Ann Garrison Darrin
JHU/APL
ann.darrin@jhuapl.edu
Tel: (240) 228-4952
Article: 17540The Portland, Oregon office of Oxford & Associates is helping local clients find ASICs designers for contract and direct positions. Most positions require at least 2 years' industry experience, and all work must be done at the clients' local sites. The most immediate needs are for designers who have on-the-job experience with cache coherency protocols, and for expert FPGA designers. If you are interested, or know anyone who is interested, in positions in the Pacific Northwest, please get in touch. Margaret Dailey Recruiter 503-291-5250 margaret_dailey@oxfordcorp.comArticle: 17541
We want to integrate Xilinx tools and their directory systems into ClearCase environment. What do you recommend? Is there any site which gives information about this issue? UtkuArticle: 17542
John Cooley wrote:
> >> I am trying to compare a data stream to check if its
> >> xxxx so I say
> >>
> >> if (data==16'hxxxx)
> >>
> >> compiler warns me saying this is redundant comparison
> >> which leaves me stranded as to how I look for xxxx
> >> condition which leaves me grounded
>
> Tell me exactly how you'd made hardware to test for the 'xxxx'
> condition, and I make sure this info makes it to those who
> make and sell synthesis tools. :^)
>
> - John Cooley
At first I was a bit surprised to see this name in a _VHDL_ group ;-) But
this seems to be the magic of crossposting.
Secondly , in Verilog the construct should be '===' (3 of them). In VHDL , you
could do with a "=".
At last , it is true that this construct doesn't make sense for synthesis. But
it could make a lot of sense in a good testbench development. And testbench code
is at least as important as code to be synthesized.
Kind regards,
Jos De Laender
>
> Part Time EDA Consumer Advocate
> Full Time ASIC, FPGA & EDA Design Consultant
>
> ============================================================================
> Trapped trying to figure out a Synopsys bug? Want to hear how 6000+ other
> users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
>
> !!! "It's not a BUG, jcooley@world.std.com
> /o o\ / it's a FEATURE!" (508) 429-4357
> ( > )
> \ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
> _] [_ Verilog, VHDL and numerous Design Methodologies.
>
> Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
> Legal Disclaimer: "As always, anything said here is only opinion."
> The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
Article: 17543This is a multi-part message in MIME format. --------------C99F04A8DDB7B765B9685F8A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit The whole designe take 60% of FPGA (not multipiers only) The multipliers are a part of it. Ray Andraka wrote: > 60% of a 4020 seems pretty big for 3 serial by parallel multipliers. The > multiplier should consist of a 32 bit (24bits + 8 bits) accumulator (registered > adder) with AND gates on one set of inputs. The accumulator has to be fitted with > a clear or load input as well, so each bit has 5 inputs. (clear/load, Q<<1, > ser-in, par-in, carry). Additionally, if the serial input is signed, you need a > conditional inversion of the parallel input, for a total of 6 inputs. You should > be able to do that in 32 CLBs (16 rows by 2 columns), which is only 4% of an > XC4020. If you need only the upper product, it can be made even smaller by > allowing the lsb to shift off on each cycle. > --------------C99F04A8DDB7B765B9685F8A Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Ilia Oussorov Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Ilia Oussorov n: Oussorov;Ilia org: Robert Bosch GmbH, FV/FLI adr: P.O.Box 10 60 50;;;Stuttgart;;D-70049;Germany email;internet: fliser6@fli.sh.bosch.de tel;work: +49-(0)-711-8117057 tel;fax: +49-(0)-711-8117602 x-mozilla-cpt: ;0 x-mozilla-html: TRUE version: 2.1 end: vcard --------------C99F04A8DDB7B765B9685F8A--Article: 17544
Alex Makris wrote: > The NT environment is undoubtly more user friendly and has a ten times > better and more efficiently > designed desktop. Which desktop environment/window manager are you using for Unix? Modern desktop environments offer the same or better flexibility like NT. Some features are not available with NT like magic codes. If you are using NT you can only link files to programs via extensions. Drag and drop an NT linked file, then your program will open the *.lnk file and not the link destination. Bye Tom!Article: 17545
Has anyone succeeded in passing more than 8 bits in a parameter to a
function using Max+ verilog input (i.e. Altera Synthesis) ?
If so, I'd be very interested to hear how you did it.
Perhaps someone could comment on my reading of the LRM's definition of
an 'implementation dependent' limit in this case, and whether 8 bits is
a sensible limit, or wanting 32 bit parameters is being unreasonable...
// Here's a test case
// You should see that the USE_PARAMETER8 and NO_PARAMETER cases will
// compile but the reset value will either be 12345621 or 12345678
// respectively, not 87654321 as desired.
//
// ==========
// Important:
// ==========
// Make sure you comment in one (and only one) of the following...
// `define USE_PARAMETER32
// `define USE_PARAMETER8
`define NO_PARAMETER
module testcase( i, o, clk, reset_l );
input clk;
input reset_l;
input[ 31:0 ] i;
output[ 31:0 ] o;
`ifdef USE_PARAMETER32
sub instance1 ( .i( i ), .o( o ), .clk( clk ), .reset_l( reset_l ) );
defparam instance1.resetvalue = 32'h87654321;
`endif
`ifdef USE_PARAMETER8
sub instance1 ( .i( i ), .o( o ), .clk( clk ), .reset_l( reset_l ) );
defparam instance1.resetvalue = 8'h21;
`endif
`ifdef NO_PARAMETER
sub instance1 ( .i( i ), .o( o ), .clk( clk ), .reset_l( reset_l ) );
`endif
endmodule
module sub( i, o, clk, reset_l );
`ifdef USE_PARAMETER32
parameter resetvalue = 32'h12345678;
`endif
`ifdef USE_PARAMETER8
parameter resetvalue = 8'h78;
`endif
input clk, reset_l;
input[ 31:0 ] i;
output[ 31:0 ] o;
reg[ 31:0 ] o; // simple clocked reg implicitly connected to o;
always @( posedge clk or negedge reset_l ) begin
if( ~reset_l )
`ifdef USE_PARAMETER32
o <= resetvalue; // use resetvalue parameter to define reset
condition
`endif
`ifdef USE_PARAMETER8
o <= { 24'h123456, resetvalue }; // kludge resetvalue
parameter to define reset condition
`endif
`ifdef NO_PARAMETER
o <= 32'h12345678;
`endif
else
o <= i;
end
endmodule
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Article: 17546Unfortunately, the M1 software (all versions) and I suspect M2.1i also, ignore the suffix of .FFX, .FFY, .F, and .G . You can direct a FMAP and a flipflop to a given CLB, but you cant control exactly where. There are also problems if you try to run 3 signals into the H-Lut, that all are sourced from outside the CLB, when you are using F and/or G for something else. The XL, XLA parts support it but the software does not. The only workaround I know is to go into the chip editor after P&R. Not a realistic workaround. The occasions when you see the .FFX and .FFY being obeyed is just luck. Another similar problem with RLOCs is that RLOCs in different hsets (i.e. in different hierarchys with RLOC_ORIGIN at the top of each) that both place logic into a CLB will fail, even though there is room in the CLB for the logic from the two hsets. In article <37A8250D.AF756037@rr.iij4u.or.jp>, <takehiro@rr.iij4u.or.jp> wrote: >Dear all, > >I try to place and route my design on XC4013XL with UCF constraint file >which includes RLOC=R0C0.FFX constraint description. >But the some RLOC constraints(not all!) may be ignored because the >instance attached the RLOC constraint is mapped on Y position of >flipflop in a CLB(same as FFY). >I have no error or warning messages about that UCF description during >translate and map process. >Is there some case that MAP ignores user specified RLOC property? >Please anyone give me advice. > >note : I use foundation M1.5. > >Thanks, > >hiro > >Article: 17547
I find that rloc=rxcy.ffx only works on fdce flops and that is all. This works for me. INST "PCI_CORE/BUSA/LOWCNT/Q0/$1I35" LOC = "CLB_R1C8.FFX" ; but only on fdce parts. If this works for you please post on comp.arch.fpga takehiro@rr.iij4u.or.jp wrote: > Dear all, > > I try to place and route my design on XC4013XL with UCF constraint file > which includes RLOC=R0C0.FFX constraint description. > But the some RLOC constraints(not all!) may be ignored because the > instance attached the RLOC constraint is mapped on Y position of > flipflop in a CLB(same as FFY). > I have no error or warning messages about that UCF description during > translate and map process. > Is there some case that MAP ignores user specified RLOC property? > Please anyone give me advice. > > note : I use foundation M1.5. > > Thanks, > > hiro -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 17548
Gopal Iyer wrote in message ... >Hi all, > Iam implementing a Adaptive Filter (Widrow-Hoff LMS) on a Xilinx 4000 >FPGA chip for my Masters' thesis. I would like to know how to observe the > outputs from the chip. Any info is welcome. You mean you want to observe the filter outputs? run the filter output nets to an OPAD. -- ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao.edu "You want partial credit? You build bridge, bridge falls down - no partial credit." -- Dr A. Chang, professor of Mechanical Engineering at Stevens Institute of TechnologyArticle: 17549
I am trying to program a Lattice ispLSI2032 part with a homemade cable. Using AN8003.pdf for connections between the '244 and the parallel port and the 2032 datasheet for pin connections on the chip, I constructed a circuit which is identical to one of the circuits found in the newsgroups and on the web, but differs from 3 other circuits I found later. Since the circuit doesn't work, I was wondering if anyone has a circuit KNOWN to work with the 2032... ???
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