Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 119150

Article: 119150
Subject: Digital gain and offset correction
From: "Marco T." <marcotoschi@gmail.com>
Date: 13 May 2007 23:31:47 -0700
Links: << >>  << T >>  << A >>
Hallo,
which is the way to perform digital vgain and offset correction using
a fpga?

Thanks,
Marco T.


Article: 119151
Subject: How to Ask a Question
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Sun, 13 May 2007 23:49:14 -0700
Links: << >>  << T >>  << A >>
Hi - 

In light of a recent flameboree in these parts, I thought it might be
helpful to provide a link to an article entitled, "How to Ask a
Question the Smart Way."  Although aimed at programmers and programmer
wannabes, the advice is equally applicable to hardware designers old
and new.

http://www.catb.org/~esr/faqs/smart-questions.html

The article's been translated into two dozen languages; look for the
links under the "Translations" header.

Bob Perlman
Cambrian Design Works
http://www.cambriandesign.com

Article: 119152
Subject: Re: Digital gain and offset correction
From: Antti <Antti.Lukats@xilant.com>
Date: 14 May 2007 00:48:44 -0700
Links: << >>  << T >>  << A >>
On 14 Mai, 08:31, "Marco T." <marcotos...@gmail.com> wrote:
> Hallo,
> which is the way to perform digital vgain and offset correction using
> a fpga?
>
> Thanks,
> Marco T.

the answer is the same as for the last time you posted this very same
question.

you can do it any way you like as long as it does what you need.

Antti



Article: 119153
Subject: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;)
From: Antti <Antti.Lukats@xilant.com>
Date: 14 May 2007 02:14:45 -0700
Links: << >>  << T >>  << A >>
As subject: all system are go and green on the Spartan-3A Starterkit
board.
No issues. Just working :)

Antti Lukats
PS demo download also available now from our site.


Article: 119154
Subject: Camera Control
From: "MJ Pearson" <mjp500@york.ac.uk>
Date: Mon, 14 May 2007 03:39:13 -0700
Links: << >>  << T >>  << A >>
Hello, I have a xupv2p board and I am wanting to use this board to perform image processing from 2 camera-link based cameras. I am building a connection board that will connect the cameras to the board and perform the de-serialization of the signals.

My question is about the control of the cameras. I am currently using a PC and frame-grabber, for which I have an API, dll files etc for camera control. Can these used by the power PC unit or Microblaze? ANY help would be gratefully recieved. Many thanks, Marc.

Article: 119155
Subject: Re: Xilinx software quality - how low can it go ?!
From: Antti <Antti.Lukats@xilant.com>
Date: 14 May 2007 03:46:27 -0700
Links: << >>  << T >>  << A >>
On 11 Mai, 20:50, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de>
wrote:
> Bob <bob36...@yahoo.com> wrote:
>
> ...
>
> > I think a better choice would be to open source iMPACT.  I doubt if
> > it contains any strategic IP.  There are six computers in the office
> > suite where I work, including Win-XP, Linux, and FreeBSD on x86_64;
> > and Win-XP and Linux on x86_32.  ISE runs fine on all of them. iMPACT
> > runs on precisely one (Win-XP on x86_32).  It fails on all the others
> > for various reasons.  It also fails to work on VMware.  These sorts
> > of driver and OS compatibility issues are something the OSS community
> > is quite good at fixing.
>
> Look with google for
> "XILINX USB/Parallel JTAG cables on Linux without windrvr"
> for an open source replacement for the windriver nightmare.
>
> --
> Uwe Bonnes                b...@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Uwe

that support is limited to Cable III and Cable IV in Cable III
compatibility mode, right?

so for Cable IV in Cable IV high speed mode there is no solution
without
the Xilinx nigthmare :(

Antti







Article: 119156
Subject: Re: Xilinx LogiCore FFT 3.2
From: bijoy <pbijoy@rediffmail.com>
Date: Mon, 14 May 2007 04:07:13 -0700
Links: << >>  << T >>  << A >>
Hi william, there is a exponent part, did you take that into account ??

rgds bijoy

Article: 119157
Subject: Re: Xilinx software quality - how low can it go ?!
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Mon, 14 May 2007 11:14:12 +0000 (UTC)
Links: << >>  << T >>  << A >>
Antti <Antti.Lukats@xilant.com> wrote:
...

> Uwe

> that support is limited to Cable III and Cable IV in Cable III
> compatibility mode, right?

> so for Cable IV in Cable IV high speed mode there is no solution
> without
> the Xilinx nigthmare :(

Sorry,

didn't read the "IV".

But is the added speed by the IV cable worth the hassle?

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 119158
Subject: Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;)
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Mon, 14 May 2007 11:15:18 +0000 (UTC)
Links: << >>  << T >>  << A >>
Antti <Antti.Lukats@xilant.com> wrote:
> As subject: all system are go and green on the Spartan-3A Starterkit
> board.
> No issues. Just working :)

> Antti Lukats
> PS demo download also available now from our site.

Links are welcome

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 119159
Subject: Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;)
From: Antti <Antti.Lukats@xilant.com>
Date: 14 May 2007 04:22:18 -0700
Links: << >>  << T >>  << A >>
On 14 Mai, 13:15, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de>
wrote:
> Antti <Antti.Luk...@xilant.com> wrote:
> > As subject: all system are go and green on the Spartan-3A Starterkit
> > board.
> > No issues. Just working :)
> > Antti Lukats
> > PS demo download also available now from our site.
>
> Links are welcome
>
> --
> Uwe Bonnes                b...@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
here you go:
http://www.xilant.com/index.php?option=com_remository&Itemid=36&func=select&id=1
Antti





Article: 119160
Subject: Re: Xilinx software quality - how low can it go ?!
From: Antti <Antti.Lukats@xilant.com>
Date: 14 May 2007 04:28:50 -0700
Links: << >>  << T >>  << A >>
On 14 Mai, 13:14, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de>
wrote:
> Antti <Antti.Luk...@xilant.com> wrote:
>
> ...
>
> > Uwe
> > that support is limited to Cable III and Cable IV in Cable III
> > compatibility mode, right?
> > so for Cable IV in Cable IV high speed mode there is no solution
> > without
> > the Xilinx nigthmare :(
>
> Sorry,
>
> didn't read the "IV".
>
> But is the added speed by the IV cable worth the hassle?
>

I think it is.
cable IV is nice piece of hardware when it works in high speed mode
- but this is very seldom, on most PC's xilinx-software-drivers fall
back into Cable III mode without explanation.

every other LPT connected software can use the LPT ports to the
maximum, its just the crappy Xilinx drivers that can not handle it
properly.

Antti











Article: 119161
Subject: Re: Digital gain and offset correction
From: "Marco T." <marcotoschi@gmail.com>
Date: 14 May 2007 04:58:02 -0700
Links: << >>  << T >>  << A >>

Antti ha scritto:

> On 14 Mai, 08:31, "Marco T." <marcotos...@gmail.com> wrote:
> > Hallo,
> > which is the way to perform digital vgain and offset correction using
> > a fpga?
> >
> > Thanks,
> > Marco T.
>
> the answer is the same as for the last time you posted this very same
> question.
>
> you can do it any way you like as long as it does what you need.
>
> Antti


Ok, but I never did it, so I asked to know if there is a prefered way.

I made made searches with google, but I didn't found relevant
informations.


In example: I have a sensor with wheatstone bridge. I amplify the
signal by 100. I connect it to adc.
Then I could perform offset correction and also gain.

But my question was made to know which tecnique do you use.


Thanks,
Marco T.


Article: 119162
Subject: Re: Digital gain and offset correction
From: Antti <Antti.Lukats@xilant.com>
Date: 14 May 2007 05:10:13 -0700
Links: << >>  << T >>  << A >>
On 14 Mai, 13:58, "Marco T." <marcotos...@gmail.com> wrote:
> Antti ha scritto:
>
> > On 14 Mai, 08:31, "Marco T." <marcotos...@gmail.com> wrote:
> > > Hallo,
> > > which is the way to perform digital vgain and offset correction using
> > > a fpga?
>
> > > Thanks,
> > > Marco T.
>
> > the answer is the same as for the last time you posted this very same
> > question.
>
> > you can do it any way you like as long as it does what you need.
>
> > Antti
>
> Ok, but I never did it, so I asked to know if there is a prefered way.
>
> I made made searches with google, but I didn't found relevant
> informations.
>
> In example: I have a sensor with wheatstone bridge. I amplify the
> signal by 100. I connect it to adc.
> Then I could perform offset correction and also gain.
>
> But my question was made to know which tecnique do you use.
>
> Thanks,
> Marco T.

the answer remains the same. you can use any way you like as long as
it does what you need.

for bridge sensor it is WAY WAY WAY more preferable to use special
flash microcontroller that can directly connect to bridge sensor.
or you can use a sensor conditioner that has the correction already
built in.
or use generic microcontroller and write the correction in C like
this:

my_wanted_result = (actual_measued_value + xxx) * yyy;

or use EDK to build a SoC system in FPGA and write:

my_wanted_result = (actual_measued_value + xxx) * yyy;

or use NIOS and write:

my_wanted_result = (actual_measued_value + xxx) * yyy;

or

... there exactly 28 more possibilities todo the same thing.

stop asking and start doing!

Antti


Article: 119163
Subject: Re: Camera Control
From: Gabor <gabor@alacron.com>
Date: 14 May 2007 05:39:00 -0700
Links: << >>  << T >>  << A >>
On May 14, 6:39 am, "MJ Pearson" <mjp...@york.ac.uk> wrote:
> Hello, I have a xupv2p board and I am wanting to use this board to perform image processing from 2 camera-link based cameras. I am building a connection board that will connect the cameras to the board and perform the de-serialization of the signals.
>
> My question is about the control of the cameras. I am currently using a PC and frame-grabber, for which I have an API, dll files etc for camera control. Can these used by the power PC unit or Microblaze? ANY help would be gratefully recieved. Many thanks, Marc.


I think it's unlikely you can directly use your dll files, however
there is a Camera Link
document describing the function of the standard dll required by the
spec.  Most are
pretty simple (like serial communication with UART...) and easy enough
to reproduce
for your system.  Higher level code developed by the framegrabber
vendor may be
harder to reproduce depending on the level of documentation supplied,
however
a well-documented API is a much better starting point to develop your
own code
from than starting from scratch.

Good Luck,
Gabor


Article: 119164
Subject: Re: Xilinx Webpack 9.1i.03 Verilog synthesis bug?
From: gabor <gabor@alacron.com>
Date: 14 May 2007 05:59:19 -0700
Links: << >>  << T >>  << A >>
On May 13, 4:25 pm, "Xilinx user" <xilinx_u...@nowhere.net> wrote:
> For the combinational-logic of my state-machine, if I use an always @*,
> Xilinx XST erroneously optimizes/removes the logic, and then rips out
> any downstream load-logic.
>
> reg [6:0] s_instr_category;
>
> // The "BAD" state-machine
> always @* begin : state_machine  // <-- line #461
>   if ( a00 ) s_instr_category = A;
>   else if ( a01 ) s_instr_category = B;
>   else if ( a02 ) s_instr_category = C;
>   ...
>   else
>     s_instr_category = MY_DEFAULT;
> end // always @*
>
> always @ (posedge clk )
>   if ( s_instr_category == A )
>     decision_junk <= s;
>   else if (s_instr_category == B )
>     decision_junk <= s + 1;
>   ...
>
> WARNING:Xst:905 - "control_fsm.v" line 461: The signals <s_instr_category>
> are missing in the sensitivity list of always block.
> Module <control_fsm> is correct for synthesis.
>
> I've tried changing always @* -> always @ ( a00,a01,a02,...), but I always
> see the same WARNING in the logfile.
> I've worked around this problem by using the ?: operator.  For some reason,
> Xilinx XST is perfectly happy with the following-code (but not the code I
> posted top.)
>
> wire [6:0] s_instr_category;
>
> // The "BAD" state-machine
> assign s_instr_category =
>   (a00) ? A :
>   (a01) ? B :
>   (a02) ? C :
>    ...
>                  : MY_DEFAULT;
>
> ...
> Any ideas?  I'm using Webpack 9.1i with Service Pack 3 (and IP-update 2.1)
> Will this be fixed in Webpack 9.2?
> And using 2D-regs in an always @* block still doesn't work.
>
> reg [15:0] mem [0:255];
> wire [7:0] address;
>
> always @*
>   latch_dout = mem[ address ]; // <-- XST 9.1i.03 *ERROR*


I think this may be one of those misleading warnings.  I don't see why
s_instr_category should be in the sensitivity list since it's never on
the right hand side of an assignment.  On the other hand it looks
like a bug of some sort.  Were you able to use an assign statement
for latch_dout as well?


Article: 119165
Subject: Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;)
From: Zara <me_zara@dea.spamcon.org>
Date: Mon, 14 May 2007 15:10:59 +0200
Links: << >>  << T >>  << A >>
On 14 May 2007 04:22:18 -0700, Antti <Antti.Lukats@xilant.com> wrote:

>On 14 Mai, 13:15, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de>
>wrote:
>> Antti <Antti.Luk...@xilant.com> wrote:
>> > As subject: all system are go and green on the Spartan-3A Starterkit
>> > board.
>> > No issues. Just working :)
>> > Antti Lukats
>> > PS demo download also available now from our site.
>>
>> Links are welcome
>>
>> --
>> Uwe Bonnes                b...@elektron.ikp.physik.tu-darmstadt.de
>>
>> Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
>> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
>here you go:
>http://www.xilant.com/index.php?option=com_remository&Itemid=36&func=select&id=1
>Antti
>
>
>


Ah, Antti, you are a genius!
I was stuck with the way to receive the clk feedback from DDR to
connect to the corresponding opb_mch_ddr pins. I completely overlooked
the possibility of generating *2* clock pairs. I had even thought of
shorting clock output to LOOP_IN or LOOP_OUT!

NTW, why do you use the combination of DCM outputs + inverters instead
of directly using the 180/270 outputs? I thought  the secodn solution
should be better... but now I don' know

Best regards,

Zara

Article: 119166
Subject: Re: Xilinx software quality - how low can it go ?!
From: Didi <dp@tgi-sci.com>
Date: 14 May 2007 06:19:27 -0700
Links: << >>  << T >>  << A >>
> It's hard sometimes to understand why they think remaining in the
> stone age is better.

I doubt they think it and I doubt they do not know they could make
a lot more money by just making the programming data publically
available.

 Someone somewhere pretty high must be desperate to preserve the
limits of what can be done under control, hence these data are secret,
the computer industry is clogged by using an architecture times
less efficient that others, and (I know you'll disagree with that)
the mass software industry is clogged by C written code, times
less efficient than it can be.
 So I guess it is futile to try to convince CPLD/FPGA manufacturers
to open the data, chances are this is not their decision. (I expect
in amusement the vehement denials of that they may have).
 Which is no reason to stop asking, to be sure.

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

On May 6, 12:04 am, fpga_t...@yahoo.com wrote:
> On May 3, 8:25 am, Frank Buss <f...@frank-buss.de> wrote:
>
> > Would be a good idea to combine both designing tools (but using the GUI of
> > Quartus, because it's nicer than the ISE GUI) and open source it. In the
> > end this would lead to less development cost for all: the FPGA companies,
> > because they don't need to write both the same things and for users of the
> > program, because they can help bugfixing it and using a more stable
> > program. Company secrets could be moved to plugin modules.
>
> When their management learn the products can be supported better with
> the same number of people leading the project, and the developers
> learn they are not likely to lose their jobs, it should be an easier
> decision. Plus they get aditional volunteer labor for design, coding,
> AND TESTING that they can not afford now. Even large customers, which
> have significant internal development staff see less project risks
> when they can fix mission critical bugs on the fly, rather than have
> the whole project grind to a stop while pressing the vendor hard for a
> fix.
>
> Another benefit, is recruiting new hires can be taken from the
> volunteer developer pool as needed, and they are already several
> months ahead of the learning curve that it takes to get a new hire
> productive.
>
> It's hard sometimes to understand why they think remaining in the
> stone age is better.



Article: 119167
Subject: Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;)
From: Antti <Antti.Lukats@xilant.com>
Date: 14 May 2007 06:30:28 -0700
Links: << >>  << T >>  << A >>
On 14 Mai, 15:10, Zara <me_z...@dea.spamcon.org> wrote:
> On 14 May 2007 04:22:18 -0700, Antti <Antti.Luk...@xilant.com> wrote:
>
> >On 14 Mai, 13:15, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de>
> >wrote:
> >> Antti <Antti.Luk...@xilant.com> wrote:
> >> > As subject: all system are go and green on the Spartan-3A Starterkit
> >> > board.
> >> > No issues. Just working :)
> >> > Antti Lukats
> >> > PS demo download also available now from our site.
>
> >> Links are welcome
>
> >> --
> >> Uwe Bonnes                b...@elektron.ikp.physik.tu-darmstadt.de
>
> >> Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
> >> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
> >here you go:
> >http://www.xilant.com/index.php?option=com_remository&Itemid=36&func=...
> >Antti
>
> Ah, Antti, you are a genius!
> I was stuck with the way to receive the clk feedback from DDR to
> connect to the corresponding opb_mch_ddr pins. I completely overlooked
> the possibility of generating *2* clock pairs. I had even thought of
> shorting clock output to LOOP_IN or LOOP_OUT!
>
> NTW, why do you use the combination of DCM outputs + inverters instead
> of directly using the 180/270 outputs? I thought  the secodn solution
> should be better... but now I don' know
>
> Best regards,
>
> Zara- Zitierten Text ausblenden -
>
Hi Zara

actually this time its not me who genius. but generically I am too ;)

to your questions: the "two clock pairs" is used often in several
other designs as well.
and yes, until you see it done this way, you look for other more
harder ways :(

the DCM scheme, well there are different possibilities, the one that
is used
is minimizing the BUFG usage, if you are not running low on BUFG you
can
use the other scheme with more BUFG useage as well.

Antti


Article: 119168
Subject: Re: Digital gain and offset correction
From: Paul <pauljbennett@gmail.com>
Date: 14 May 2007 07:28:39 -0700
Links: << >>  << T >>  << A >>
Gain = multiplication   or  even simpler, right bitshift if you only
need scaling factors of powers of 2
Offset = addition

both operations are done very easily in an FPGA

If you're really asking how to perform multiplication and addition in
an fpga, then you should go purchase a decent VHDL or Verilog textbook
- there are many out there.  For VHDL I like Andrew Rushton's VHDL for
Logic Synthesis, but that's a personal preferance.  For Verilog I have
no idea, but I'm sure many people here would be happy to recommend you
one.



On May 14, 2:31 am, "Marco T." <marcotos...@gmail.com> wrote:
> Hallo,
> which is the way to perform digital vgain and offset correction using
> a fpga?
>
> Thanks,
> Marco T.



Article: 119169
Subject: Re: How to Ask a Question
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 14 May 2007 15:45:51 +0100
Links: << >>  << T >>  << A >>
"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message 
news:1o0g43df683o804jovq1abubr2a0mhf1fe@4ax.com...
> Hi -
>
> In light of a recent flameboree in these parts, I thought it might be
> helpful to provide a link to an article entitled, "How to Ask a
> Question the Smart Way."  Although aimed at programmers and programmer
> wannabes, the advice is equally applicable to hardware designers old
> and new.
>
> http://www.catb.org/~esr/faqs/smart-questions.html
>
> The article's been translated into two dozen languages; look for the
> links under the "Translations" header.
>
> Bob Perlman
> Cambrian Design Works
> http://www.cambriandesign.com

Hi Bob,
I agree totally. I find that if you think of a good subject line for your 
post, nine times out of ten you get a quicker and better answer putting that 
text into the Google search box than you do from a newsgroup.
Cheers, Syms.
p.s. The Google toolbar has this great feature where you can add a Xilinx 
(or anything else) search to your toolbar. If you have the thing installed, 
go to the Xilinx website, right click on the search box in the top right, 
click 'Generate Custom Search' in the menu box. V. useful. 



Article: 119170
Subject: Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;)
From: Zara <me_zara@dea.spamcon.org>
Date: Mon, 14 May 2007 17:05:19 +0200
Links: << >>  << T >>  << A >>
On 14 May 2007 06:30:28 -0700, Antti <Antti.Lukats@xilant.com> wrote:
>On 14 Mai, 15:10, Zara <me_z...@dea.spamcon.org> wrote:
>> On 14 May 2007 04:22:18 -0700, Antti <Antti.Luk...@xilant.com> wrote:
>>
>> >On 14 Mai, 13:15, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de>
>> >wrote:
>> >> Antti <Antti.Luk...@xilant.com> wrote:
>> >> > As subject: all system are go and green on the Spartan-3A Starterkit
>> >> > board.
>> >> > No issues. Just working :)
>> >> > Antti Lukats
<...>
>> Ah, Antti, you are a genius!
>> I was stuck with the way to receive the clk feedback from DDR to
>> connect to the corresponding opb_mch_ddr pins. I completely overlooked
>> the possibility of generating *2* clock pairs. I had even thought of
>> shorting clock output to LOOP_IN or LOOP_OUT!
>>
>> NTW, why do you use the combination of DCM outputs + inverters instead
>> of directly using the 180/270 outputs? I thought  the secodn solution
>> should be better... but now I don' know
>>
<...>
>
>actually this time its not me who genius. but generically I am too ;)
>
>to your questions: the "two clock pairs" is used often in several
>other designs as well.
>and yes, until you see it done this way, you look for other more
>harder ways :(
>
>the DCM scheme, well there are different possibilities, the one that
>is used
>is minimizing the BUFG usage, if you are not running low on BUFG you
>can
>use the other scheme with more BUFG useage as well.
>

Thanks!

Zara

Article: 119171
Subject: Anyone using the TimingAnalyzer
From: chewie54 <dfabrizio51@gmail.com>
Date: 14 May 2007 09:18:38 -0700
Links: << >>  << T >>  << A >>
Hello All,

Back in the 2002,  I was developing a program called the
TimingAnalyzer.   Below is a copy of an announcement made
on this forum back then.

I was wondering if anyone has been using it since then or what
programs your are using to do timing diagrams?

Regards,
Dan Fabrizio

------------------------------------------------------------------------------------------
The TimingAnalyzer can be used to draw timing diagrams and
check for timing problems in digital systems. The diagrams
can be included in word processing documents, printed, or
saved as image files.

Signals, clocks, buses, logic gate functions, counters,
shift registers, delays, constraints, arithmetic functions,
statebars, and text labels can be easily added using the GUI.

Part libraries are saved in text files so the user can easily
add new parts, delays, constraints, or completely
new libraries. The timing diagram is also saved as text so it
can easily be distributed or modified.

It was written using Java with the intention of being a single source
cross-platform application. I'm testing it in Windows and Linux.


Article: 119172
Subject: does SRL exist in non-xilinx FPGAs?
From: tlenomade@googlemail.com
Date: 14 May 2007 09:21:51 -0700
Links: << >>  << T >>  << A >>
Hey,

Is there any non-xilinx FPGA that has the equivalent of Xilinx Virtex
SRL component as a basic component logic? If Not, why? has Xilinx
patented it?

Many Thanks  :)


Article: 119173
Subject: Re: does SRL exist in non-xilinx FPGAs?
From: austin <austin@xilinx.com>
Date: Mon, 14 May 2007 09:43:42 -0700
Links: << >>  << T >>  << A >>
?

Xilinx has patents on the use of a LUT as a LUT, SRL, or LUTRAM (by
configuration).  This is presumably broad enough that others have
decided not to try to "design around" the patents, but have rather
decided to provide similar function through other means.

There is nothing to prevent someone from inserting a shift register in
their logic block as a completely separate element.  They just are not
able to use the LUT bits to perform the function (as that is one of our
basic claims).

FPGA repeatable interconnect structure with hierarchical interconnect
lines US Pat. 5914616 - Filed Feb 26, 1997 - XILINX, Inc.
When function generators F, G, H, J are configured as shift registers as
described by Bauer, the shift register data input signal is taken from
BF, BG, BH, ...

FPGA architecture with deep look-up table RAMs
US Pat. 6288568 - Filed May 19, 2000 - Xilinx, Inc.
11 12 historically paired with flip-flops in Xilinx logic elements.
location in a shift register and all other data are shifted one Further,
when an n-bit, ...

Linear feedback shift register in a programmable gate array
US Pat. 6181164 - Filed May 13, 1999 - Xilinx, Inc.
Before data is fed back into the gates as shown and which can be
implemented with a shift register, parity must have been generated from
all the 4-LUT. ...

Structure for optionally cascading shift registers US Pat. 6118298 -
Filed Feb 18, 1999 - Xilinx, Inc. first full 16-bit shift register 1200
addressed to 1111, a second full ... 8 provides only a single output
from each LUT, (outputs are labeled X and Y), ...

FPGA repeatable interconnect structure with bidirectional and
unidirectional interconnect lines US Pat. 5942913 - Filed Mar 20, 1997 -
Xilinx, Inc. For example, pages 4-11 through 4-23 of the Xilinx 1996
Data Book ... the shift register data input signal is taken from BF, BG,
BH, BJ, respectively. ...

Configurable logic element with ability to evaluate five and six input
functions US Pat. 5920202 - Filed Apr 4, 1997 - Xilinx, Inc.
The function generator of this embodiment can therefore be configured as
a look-up table, a shift register, a 16x1 RAM, half of a 16x1
dual-ported RAM (when ...

FPGA lookup table with speed read decoder US Pat. 6529040 - Filed May 5,
2000 - Xilinx, Inc. In addition to the configuration mode and memory
read/ write operations, LUT 300 can implement a shift register. During
shift register operations, ...

FIFO in FPGA having logic elements that include cascadable shift
registers US Pat. 6262597 - Filed Jul 24, 2000 - Xilinx, Inc.
If a shift register FIFO is desired that is no more than 16 words deep,
then such a 10 the right of the picture, for example cell 77016 of LUT-F
of slice ...

FPGA lookup table with dual ended writes for ram and shift register
modes US Pat. 6373279 - Filed May 5, 2000 - Xilinx, Inc.
In addition to the configuration mode and memory read/ write operations,
LUT 300 can implement a shift register. During shift register
operations, ...

(above from google patents).

The oldest patents are from 1997, so they have a while yet before they
expire.

Next time you have a question like this, try google patent!

http://www.google.com/patents

Austin

Article: 119174
Subject: Lockup with Xilinx mch_opb_ddr
From: acher@in.tum.de (Georg Acher)
Date: Mon, 14 May 2007 17:35:20 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hi,

I'm using the mch_opb_ddr-controller V1.00c from EDK8.2 in a Microblaze design. 
Beside the Microblaze, another bus master is accessing the DDR. Since I need to
avoid some deadlocks over the OPB-Bus, I've added a third MCH to the mch_opb_ddr,
which my bus master is using. The protocol is also simpler and a bit faster than
OPB, so it sounds like a good choice just for RAM-access. In principle it works,
but it hangs during heavy traffic :-(

This happens usually during a read from my side, where the read address is put on
the MCH2 along with "control"=0 and "write"=1 for one clock. But no "exists"
appears, the Microblaze is dead, even DDR-RAM access over JTAG fails. On the
DDR-side no access can be seen, only the refresh runs.

When I swap "my" MCH with the instruction cache-MCH, the lockup appears much
earlier.

I already made sure that no address outside of the DDR-area is accessed, the
timing looks good, too. I thought that one can't do anything wrong with just two
control signals... To me, it looks like an arbitration issue when the whole
controller stops.

Is there something special to know about the MCH/XCL and its usage? Are there
issues with more than 2 MCH channels? 

-- 
         Georg Acher, acher@in.tum.de
         http://www.lrr.in.tum.de/~acher
         "Oh no, not again !" The bowl of petunias



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search