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Try this: http://xgoogle.xilinx.com/search?getfields=*&numgm=5&filter=0&proxystylesheet=xilinx&client=xilinx&site=EntireSite&btnG=Google+Search&output=xml_no_dtd&sort=date%3aD%3aL%3ad1&ie=UTF-8&oe=UTF-8&requiredfields=-status:archive&q=ddr+phase+shift&submit2.x=0&submit2.y=0&submit2=Search&lang2search= or search xilinx website for ddr phase shiftArticle: 127301
Images of the new version of Tarfessock1 here http://www.enterpoint.co.uk/moelbryn/tarfessock1.html. We have replaced the connector that has been giving us supply issues and we expect to complete testing of the new version in early January. They will ship shortly afterwards to customers assuming no major issues in testing program. The new versions of the Craignell FPGA DIL modules are now in test and these also should available soon. The new programming adaptor for these is expected mid January and we will do a full launch of the product then. If you want to lash up a crude adaptor of your own and desperate for a module please do contact our sales team for advance shipping of the launch of the new versions. The low cost sister product Drigmorn1 has now shipped to the first customers. It should be appearing on the shop website soon but in the meantime just contact our sales team if you want one as it is available. John Adair Enterpoint Ltd.Article: 127302
I am trying to covert the following Verilog code to VHDL. I am having issues with converting the arrays to VHDL. Could you please comment on how this should be done module FIFO16x8(DataOut, DataIn, FF, AF, HF, AE, EF, Push, Pop, Dump, Clk); parameter WIDTH = 8; parameter DEPTH = 16; parameter LOG2DEPTH = 4; input [(WIDTH-1):0] DataIn; output [(WIDTH-1):0] DataOut; output FF, AF, HF, AE, EF; input Push, Pop, Dump, Clk; wire WE, RE; reg [(LOG2DEPTH-1):0] Contents, ReadPointer, WritePointer; reg [(WIDTH-1):0] queue[(DEPTH-1):0]; assign FF = (Contents == (DEPTH-1))? 1 : 0; assign AF = (Contents > (DEPTH-3))? 1 : 0; assign HF = (Contents > (DEPTH/2))? 1 : 0; assign AE = (Contents < 3)? 1 : 0; assign EF = (Contents == 0)? 1 : 0; assign WE = Push && ~FF; assign RE = Pop && ~EF; assign DataOut = queue[ReadPointer]; always @ (posedge Clk) begin if (Dump == 1) Contents <= 0; else if ((WE == 1) && (RE == 0)) Contents <= Contents + 1; else if ((WE == 0) && (RE == 1)) Contents <= Contents - 1; else Contents <= Contents; end always @ (posedge Clk) begin if (Dump == 1) begin ReadPointer <= 0; WritePointer <= 0; end else begin if (RE == 1) begin ReadPointer <= ReadPointer + 1; end if (WE == 1) begin queue[WritePointer] <= DataIn; WritePointer <= WritePointer + 1; end end end endmodule I have declared an array in VHDL as follows TYPE queue IS ARRAY (7 DOWNTO 0, 15 DOWNTO 0) OF std_logic_vector(7 downto 0); I am not sure about how to convert the Verilog statements belwo to VHDL. Verilog code is referenced above. assign DataOut = queue[ReadPointer]; and queue[WritePointer] <= DataIn; thanks AnujaArticle: 127303
On Dec 17, 6:11 am, Nicolas Matringe <nic_o_...@msn.com> wrote: > Hello all > I am struggling with ISE and CoreGen to generate a memory block that > would be customizable (mainly in depth & width) through generic > parameters. > The Memory block generator datasheet seems to indicate that this is > possible but does not explain how. All there is is the parameters > list. > > ISE keeps telling me "Port <xxxx> of instance <blk_mem_inst> has > different type in definition <blk_mem>" > I don't have any component named blk_mem (I had generated one with the > GUI but I have deleted it and removed from ISE project) > > Thanks in advance > Nicolas Memory blocks generated using CoreGen will have fixed widths and depth. The VHDL file generated is only for simulation (Using XilinxCoreLib) and the actual implementation is in the EDIF file. The EDIF file is used by ISE during synthesis. One way to get configurable memory using generics is to let the synthesis tool (XST, Leonardo Spectrum etc.) infer block ram from VHDL code. Here is a link which may be useful http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/vtex11.html Hope this helps. -Sudheendra KadriArticle: 127304
On Dec 17, 2:04 pm, Anuja <thakkar.an...@gmail.com> wrote: > I am trying to covert the following Verilog code to VHDL. I am having > issues with converting the arrays to VHDL. Could you please comment on > how this should be done > module FIFO16x8(DataOut, DataIn, FF, AF, HF, AE, EF, Push, Pop, Dump, > Clk); > parameter WIDTH = 8; > parameter DEPTH = 16; > parameter LOG2DEPTH = 4; > > input [(WIDTH-1):0] DataIn; > output [(WIDTH-1):0] DataOut; > output FF, AF, HF, AE, EF; > input Push, Pop, Dump, Clk; > > wire WE, RE; > > reg [(LOG2DEPTH-1):0] Contents, ReadPointer, WritePointer; > reg [(WIDTH-1):0] queue[(DEPTH-1):0]; > > assign FF = (Contents == (DEPTH-1))? 1 : 0; > assign AF = (Contents > (DEPTH-3))? 1 : 0; > assign HF = (Contents > (DEPTH/2))? 1 : 0; > assign AE = (Contents < 3)? 1 : 0; > assign EF = (Contents == 0)? 1 : 0; > > assign WE = Push && ~FF; > assign RE = Pop && ~EF; > > assign DataOut = queue[ReadPointer]; > > always @ (posedge Clk) > begin > if (Dump == 1) > Contents <= 0; > else > if ((WE == 1) && (RE == 0)) > Contents <= Contents + 1; > else > if ((WE == 0) && (RE == 1)) > Contents <= Contents - 1; > else > Contents <= Contents; > end > > always @ (posedge Clk) > begin > if (Dump == 1) > begin > ReadPointer <= 0; > WritePointer <= 0; > end > else > begin > if (RE == 1) > begin > ReadPointer <= ReadPointer + 1; > end > if (WE == 1) > begin > queue[WritePointer] <= DataIn; > WritePointer <= WritePointer + 1; > end > end > end > > endmodule > > I have declared an array in VHDL as follows > TYPE queue IS ARRAY (7 DOWNTO 0, 15 DOWNTO 0) > OF std_logic_vector(7 downto 0); > > I am not sure about how to convert the Verilog statements belwo to > VHDL. Verilog code is referenced above. > assign DataOut = queue[ReadPointer]; > and > queue[WritePointer] <= DataIn; > > thanks > Anuja Use, TYPE queue IS ARRAY(15 DOWNTO 0) OF std_logic_vector(7 DOWNTO 0); Since your read and write pointers are std_logic_vectors, they cannot be used for indexing into and array. Convert them to integers using the functions in numeric_std package like so DataOut <= queue(to_integer(ReadPointer)); and queue(to_integer(WritePointer)) <= DataIn; Hope this helps, Sudheendra KadriArticle: 127305
On Dec 17, 4:30 pm, sudhi <sudhi.ka...@gmail.com> wrote: > On Dec 17, 2:04 pm, Anuja <thakkar.an...@gmail.com> wrote: > > > > > > > I am trying to covert the following Verilog code to VHDL. I am having > > issues with converting the arrays to VHDL. Could you please comment on > > how this should be done > > module FIFO16x8(DataOut, DataIn, FF, AF, HF, AE, EF, Push, Pop, Dump, > > Clk); > > parameter WIDTH = 8; > > parameter DEPTH = 16; > > parameter LOG2DEPTH = 4; > > > input [(WIDTH-1):0] DataIn; > > output [(WIDTH-1):0] DataOut; > > output FF, AF, HF, AE, EF; > > input Push, Pop, Dump, Clk; > > > wire WE, RE; > > > reg [(LOG2DEPTH-1):0] Contents, ReadPointer, WritePointer; > > reg [(WIDTH-1):0] queue[(DEPTH-1):0]; > > > assign FF = (Contents == (DEPTH-1))? 1 : 0; > > assign AF = (Contents > (DEPTH-3))? 1 : 0; > > assign HF = (Contents > (DEPTH/2))? 1 : 0; > > assign AE = (Contents < 3)? 1 : 0; > > assign EF = (Contents == 0)? 1 : 0; > > > assign WE = Push && ~FF; > > assign RE = Pop && ~EF; > > > assign DataOut = queue[ReadPointer]; > > > always @ (posedge Clk) > > begin > > if (Dump == 1) > > Contents <= 0; > > else > > if ((WE == 1) && (RE == 0)) > > Contents <= Contents + 1; > > else > > if ((WE == 0) && (RE == 1)) > > Contents <= Contents - 1; > > else > > Contents <= Contents; > > end > > > always @ (posedge Clk) > > begin > > if (Dump == 1) > > begin > > ReadPointer <= 0; > > WritePointer <= 0; > > end > > else > > begin > > if (RE == 1) > > begin > > ReadPointer <= ReadPointer + 1; > > end > > if (WE == 1) > > begin > > queue[WritePointer] <= DataIn; > > WritePointer <= WritePointer + 1; > > end > > end > > end > > > endmodule > > > I have declared an array in VHDL as follows > > TYPE queue IS ARRAY (7 DOWNTO 0, 15 DOWNTO 0) > > OF std_logic_vector(7 downto 0); > > > I am not sure about how to convert the Verilog statements belwo to > > VHDL. Verilog code is referenced above. > > assign DataOut = queue[ReadPointer]; > > and > > queue[WritePointer] <= DataIn; > > > thanks > > Anuja > > Use, > > TYPE queue IS ARRAY(15 DOWNTO 0) OF std_logic_vector(7 DOWNTO 0); > > Since your read and write pointers are std_logic_vectors, they cannot > be used for indexing into and array. Convert them to integers using > the functions in numeric_std package like so > > DataOut <= queue(to_integer(ReadPointer)); > > and > > queue(to_integer(WritePointer)) <= DataIn; > > Hope this helps, > Sudheendra Kadri- Hide quoted text - > > - Show quoted text - Shouldnt the array be multidimensional? Isnt the array you defined one dimensional?Article: 127306
On Dec 17, 4:39 pm, Anuja <thakkar.an...@gmail.com> wrote: > On Dec 17, 4:30 pm, sudhi <sudhi.ka...@gmail.com> wrote: > > > > > > > On Dec 17, 2:04 pm, Anuja <thakkar.an...@gmail.com> wrote: > > > > I am trying to covert the following Verilog code to VHDL. I am having > > > issues with converting the arrays to VHDL. Could you please comment on > > > how this should be done > > > module FIFO16x8(DataOut, DataIn, FF, AF, HF, AE, EF, Push, Pop, Dump, > > > Clk); > > > parameter WIDTH = 8; > > > parameter DEPTH = 16; > > > parameter LOG2DEPTH = 4; > > > > input [(WIDTH-1):0] DataIn; > > > output [(WIDTH-1):0] DataOut; > > > output FF, AF, HF, AE, EF; > > > input Push, Pop, Dump, Clk; > > > > wire WE, RE; > > > > reg [(LOG2DEPTH-1):0] Contents, ReadPointer, WritePointer; > > > reg [(WIDTH-1):0] queue[(DEPTH-1):0]; > > > > assign FF = (Contents == (DEPTH-1))? 1 : 0; > > > assign AF = (Contents > (DEPTH-3))? 1 : 0; > > > assign HF = (Contents > (DEPTH/2))? 1 : 0; > > > assign AE = (Contents < 3)? 1 : 0; > > > assign EF = (Contents == 0)? 1 : 0; > > > > assign WE = Push && ~FF; > > > assign RE = Pop && ~EF; > > > > assign DataOut = queue[ReadPointer]; > > > > always @ (posedge Clk) > > > begin > > > if (Dump == 1) > > > Contents <= 0; > > > else > > > if ((WE == 1) && (RE == 0)) > > > Contents <= Contents + 1; > > > else > > > if ((WE == 0) && (RE == 1)) > > > Contents <= Contents - 1; > > > else > > > Contents <= Contents; > > > end > > > > always @ (posedge Clk) > > > begin > > > if (Dump == 1) > > > begin > > > ReadPointer <= 0; > > > WritePointer <= 0; > > > end > > > else > > > begin > > > if (RE == 1) > > > begin > > > ReadPointer <= ReadPointer + 1; > > > end > > > if (WE == 1) > > > begin > > > queue[WritePointer] <= DataIn; > > > WritePointer <= WritePointer + 1; > > > end > > > end > > > end > > > > endmodule > > > > I have declared an array in VHDL as follows > > > TYPE queue IS ARRAY (7 DOWNTO 0, 15 DOWNTO 0) > > > OF std_logic_vector(7 downto 0); > > > > I am not sure about how to convert the Verilog statements belwo to > > > VHDL. Verilog code is referenced above. > > > assign DataOut = queue[ReadPointer]; > > > and > > > queue[WritePointer] <= DataIn; > > > > thanks > > > Anuja > > > Use, > > > TYPE queue IS ARRAY(15 DOWNTO 0) OF std_logic_vector(7 DOWNTO 0); > > > Since your read and write pointers are std_logic_vectors, they cannot > > be used for indexing into and array. Convert them to integers using > > the functions in numeric_std package like so > > > DataOut <= queue(to_integer(ReadPointer)); > > > and > > > queue(to_integer(WritePointer)) <= DataIn; > > > Hope this helps, > > Sudheendra Kadri- Hide quoted text - > > > - Show quoted text - > > Shouldnt the array be multidimensional? Isnt the array you defined one > dimensional?- Hide quoted text - > > - Show quoted text - I am getting the following error message No feasible entries for subprogram "to_integer". I HAVE INCLUDED NUMERIC_STD package as follows LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; USE IEEE.numeric_std.ALL; It also comlained about target of signal assignment is not a signal. So, I defined q_queue of type queue(array) and that was solved.Article: 127307
On Dec 17, 2:53 pm, Anuja <thakkar.an...@gmail.com> wrote: > On Dec 17, 4:39 pm, Anuja <thakkar.an...@gmail.com> wrote: > > > > > On Dec 17, 4:30 pm, sudhi <sudhi.ka...@gmail.com> wrote: > > > > On Dec 17, 2:04 pm, Anuja <thakkar.an...@gmail.com> wrote: > > > > > I am trying to covert the following Verilog code to VHDL. I am having > > > > issues with converting the arrays to VHDL. Could you please comment on > > > > how this should be done > > > > module FIFO16x8(DataOut, DataIn, FF, AF, HF, AE, EF, Push, Pop, Dump, > > > > Clk); > > > > parameter WIDTH = 8; > > > > parameter DEPTH = 16; > > > > parameter LOG2DEPTH = 4; > > > > > input [(WIDTH-1):0] DataIn; > > > > output [(WIDTH-1):0] DataOut; > > > > output FF, AF, HF, AE, EF; > > > > input Push, Pop, Dump, Clk; > > > > > wire WE, RE; > > > > > reg [(LOG2DEPTH-1):0] Contents, ReadPointer, WritePointer; > > > > reg [(WIDTH-1):0] queue[(DEPTH-1):0]; > > > > > assign FF = (Contents == (DEPTH-1))? 1 : 0; > > > > assign AF = (Contents > (DEPTH-3))? 1 : 0; > > > > assign HF = (Contents > (DEPTH/2))? 1 : 0; > > > > assign AE = (Contents < 3)? 1 : 0; > > > > assign EF = (Contents == 0)? 1 : 0; > > > > > assign WE = Push && ~FF; > > > > assign RE = Pop && ~EF; > > > > > assign DataOut = queue[ReadPointer]; > > > > > always @ (posedge Clk) > > > > begin > > > > if (Dump == 1) > > > > Contents <= 0; > > > > else > > > > if ((WE == 1) && (RE == 0)) > > > > Contents <= Contents + 1; > > > > else > > > > if ((WE == 0) && (RE == 1)) > > > > Contents <= Contents - 1; > > > > else > > > > Contents <= Contents; > > > > end > > > > > always @ (posedge Clk) > > > > begin > > > > if (Dump == 1) > > > > begin > > > > ReadPointer <= 0; > > > > WritePointer <= 0; > > > > end > > > > else > > > > begin > > > > if (RE == 1) > > > > begin > > > > ReadPointer <= ReadPointer + 1; > > > > end > > > > if (WE == 1) > > > > begin > > > > queue[WritePointer] <= DataIn; > > > > WritePointer <= WritePointer + 1; > > > > end > > > > end > > > > end > > > > > endmodule > > > > > I have declared an array in VHDL as follows > > > > TYPE queue IS ARRAY (7 DOWNTO 0, 15 DOWNTO 0) > > > > OF std_logic_vector(7 downto 0); > > > > > I am not sure about how to convert the Verilog statements belwo to > > > > VHDL. Verilog code is referenced above. > > > > assign DataOut = queue[ReadPointer]; > > > > and > > > > queue[WritePointer] <= DataIn; > > > > > thanks > > > > Anuja > > > > Use, > > > > TYPE queue IS ARRAY(15 DOWNTO 0) OF std_logic_vector(7 DOWNTO 0); > > > > Since your read and write pointers are std_logic_vectors, they cannot > > > be used for indexing into and array. Convert them to integers using > > > the functions in numeric_std package like so > > > > DataOut <= queue(to_integer(ReadPointer)); > > > > and > > > > queue(to_integer(WritePointer)) <= DataIn; > > > > Hope this helps, > > > Sudheendra Kadri- Hide quoted text - > > > > - Show quoted text - > > > Shouldnt the array be multidimensional? Isnt the array you defined one > > dimensional?- Hide quoted text - > > > - Show quoted text - > > I am getting the following error message > No feasible entries for subprogram "to_integer". > > I HAVE INCLUDED NUMERIC_STD package as follows > > LIBRARY IEEE; > USE IEEE.std_logic_1164.ALL; > USE IEEE.std_logic_unsigned.ALL; > USE IEEE.numeric_std.ALL; > > It also comlained about target of signal assignment is not a signal. > So, I defined q_queue of type queue(array) and that was solved. Take a look at this for the conversion problem http://dz.ee.ethz.ch/support/ic/vhdl/vhdlsources.en.html In a fifo you only need a single dimensional array of std_logic_vectors. If the fifo is bit addressable then you could call this declaration a multidimensional array. -Sudheendra KadriArticle: 127308
comp.arch.fpga wrote: > At these low quantities I suggest that you use a device that has > ethernet MACs included. (Virtex-4 FX, Virtex-5 LXT). May I ask why an FPGA has to be used at all? A whole assembled and tested board (like Gumstix for example) with a fast (say 200 MIPS) uC and ethernet and full FREE TCP/IP and what not costs much less than a Virtex chip alone... If some task had to be done by hard logic, just add a cheap Spartan 3e or whatever... -Alex.Article: 127309
Greetings, What's the best way to clock DDR flops from a DCM? In all the DDR I/O I've produced, I've always used the DCM clock output through a BUFG, feeding the normal and inverted versions of that buffered clock to my I/O registers. I understand that - at least in some silicon - there can be duty-cycle distortion that would compromise this normal/invert approach versus the alternative.... Much of the early DDR information suggested using the 0 and 180 degree outputs from the DCM. I never considered this a good design practice because the outputs are going through different BUFGs with different clock loads on each net resulting in a designed-in skew that would compromise the DDR sampling windows. Is there any real evidence one way or the other to suggest that one of these approaches is better than the other? I was sad to see the code for xapp485 appears to use two BUFGs, but not for CLKFX and CLKFX180, but inputs of CLKFX and ~CLKFX! If that's not a bastardization of the two choices, I'm not sure what is. Don't newer parts route differential clocks for single global clock nets now? Or is that just the Virtex series? My designs are currently Spartan-3E with DDR I/O in the 400-600 Mb/s range. - John_HArticle: 127310
On 12=D4=C217=C8=D5, =CF=C2=CE=E76=CA=B113=B7=D6, "Symon" <symon_bre...@hotm= ail.com> wrote: > <wxy0...@gmail.com> wrote in message > > news:58990fd1-be0d-410e-85ad-37765935953b@e6g2000prf.googlegroups.com... > > > > > > > Xilinx V4SX35 > > ISE 8.2.03 > > Modelsim > > > I got CLKI(300MHz), CLKI_DIV(150MHz) generated through a counter(just > > a flip_flop) clocked by CLKI, both clocks connect to BUFG. Then I use > > CLKI to sample data generated byCLKI_DIV(width=3D160bit), simulation > > result in some warnings which said setuptime is not enough during > > sampling. How can I constraint PAR to get enough setuptime? > > > Because of funtion request, I can not use DCM and OSERDES. The minimum > > delay between risingedge of CLKI_DIV and CLKI is much more than the > > period of CLKI. I have to make sure all simultaneous data sampled by > > CLKI simultaneously. But actually, there always some bits sampled a > > period(CLKI) later or earlier. I can constraint the max delay from the > > last 150MHz flip-flop to the first 300MHz flip-flop, but how can I > > constraint the minimum delay? > > > Thank you!! > > Dear Whoever, > Use CLKI to clock _all_ the synchronous elements. Use CLKI_DIV as the cloc= k > enable for all the synchronous elements you were going to clock with > CLKI_DIV. > HTH., Syms.- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - Thanks! That is exactly what I am doing now, and the FPGA is working properly under lab condition. It just a warning during simulation. I just worry about when the environment, for example, the voltage changes, the temperature changes, or something like that. I move the flipflop which generate CLKI_DIV to change the phase relationship between the two clocks, but it's time consuming and not effective. Is there some other methods to achieve the setup time? Some kind of constraints in the UCF file?Article: 127311
"John_H" <newsgroup@johnhandwork.com> wrote in message news:0971fbbb-c439-43eb-acca-689c3c284a70@e25g2000prg.googlegroups.com... > Greetings, > > What's the best way to clock DDR flops from a DCM? > > In all the DDR I/O I've produced, I've always used the DCM clock > output through a BUFG, feeding the normal and inverted versions of > that buffered clock to my I/O registers. I understand that - at least > in some silicon - there can be duty-cycle distortion that would > compromise this normal/invert approach versus the alternative.... > > Much of the early DDR information suggested using the 0 and 180 degree > outputs from the DCM. I never considered this a good design practice > because the outputs are going through different BUFGs with different > clock loads on each net resulting in a designed-in skew that would > compromise the DDR sampling windows. > > Is there any real evidence one way or the other to suggest that one of > these approaches is better than the other? > > I was sad to see the code for xapp485 appears to use two BUFGs, but > not for CLKFX and CLKFX180, but inputs of CLKFX and ~CLKFX! If that's > not a bastardization of the two choices, I'm not sure what is. > > Don't newer parts route differential clocks for single global clock > nets now? Or is that just the Virtex series? My designs are > currently Spartan-3E with DDR I/O in the 400-600 Mb/s range. > > - John_H Using the CLK0 and CLK180 DCM outputs into two BUFGs produces less duty cycle distortion than using one clock at the IOB plus the IOB's locally inverted clock, when doing DDR stuff. This makes sense because the locally inverted clock will always have some delay with respect to its source clock. The Xilinx documentation for high speed RAM interfaces should confirm this. I believe that Virtex5 is the first family to use differential clocks internally, and this will further reduce duty cycle distortion when using DDR techniques. BobArticle: 127312
Hello ! Does someone have verilog-HDL sample apply to Xilinx Evaluation boad [TB-4V-FX60-PRO] ? I want to sample source. I will implement only ISE tool by nothing EDK tool.Article: 127313
Hi,
I'm planning to purchase the Darnaw1 PGA module (http://
www.enterpoint.co.uk/moelbryn/darnaw1.html). for my audio console
project. Has anyone worked on this module?
About my audio console project.
It basically consists of a system controller (ARM7/ARM9) and an FPGA.
The FPGA contains all the periperals like, S/PDIF receiver, ATA HDD
interface, FTDI Vinculum USB host interface, multichannel audio codec,
STA013 mp3 player interface etc. The FPGA will be connected to the
ARM7/9 through External Bus Interface (EBI).All the peripherals on the
FPGA will be mapped to some address on the EBI of ARM. Since there are
a lot of peripherals on the FPGA i'll require a lot of logic and I/O
too. I cannot afford to design/fabricate 6 layer + boards required for
such an FPGA. Darnaw looks like the perfect solution.
Aravind.
Article: 127314On Dec 17, 3:23 pm, sudhi <sudhi.ka...@gmail.com> wrote: > On Dec 17, 6:11 am, Nicolas Matringe <nic_o_...@msn.com> wrote: > > > Hello all > > I am struggling with ISE and CoreGen to generate a memory block that > > would be customizable (mainly in depth & width) through generic > > parameters. > > The Memory block generator datasheet seems to indicate that this is > > possible but does not explain how. All there is is the parameters > > list. > > > ISE keeps telling me "Port <xxxx> of instance <blk_mem_inst> has > > different type in definition <blk_mem>" > > I don't have any component named blk_mem (I had generated one with the > > GUI but I have deleted it and removed from ISE project) > > > Thanks in advance > > Nicolas > > Memory blocks generated using CoreGen will have fixed widths and > depth. The VHDL file generated is only for simulation (Using > XilinxCoreLib) and the actual implementation is in the EDIF file. The > EDIF file is used by ISE during synthesis. > > One way to get configurable memory using generics is to let the > synthesis tool (XST, Leonardo Spectrum etc.) infer block ram from VHDL > code. > > Here is a link which may be useful > > http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/vtex11.html > > Hope this helps. > -Sudheendra Kadri The Xilinx XST documentation will provide the HDL coding structure needed to infer various RAM types. You don't necessarily need to use the LogicCore generator for RAM. Darol KlawetterArticle: 127315
>On Dec 17, 4:39 pm, Anuja <thakkar.an...@gmail.com> wrote: >> On Dec 17, 4:30 pm, sudhi <sudhi.ka...@gmail.com> wrote: <snip /> >> >> > Since your read and write pointers are std_logic_vectors, they cannot >> > be used for indexing into and array. Convert them to integers using >> > the functions in numeric_std package like so >> >> > DataOut <= queue(to_integer(ReadPointer)); >> >> > and >> >> > queue(to_integer(WritePointer)) <= DataIn; >> >> > Hope this helps, >> > Sudheendra Kadri- Hide quoted text - >> >> > - Show quoted text - >> >> Shouldnt the array be multidimensional? Isnt the array you defined one >> dimensional?- Hide quoted text - >> >> - Show quoted text - > >I am getting the following error message >No feasible entries for subprogram "to_integer". > >I HAVE INCLUDED NUMERIC_STD package as follows > >LIBRARY IEEE; >USE IEEE.std_logic_1164.ALL; >USE IEEE.std_logic_unsigned.ALL; >USE IEEE.numeric_std.ALL; > >It also comlained about target of signal assignment is not a signal. >So, I defined q_queue of type queue(array) and that was solved. > > You do not need "USE IEEE.std_logic_unsigned.ALL;" Instead do a cast to type 'unsigned'... DataOut <= queue(to_integer(unsigned(ReadPointer))); queue(to_integer(unsigned(WritePointer))) <= DataIn;Article: 127316
On 18 Dez., 10:31, "RCIngham" <robert.ing...@gmail.com> wrote: > >On Dec 17, 4:39 pm, Anuja <thakkar.an...@gmail.com> wrote: > >> On Dec 17, 4:30 pm, sudhi <sudhi.ka...@gmail.com> wrote: > > <snip /> > > > > > > > > >> > Since your read and write pointers are std_logic_vectors, they > cannot > >> > be used for indexing into and array. Convert them to integers using > >> > the functions in numeric_std package like so > > >> > DataOut <= queue(to_integer(ReadPointer)); > > >> > and > > >> > queue(to_integer(WritePointer)) <= DataIn; > > >> > Hope this helps, > >> > Sudheendra Kadri- Hide quoted text - > > >> > - Show quoted text - > > >> Shouldnt the array be multidimensional? Isnt the array you defined one > >> dimensional?- Hide quoted text - > > >> - Show quoted text - > > >I am getting the following error message > >No feasible entries for subprogram "to_integer". > > >I HAVE INCLUDED NUMERIC_STD package as follows > > >LIBRARY IEEE; > >USE IEEE.std_logic_1164.ALL; > >USE IEEE.std_logic_unsigned.ALL; > >USE IEEE.numeric_std.ALL; > > >It also comlained about target of signal assignment is not a signal. > >So, I defined q_queue of type queue(array) and that was solved. > > You do not need "USE IEEE.std_logic_unsigned.ALL;" In fact, including both is dangerous. Also, std_logic_unisgned is deprecated. > Instead do a cast to type 'unsigned'... > DataOut <= queue(to_integer(unsigned(ReadPointer))); > queue(to_integer(unsigned(WritePointer))) <= DataIn; Or even better, declare read pointer to be an integer to begin with: signal ReadPointer : integer range 0 to RANGE-1 := 0; This avoids both casts. Kolja SulimmaArticle: 127317
On Dec 18, 4:57 am, "comp.arch.fpga" <ksuli...@googlemail.com> wrote: > On 18 Dez., 10:31, "RCIngham" <robert.ing...@gmail.com> wrote: > > > > > >On Dec 17, 4:39 pm, Anuja <thakkar.an...@gmail.com> wrote: > > >> On Dec 17, 4:30 pm, sudhi <sudhi.ka...@gmail.com> wrote: > > > <snip /> > > > >> > Since your read and write pointers are std_logic_vectors, they > > cannot > > >> > be used for indexing into and array. Convert them to integers using > > >> > the functions in numeric_std package like so > > > >> > DataOut <= queue(to_integer(ReadPointer)); > > > >> > and > > > >> > queue(to_integer(WritePointer)) <= DataIn; > > > >> > Hope this helps, > > >> > Sudheendra Kadri- Hide quoted text - > > > >> > - Show quoted text - > > > >> Shouldnt the array be multidimensional? Isnt the array you defined one > > >> dimensional?- Hide quoted text - > > > >> - Show quoted text - > > > >I am getting the following error message > > >No feasible entries for subprogram "to_integer". > > > >I HAVE INCLUDED NUMERIC_STD package as follows > > > >LIBRARY IEEE; > > >USE IEEE.std_logic_1164.ALL; > > >USE IEEE.std_logic_unsigned.ALL; > > >USE IEEE.numeric_std.ALL; > > > >It also comlained about target of signal assignment is not a signal. > > >So, I defined q_queue of type queue(array) and that was solved. > > > You do not need "USE IEEE.std_logic_unsigned.ALL;" > > In fact, including both is dangerous. > Also, std_logic_unisgned is deprecated. > > > Instead do a cast to type 'unsigned'... > > DataOut <= queue(to_integer(unsigned(ReadPointer))); > > queue(to_integer(unsigned(WritePointer))) <= DataIn; > > Or even better, declare read pointer to be an integer to begin with: > signal ReadPointer : integer range 0 to RANGE-1 := 0; > This avoids both casts. > > Kolja Sulimma- Hide quoted text - > > - Show quoted text - My problem was solved by using the package IEEE.std_logic_unsigned.ALL; and I used the function conv_integer which directly converts the std_logic_vector to integer. In this case i do not have to convert the vector to unsigned. Thank you all for your help AnujaArticle: 127318
"John Adair" <g1@enterpoint.co.uk> wrote in message news:c87ced99-3e2a-439e-8beb-89a6636c67be@v4g2000hsf.googlegroups.com... > Images of the new version of Tarfessock1 here > http://www.enterpoint.co.uk/moelbryn/tarfessock1.html. ..snip > product Drigmorn1 has now shipped to the first customers. It should be > appearing on the shop website soon but in the meantime just contact > our sales team if you want one as it is available. To give some independent comments, I got hold of a S500 Drigmorn1 modules (next day delivery, at least in the UK) and I can say it is a very well engineered board. It is amazing how small the Spartan CP132 package is, it is tiny! I ported my CPU86 design (+16550, 60% slices @ 40MHz) without any issues. Nice board and I have no problems recommending it! Hans www.ht-lab.comArticle: 127319
Aravind Most people that has these modules only got them with the new revision release in the last few weeks. The first revison batch was snapped up very rapidly by only 2 or 3 customers taking numbers of units. Those modules ended up in some interesting projects. A lot of modules have shipped in the last few weeks so the same question in a few weeks should get a better response. If you have any questions in the meantime I'll be happy to answer then in the newsgroup or you can place a query with my team on our "support" email - @enterpoint.co.uk. We should be adding some applications and related information over the coming months as soon as we get a little less busy. We have launched a lot of things this month and January will bring some more. The FAQ page on this product will appear soon although most questions so far have been on the I/O available on the PGA (220 from my memory) and on MicroBlaze applications. John Adair Enterpoint Ltd. On 18 Dec, 06:18, aravind <aramos...@gmail.com> wrote: > Hi, > I'm planning to purchase the Darnaw1 PGA module (http://www.enterpoint.co.uk/moelbryn/darnaw1.html). for my audio console > project. Has anyone worked on this module? > > About my audio console project. > It basically consists of a system controller (ARM7/ARM9) and an FPGA. > The FPGA contains all the periperals like, S/PDIF receiver, ATA HDD > interface, FTDI Vinculum USB host interface, multichannel audio codec, > STA013 mp3 player interface etc. The FPGA will be connected to the > ARM7/9 through External Bus Interface (EBI).All the peripherals on the > FPGA will be mapped to some address on the EBI of ARM. Since there are > a lot of peripherals on the FPGA i'll require a lot of logic and I/O > too. I cannot afford to design/fabricate 6 layer + boards required for > such an FPGA. Darnaw looks like the perfect solution. > > Aravind.Article: 127320
Hi All, We are on a new board with on-board XC3S250E-VQ100. All VCCint are 1.2V All VCCaux are 2.5V Bank0 VCCio are 3.3V Bank2 VCCio are 3.3V Bank1 VCCio are un-driven (not powered) Bank3 VCCio are un-driven (not powered) Bank1 VCCio and Bank3 VCCio are connected together We can see a strange issue on VCCio of bank1 and Bank3 if they stay un-driven (not powered). We can see a voltage of 4.64V on Bank1 VCCio and Bank3 VCCio. Now if we charge a 200ohm resistor on Bank1 VCCio we can see a voltage of 4.05V on Bank1 VCCio and Bank3 VCCio. Are there something wrong with our Spartan3E! Why this 4.64V ? Please help to understand. Regards, Laurent www.amontec.comArticle: 127321
Amontec, Larry wrote: > Hi All, > > We are on a new board with on-board XC3S250E-VQ100. > > All VCCint are 1.2V > All VCCaux are 2.5V > Bank0 VCCio are 3.3V > Bank2 VCCio are 3.3V > > Bank1 VCCio are un-driven (not powered) > Bank3 VCCio are un-driven (not powered) > Bank1 VCCio and Bank3 VCCio are connected together > > We can see a strange issue on VCCio of bank1 and Bank3 if they stay > un-driven (not powered). We can see a voltage of 4.64V on Bank1 VCCio > and Bank3 VCCio. > > Now if we charge a 200ohm resistor on Bank1 VCCio we can see a voltage > of 4.05V on Bank1 VCCio and Bank3 VCCio. > > Are there something wrong with our Spartan3E! > Why this 4.64V ? > > Please help to understand. > > Regards, > Laurent > www.amontec.com I forgot to tell that these conditions comes before downloading the FPGA just after the power-on of the board with stable Power Supply.Article: 127322
austin wrote: > The only way to save power is to gate the clock, and turn it off before > it gets to the global clock tree. This may be problematic for timing. > The Xilinx clock tree and the software already turns off unused leaves > of the tree, so saving any power power will require shutting clocks off > completely. If you gate the clock externally to multiple clock inputs, with equal path length and gate delay outside, is there still internal clock skew between different clock inputs? A simple TTL clock gate shouldn't be so hard to do. -- glenArticle: 127323
Hi alll,
I am trying to setup simple TX and RX communication using the MGT
Transceiver without any 8b/10b encoding. I see the exact output TXP
and TXP pins. But the RX data decoded seemed to be misaligned by one
bit. Recovered Clk is buffered to connect to RXUSRCLK_IN and
RXUSRCLK2_IN.
Sample module is given below..
is there anything iam missing here?
Thanks,
Shakith
module rr(BREFCLK_IN,
BREFCLK2_IN,
LOOPBACK_IN,
POWERDOWN_IN,
REFCLKSEL_IN,
RXN_IN,
RXPOLARITY_IN,
RXP_IN,
RXRESET_IN,
RXUSRCLK_IN,
RXUSRCLK2_IN,
TXDATA_IN,
TXINHIBIT_IN,
TXPOLARITY_IN,
TXRESET_IN,
TXUSRCLK_IN,
TXUSRCLK2_IN,
RXBUFSTATUS_OUT,
RXDATA_OUT,
RXRECCLK_OUT,
TXBUFERR_OUT,
TXN_OUT,
TXP_OUT,
rx_status);
input BREFCLK_IN;
input BREFCLK2_IN;
input [1:0] LOOPBACK_IN;
input POWERDOWN_IN;
input REFCLKSEL_IN;
input RXN_IN;
input RXPOLARITY_IN;
input RXP_IN;
input RXRESET_IN;
input RXUSRCLK_IN;
input RXUSRCLK2_IN;
input [19:0] TXDATA_IN;
input TXINHIBIT_IN;
input TXPOLARITY_IN;
input TXRESET_IN;
input TXUSRCLK_IN;
input TXUSRCLK2_IN;
output [1:0] RXBUFSTATUS_OUT;
output [19:0] RXDATA_OUT;
output RXRECCLK_OUT;
output TXBUFERR_OUT;
output TXN_OUT;
output TXP_OUT;
output [2:0] rx_status;
wire GND_BIT;
wire [3:0] GND_BUS_4;
wire [1:0] RXCHARISK_float;
wire [15:0] RXDATA_float;
wire [1:0] RXRUNDISP_float;
wire [1:0] TXCHARDISPMODE_GND;
wire [1:0] TXCHARDISPVAL_GND;
wire [15:0] TXDATA_GND;
wire [3:0] VCC_BUS_4;
assign GND_BIT = 0;
assign GND_BUS_4 = 4'b0000;
assign TXCHARDISPMODE_GND = 2'b00;
assign TXCHARDISPVAL_GND = 2'b00;
assign TXDATA_GND = 16'b0000000000000000;
assign VCC_BUS_4 = 4'b1111;
GT_CUSTOM GT_CUSTOM_INST (.BREFCLK(BREFCLK_IN),
.BREFCLK2(BREFCLK2_IN),
.CHBONDI(GND_BUS_4[3:0]),
.CONFIGENABLE(GND_BIT),
.CONFIGIN(GND_BIT),
.ENCHANSYNC(GND_BIT),
.ENMCOMMAALIGN(GND_BIT),
.ENPCOMMAALIGN(GND_BIT),
.LOOPBACK(LOOPBACK_IN[1:0]),
.POWERDOWN(POWERDOWN_IN),
.REFCLK(GND_BIT),
.REFCLKSEL(REFCLKSEL_IN),
.REFCLK2(GND_BIT),
.RXN(RXN_IN),
.RXP(RXP_IN),
.RXPOLARITY(RXPOLARITY_IN),
.RXRESET(RXRESET_IN),
.RXUSRCLK(RXUSRCLK_IN),
.RXUSRCLK2(RXUSRCLK2_IN),
.TXBYPASS8B10B(VCC_BUS_4[3:0]),
.TXCHARDISPMODE({TXCHARDISPMODE_GND[1:0],
TXDATA_IN[19:19], TXDATA_IN[9:9]}),
.TXCHARDISPVAL({TXCHARDISPVAL_GND[1:0],
TXDATA_IN[18:18], TXDATA_IN[8:8]}),
.TXCHARISK(GND_BUS_4[3:0]),
.TXDATA({TXDATA_GND[15:0],
TXDATA_IN[17:10],
TXDATA_IN[7:0]}),
.TXFORCECRCERR(GND_BIT),
.TXINHIBIT(TXINHIBIT_IN),
.TXPOLARITY(TXPOLARITY_IN),
.TXRESET(TXRESET_IN),
.TXUSRCLK(TXUSRCLK_IN),
.TXUSRCLK2(TXUSRCLK2_IN),
.CHBONDDONE(),
.CHBONDO(),
.CONFIGOUT(),
.RXBUFSTATUS(RXBUFSTATUS_OUT[1:0]),
.RXCHARISCOMMA(),
.RXCHARISK({RXCHARISK_float[1:0],
RXDATA_OUT[19:19], RXDATA_OUT[9:9]}),
.RXCHECKINGCRC(),
.RXCLKCORCNT(rx_status),
.RXCOMMADET(),
.RXCRCERR(),
.RXDATA({RXDATA_float[15:0],
RXDATA_OUT[17:10],
RXDATA_OUT[7:0]}),
.RXDISPERR(),
.RXLOSSOFSYNC(),
.RXNOTINTABLE(),
.RXREALIGN(),
.RXRECCLK(RXRECCLK_OUT),
.RXRUNDISP({RXRUNDISP_float[1:0],
RXDATA_OUT[18:18], RXDATA_OUT[8:8]}),
.TXBUFERR(TXBUFERR_OUT),
.TXKERR(),
.TXN(TXN_OUT),
.TXP(TXP_OUT),
.TXRUNDISP());
defparam GT_CUSTOM_INST.ALIGN_COMMA_MSB = "FALSE";
defparam GT_CUSTOM_INST.CHAN_BOND_LIMIT = 16;
defparam GT_CUSTOM_INST.CHAN_BOND_MODE = "OFF";
defparam GT_CUSTOM_INST.CHAN_BOND_OFFSET = 8;
defparam GT_CUSTOM_INST.CHAN_BOND_ONE_SHOT = "FALSE";
defparam GT_CUSTOM_INST.CHAN_BOND_SEQ_1_1 = 11'b00000000000;
defparam GT_CUSTOM_INST.CHAN_BOND_SEQ_1_2 = 11'b00000000000;
defparam GT_CUSTOM_INST.CHAN_BOND_SEQ_1_3 = 11'b00000000000;
defparam GT_CUSTOM_INST.CHAN_BOND_SEQ_1_4 = 11'b00000000000;
defparam GT_CUSTOM_INST.CHAN_BOND_SEQ_2_1 = 11'b00000000000;
defparam GT_CUSTOM_INST.CHAN_BOND_SEQ_2_2 = 11'b00000000000;
defparam GT_CUSTOM_INST.CHAN_BOND_SEQ_2_3 = 11'b00000000000;
defparam GT_CUSTOM_INST.CHAN_BOND_SEQ_2_4 = 11'b00000000000;
defparam GT_CUSTOM_INST.CHAN_BOND_SEQ_2_USE = "FALSE";
defparam GT_CUSTOM_INST.CHAN_BOND_SEQ_LEN = 1;
defparam GT_CUSTOM_INST.CHAN_BOND_WAIT = 8;
defparam GT_CUSTOM_INST.CLK_CORRECT_USE = "FALSE";
defparam GT_CUSTOM_INST.CLK_COR_INSERT_IDLE_FLAG = "FALSE";
defparam GT_CUSTOM_INST.CLK_COR_KEEP_IDLE = "FALSE";
defparam GT_CUSTOM_INST.CLK_COR_REPEAT_WAIT = 1;
defparam GT_CUSTOM_INST.CLK_COR_SEQ_1_1 = 11'b00000000000;
defparam GT_CUSTOM_INST.CLK_COR_SEQ_1_2 = 11'b00000000000;
defparam GT_CUSTOM_INST.CLK_COR_SEQ_1_3 = 11'b00000000000;
defparam GT_CUSTOM_INST.CLK_COR_SEQ_1_4 = 11'b00000000000;
defparam GT_CUSTOM_INST.CLK_COR_SEQ_2_1 = 11'b00000000000;
defparam GT_CUSTOM_INST.CLK_COR_SEQ_2_2 = 11'b00000000000;
defparam GT_CUSTOM_INST.CLK_COR_SEQ_2_3 = 11'b00000000000;
defparam GT_CUSTOM_INST.CLK_COR_SEQ_2_4 = 11'b00000000000;
defparam GT_CUSTOM_INST.CLK_COR_SEQ_2_USE = "FALSE";
defparam GT_CUSTOM_INST.CLK_COR_SEQ_LEN = 1;
defparam GT_CUSTOM_INST.COMMA_10B_MASK = 10'b0000000000;
defparam GT_CUSTOM_INST.CRC_END_OF_PKT = "K29_7";
defparam GT_CUSTOM_INST.CRC_FORMAT = "USER_MODE";
defparam GT_CUSTOM_INST.CRC_START_OF_PKT = "K27_7";
defparam GT_CUSTOM_INST.DEC_MCOMMA_DETECT = "FALSE";
defparam GT_CUSTOM_INST.DEC_PCOMMA_DETECT = "FALSE";
defparam GT_CUSTOM_INST.DEC_VALID_COMMA_ONLY = "TRUE";
defparam GT_CUSTOM_INST.MCOMMA_10B_VALUE = 10'b1100000000;
defparam GT_CUSTOM_INST.MCOMMA_DETECT = "FALSE";
defparam GT_CUSTOM_INST.PCOMMA_10B_VALUE = 10'b0011111000;
defparam GT_CUSTOM_INST.PCOMMA_DETECT = "FALSE";
defparam GT_CUSTOM_INST.RX_BUFFER_USE = "TRUE";
defparam GT_CUSTOM_INST.RX_CRC_USE = "FALSE";
defparam GT_CUSTOM_INST.RX_DATA_WIDTH = 2;
defparam GT_CUSTOM_INST.RX_DECODE_USE = "FALSE";
defparam GT_CUSTOM_INST.RX_LOSS_OF_SYNC_FSM = "FALSE";
defparam GT_CUSTOM_INST.RX_LOS_INVALID_INCR = 1;
defparam GT_CUSTOM_INST.RX_LOS_THRESHOLD = 4;
defparam GT_CUSTOM_INST.TERMINATION_IMP = 50;
defparam GT_CUSTOM_INST.SERDES_10B = "FALSE";
defparam GT_CUSTOM_INST.TX_BUFFER_USE = "TRUE";
defparam GT_CUSTOM_INST.TX_CRC_FORCE_VALUE = 8'b11010110;
defparam GT_CUSTOM_INST.TX_CRC_USE = "FALSE";
defparam GT_CUSTOM_INST.TX_DATA_WIDTH = 2;
defparam GT_CUSTOM_INST.TX_DIFF_CTRL = 500;
defparam GT_CUSTOM_INST.TX_PREEMPHASIS = 0;
defparam GT_CUSTOM_INST.REF_CLK_V_SEL = 1;
endmodule
Article: 127324<snip /> > >My problem was solved by using the package >IEEE.std_logic_unsigned.ALL; and I used the function conv_integer >which directly converts the std_logic_vector to integer. In this case >i do not have to convert the vector to unsigned. > >Thank you all for your help > >Anuja > If you ever go on a VHDL course, I am sure that you will be told that use of the 'std_logic_arith', 'std_logic_signed', 'std_logic_unsigned' packages is DEPRECATED, and that you should only use the IEEE Standard 1076.3-1997 'numeric_std' (or 'numeric_bit' if not using 9-level logic) package. I strongly advise you to get into this good habit now.
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