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Messages from 127075

Article: 127075
Subject: Re: Different synthesis report between ISE-xst and EDK-xst
From: SvenA <sven.artz@gmx.de>
Date: Tue, 11 Dec 2007 04:15:19 -0800 (PST)
Links: << >>  << T >>  << A >>
I think I found the problem for the not running c-code.
After I generated a new linker script the c-code ran. The core is
working as well. I drove a 1Khz signal trough my to wired in- and
outputs.
It looks like I missunderstood the RTL-Schematic from ISE.

But there is still the Question whether ISE and EDK run XSt with
different parameters and why?


Regards

 Sven

Article: 127076
Subject: sobel in vhdl
From: rossalbi <rossalbi@hotmail.com>
Date: Tue, 11 Dec 2007 04:57:16 -0800 (PST)
Links: << >>  << T >>  << A >>


Hi people...

I am trying to find a vhdl code for 3x3 sobel algorithm to implement
on a Spartan 3, FPGA.

I have found many papers on the subject but they are all from a high
level of abstraction and none include any actual code.

Any help would be greatly appreciated.

Ross Albi

Article: 127077
Subject: Re: Net hierarchy with Xilinx 9.1
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Tue, 11 Dec 2007 13:51:42 +0000
Links: << >>  << T >>  << A >>
On Sat, 8 Dec 2007 14:04:18 -0800 (PST), Louis Dupont
<louis.dupont@gmail.com> wrote:

>Hi,
>
>I ran into a small problem while trying to use a UCF file created for
>ISE 8.2 within EDK 9.1. I had a few INSTs and NETs relatively deep
>within the design's hierarchy:
>
>INST "ioring/U_top/u_adc_clk_dcm" FACTORY_JF = "ABCD";
>NET "ioring/U_top/sdram_clk_sig" TNM = sdramclk;
>
>I get an error from Xilinx stating it can find neither the instance
>nor the net when trying to implement these constraints. Looking
>around, I found the solution for the INST using the syntax:
>
>INST "ioring/*U_top/* u_adc_clk_dcm" FACTORY_JF = "ABCD";
>
>But It didn't work for the net (sdram_clk_sig is a std_logic signal
>within the U_top instance). Anybody knows the correct syntax to access
>a net within such hierarchy with Xilinx 9.1?

No, but maybe you could generate the post-synthesis simulation model,
and search it to find the net name. 

If the net has been optimised away or combined with another functionally
equivalent one, searching for components connected to it should give you
the information you need.

- Brian

Article: 127078
Subject: Re: DDS generator with interpolated samples for Spartan3E development
From: John_H <newsgroup@johnhandwork.com>
Date: Tue, 11 Dec 2007 14:22:35 GMT
Links: << >>  << T >>  << A >>
chesi wrote:
> On 8 dic, 19:24, emeb <ebromba...@gmail.com> wrote:
>> A few suggestions:
>>
>> * Use a longer Sine lookup table instead of interpolation.
>> * Store only 1/4 cycle of the sinewave in the lookup table and use bit
>> operations on the address and output to map the 1/4 cycle onto the
>> full wave.
>> * Use a dual-port RAM for the lookup table to simultaneously generate
>> sine & cosine (useful for digital radio applications)
>>
>> Inverse sinc filters are common ways to equalize the spectral droop
>> caused by the zero-order hold nature of the DAC. Typically a simple
>> FIR filter with a few taps (<10) can 'lift' the high frequency
>> response of the signal to compensate for this rolloff. This page
>> describes one way to do it:
>>
>> http://www.maxim-ic.com/appnotes.cfm/an_pk/3853
>> EB
> 
> An additional suggestion to what Emeb has said...
> Instead of directly storing the sine samples in the lookup table you
> may store the difference between the sine function and y=x function.
> You'll save some bits in your table.
> 
> CÚsar


But is a "real" phase value desired (pi/2=90 degrees) or a normalized 
ROM-address phase value where 2^n=90 degrees?

Article: 127079
Subject: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
From: axalay <axalay@gmail.com>
Date: Tue, 11 Dec 2007 07:11:44 -0800 (PST)
Links: << >>  << T >>  << A >>
Thanks!
I solve this problem

Article: 127080
Subject: Re: sobel in vhdl
From: "RCIngham" <robert.ingham@gmail.com>
Date: Tue, 11 Dec 2007 10:05:42 -0600
Links: << >>  << T >>  << A >>
>
>
>Hi people...
>
>I am trying to find a vhdl code for 3x3 sobel algorithm to implement
>on a Spartan 3, FPGA.
>
Ever thought of writing it yourself? As a hint, do the x2 as a left
shift.

HTH!


Article: 127081
Subject: Re: keep_hierarchy attribute equivalent for Lattice/Synplicity?
From: "theosib@gmail.com" <theosib@gmail.com>
Date: Tue, 11 Dec 2007 08:22:11 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 10, 5:13 pm, John_H <newsgr...@johnhandwork.com> wrote:

> The equivalent_register_removal = "no" sounds like syn_preserve = 1.
> I haven't used XST myself, so I'm guessing by the names.  Two
> identical flops won't be optimized to one, constant registers aren't
> removed, and register retiming won't affect registers where
> syn_preserve=1.

Thanks again for the help.  What I'm finding seems to suggest that the
synthesis attribute should be on the same line as the net or reg it's
referring to.  How do you apply more than one attribute to the same
object?  Like syn_preserve=1 and syn_maxfan=1 to the same register?

Thanks.

Article: 127082
Subject: Re: Xilinx ise 9.2i clean up project files
From: Gabor <gabor@alacron.com>
Date: Tue, 11 Dec 2007 08:41:19 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 11, 1:22 am, Daniel O'Connor <dar...@dons.net.au> wrote:
> Gabor wrote:
> > The other workaround I found was to just start a new project and
> > include all of my sources from the broken one.  That is a real
> > pain, though.
>
> When I was experimenting I found ISE would eat my project or hang eating all
> the CPU if I wasn't very careful (with 8.2) and I also wanted to swap
> between architectures. Furthermore the .ise file is not suitable for
> version control... I did some research and found there is a tool you
> can use to recreate the ISE file from a plain text file (you lose some
> info but it is very usable)
>
> Create the file foo.npl with the following contents..
> # Create the project
> NewProject(foo.ise)
>
> # Set basic properties
> SetProperty(Device Family, spartan3)
> SetProperty(Device, xc3s400)
> SetProperty(Package, tq144)
> SetProperty(Speed Grade, -4)
> SetProperty(Top-Level Module Type, HDL)
>
> # Add the sources
> AddSource(foo.v, Verilog Design File)
> AddSource(foo.ucf, SA)
> AddSource(abc.xco, Coregen Design File)
>
> # Test bench sources
> AddSource(foo_test.v, Verilog Design File)
>
> # This doesn't actually work..
> SetProperty(Simulation Run Time, 5000 ns, foo_test_v, Simulate Post-Place & Route Model, 9, SA)
>
> # Close the project to tidy up
> CloseProject()
>
> Then run
> pjcli -f foo.npl
>
> I've tested this on FreeBSD (linux emulation) & Windows with ISE8.2.
>
> Hope it helps.
>
> --
> Daniel O'Connor software and network engineer
> for Genesis Software -http://www.gsoft.com.au
> "The nice thing about standards is that there
> are so many of them to choose from."
>   -- Andrew Tanenbaum
> GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C

If you have an older version of ISE (6.x works) you can generate the
.npl file from the GUI.  One thing I found out about ISE 8.x and
later is that if you "upgrade" a project from 6.x to 8.x, your .npl
file gets trashed in the process (I guess they really don't want
you keeping a project setup in clear text).  So it's a good idea to
back up the .npl file first.

Article: 127083
Subject: Re: keep_hierarchy attribute equivalent for Lattice/Synplicity?
From: John_H <newsgroup@johnhandwork.com>
Date: Tue, 11 Dec 2007 08:48:35 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 11, 8:22 am, "theo...@gmail.com" <theo...@gmail.com> wrote:
>
> Thanks again for the help.  What I'm finding seems to suggest that the
> synthesis attribute should be on the same line as the net or reg it's
> referring to.  How do you apply more than one attribute to the same
> object?  Like syn_preserve=1 and syn_maxfan=1 to the same register?
>
> Thanks.

I thought I'd learned how to do multiple attributes from the Synplify
help as well.  Part of your answer may depend on whether you're
Verilog or VHDL.  In my Verilog use, I'll either have two attributes
in the new format preceeding the object (where I think the comma is
used and no "synthesis" keyword is needed)

(* syn_preserve=1
 , syn_useioff=1 *) reg myTristateCtrl;

but I've always found it easy (from getting the attributes to stick)
to use the inline comment before the object close (there is no comma
between attributes):

wire myBigDistribution /* synthesis syn_keep=1 syn_maxfan=20 */;

If you want to make an attribute global for a module and its
submodules, you can attach the primitive to the initial module
declaration.  Adding the /* synthesis xc_fast=1 */ before the closing
semicolon to the declaration list applies the attribute or directive
globally for that point in the hierarchy and down.

VHDL results may vary.

- John_H

Article: 127084
Subject: Re: PCI Parallel port card for JTAG / programming?
From: Peter Wallace <pcw@karpy.com>
Date: Tue, 11 Dec 2007 08:57:27 -0800
Links: << >>  << T >>  << A >>
On Mon, 10 Dec 2007 16:31:44 -0800, ee_ether wrote:

> Hi,
> 
> I need a PCI parallel port card since the new PC is "legacy free".  I
> use parallel port based JTAG debuggers and programmers for micros
> (AVRs), CPLDs (Xilinx/Altera/Lattice) and FPGAs (Xilinx/Altera).
> 
> Which PCI parallel cards work or don't work for you?  Tried it under
> Linux?
> 
> Seems like most PCI parallel cards are based on chipsets from Netmos --
> any luck with these?
> 
> Thanks.
 
I have a NetMos parallel card and it works fine (at least for Xilinx
Parallel cable III JTAG)


Peter Wallace

Article: 127085
Subject: Chipscope 7.1 and JTAG TAP
From: Paul <Paul@yahoo.co.uk>
Date: Tue, 11 Dec 2007 17:03:24 +0000
Links: << >>  << T >>  << A >>
Hi

I am using Chipscope 7.1 and I have a VirtexII xc2V6000 with a 
Instruction width of 6 bits. I have a design for which I had 
automatically generated a JTAG Controller. I can successfully sythesize 
the design as well as the JTAG TAP. The problem is just that when I use 
ChipScope Pro with to connect to the device it tells me that there are 0
Core units found in the JTAG device chain.

I have the following options when generating the JTAG TAP Controller:

Instruction Register Bid Width: 6  (this is what Chipscope pro tells me)
Version Number: 0
Pert Number: 	0
Manufacturer:	0
TDI Signal name: tdi
TDO Signal name: tdo
TMS Signal name: tms
TCK Signal name: tck
TRST Signal name: trst_n

I dont think that Version number, Part Number and Manufacturer are 
critical, right? Anyone an idea what I could have been missing?
Probably something obvious when running the synthesis with Xilinx XST?

Many thanks for helpful tips!
Paul

Article: 127086
Subject: Craignell and Darnaw1 Website Updates
From: John Adair <g1@enterpoint.co.uk>
Date: Tue, 11 Dec 2007 10:06:54 -0800 (PST)
Links: << >>  << T >>  << A >>
Pictures of the new issue PGA Darnaw1 on our website
http://www.enterpoint.co.uk/moelbryn/darnaw1.html. Main difference is
the more standard 2x7 2mm JTAG and Serial Flash programming headers
allowing our Prog2 cable and the Xilinx cables to be used directly
with this module.

Pictures of the new version Craignells now on the site
http://www.enterpoint.co.uk/component_replacements/craignell.html. You
will see how much we have crushed these modules down and now are apart
for the DIL Header all components are now on a single side to improve
our manufacturing process. We are testing these now but probably won't
let them out on the shop website until the new programming header
adaptor is available to make connection to the 1.27mm programming
header a bit easier. This adaptor is expected to be available mid-
January.

John Adair
Enterpoint Ltd.



Article: 127087
Subject: Re: Craignell and Darnaw1 Website Updates
From: John_H <newsgroup@johnhandwork.com>
Date: Tue, 11 Dec 2007 10:27:52 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 11, 10:06 am, John Adair <g...@enterpoint.co.uk> wrote:
> Pictures of the new issue PGA Darnaw1 on our websitehttp://www.enterpoint.co.uk/moelbryn/darnaw1.html. Main difference is
> the more standard 2x7 2mm JTAG and Serial Flash programming headers
> allowing our Prog2 cable and the Xilinx cables to be used directly
> with this module.
>
> Pictures of the new version Craignells now on the sitehttp://www.enterpoint.co.uk/component_replacements/craignell.html. You
> will see how much we have crushed these modules down and now are apart
> for the DIL Header all components are now on a single side to improve
> our manufacturing process. We are testing these now but probably won't
> let them out on the shop website until the new programming header
> adaptor is available to make connection to the 1.27mm programming
> header a bit easier. This adaptor is expected to be available mid-
> January.
>
> John Adair
> Enterpoint Ltd.

I sincerely appreciate the size reference in the Craignell
photograph.  If only I knew what the size of that coin was!  Maybe a
few pieces of currency from around the globe would help, looking at
your customer base for ideas.  I found it funny that photos with a
size reference from asian countries often used a pack of cigarettes;
while somewhat universal, fewer people smoke these days.

- John_H

Article: 127088
Subject: Re: Craignell and Darnaw1 Website Updates
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Wed, 12 Dec 2007 09:09:33 +1300
Links: << >>  << T >>  << A >>
John_H wrote:
> On Dec 11, 10:06 am, John Adair <g...@enterpoint.co.uk> wrote:
> 
>>Pictures of the new issue PGA Darnaw1 on our websitehttp://www.enterpoint.co.uk/moelbryn/darnaw1.html. Main difference is
>>the more standard 2x7 2mm JTAG and Serial Flash programming headers
>>allowing our Prog2 cable and the Xilinx cables to be used directly
>>with this module.
>>
>>Pictures of the new version Craignells now on the sitehttp://www.enterpoint.co.uk/component_replacements/craignell.html. You
>>will see how much we have crushed these modules down and now are apart
>>for the DIL Header all components are now on a single side to improve
>>our manufacturing process. We are testing these now but probably won't
>>let them out on the shop website until the new programming header
>>adaptor is available to make connection to the 1.27mm programming
>>header a bit easier. This adaptor is expected to be available mid-
>>January.
>>
>>John Adair
>>Enterpoint Ltd.
> 
> 
> I sincerely appreciate the size reference in the Craignell
> photograph.  If only I knew what the size of that coin was!  Maybe a
> few pieces of currency from around the globe would help, looking at
> your customer base for ideas.  I found it funny that photos with a
> size reference from asian countries often used a pack of cigarettes;
> while somewhat universal, fewer people smoke these days.

What about some sort of stick, with notches cut in it, maybe based on
someone's thumb-width, or elbow-finger length ? ;)

Or you could leap a couple of millenia, and google
"International System of Units length" just for fun, to see what happens.

Or, since these boards have 'ancient' derivative names, perhaps
length could be given in an associated history/engineering combination 
of pico-furlongs ?

-jg




Article: 127089
Subject: Re: Craignell and Darnaw1 Website Updates
From: John_H <newsgroup@johnhandwork.com>
Date: Tue, 11 Dec 2007 12:25:30 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 11, 12:09 pm, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> John_H wrote:
> > On Dec 11, 10:06 am, John Adair <g...@enterpoint.co.uk> wrote:
>
> >>Pictures of the new issue PGA Darnaw1 on our websitehttp://www.enterpoint.co.uk/moelbryn/darnaw1.html. Main difference is
> >>the more standard 2x7 2mm JTAG and Serial Flash programming headers
> >>allowing our Prog2 cable and the Xilinx cables to be used directly
> >>with this module.
>
> >>Pictures of the new version Craignells now on the sitehttp://www.enterpoint.co.uk/component_replacements/craignell.html. You
> >>will see how much we have crushed these modules down and now are apart
> >>for the DIL Header all components are now on a single side to improve
> >>our manufacturing process. We are testing these now but probably won't
> >>let them out on the shop website until the new programming header
> >>adaptor is available to make connection to the 1.27mm programming
> >>header a bit easier. This adaptor is expected to be available mid-
> >>January.
>
> >>John Adair
> >>Enterpoint Ltd.
>
> > I sincerely appreciate the size reference in the Craignell
> > photograph.  If only I knew what the size of that coin was!  Maybe a
> > few pieces of currency from around the globe would help, looking at
> > your customer base for ideas.  I found it funny that photos with a
> > size reference from asian countries often used a pack of cigarettes;
> > while somewhat universal, fewer people smoke these days.
>
> What about some sort of stick, with notches cut in it, maybe based on
> someone's thumb-width, or elbow-finger length ? ;)
>
> Or you could leap a couple of millenia, and google
> "International System of Units length" just for fun, to see what happens.
>
> Or, since these boards have 'ancient' derivative names, perhaps
> length could be given in an associated history/engineering combination
> of pico-furlongs ?
>
> -jg- Hide quoted text -
>
> - Show quoted text -

http://www.google.com/search?hl=en&q=convert+2+inches+to+light-seconds

169 pico-light-seconds?

The acient units could be appropriate, but don't work well in a photo
unless you could use ancient engineering instruments which were always
the same size, perhaps a sextant or a slide rule?

Article: 127090
Subject: Re: Craignell and Darnaw1 Website Updates
From: John Adair <g1@enterpoint.co.uk>
Date: Tue, 11 Dec 2007 12:56:18 -0800 (PST)
Links: << >>  << T >>  << A >>
John

Coin diameter is 25.11mm, call it an inch for imperial synplicity.

John Adair
Enterpoint Ltd.

On 11 Dec, 18:27, John_H <newsgr...@johnhandwork.com> wrote:
> On Dec 11, 10:06 am, John Adair <g...@enterpoint.co.uk> wrote:
>
>
>
>
>
> > Pictures of the new issue PGA Darnaw1 on our websitehttp://www.enterpoint.co.uk/moelbryn/darnaw1.html. Main difference is
> > the more standard 2x7 2mm JTAG and Serial Flash programming headers
> > allowing our Prog2 cable and the Xilinx cables to be used directly
> > with this module.
>
> > Pictures of the new version Craignells now on the sitehttp://www.enterpoint.co.uk/component_replacements/craignell.html. You
> > will see how much we have crushed these modules down and now are apart
> > for the DIL Header all components are now on a single side to improve
> > our manufacturing process. We are testing these now but probably won't
> > let them out on the shop website until the new programming header
> > adaptor is available to make connection to the 1.27mm programming
> > header a bit easier. This adaptor is expected to be available mid-
> > January.
>
> > John Adair
> > Enterpoint Ltd.
>
> I sincerely appreciate the size reference in the Craignell
> photograph.  If only I knew what the size of that coin was!  Maybe a
> few pieces of currency from around the globe would help, looking at
> your customer base for ideas.  I found it funny that photos with a
> size reference from asian countries often used a pack of cigarettes;
> while somewhat universal, fewer people smoke these days.
>
> - John_H- Hide quoted text -
>
> - Show quoted text -


Article: 127091
Subject: Re: PCI Parallel port card for JTAG / programming?
From: Anton Erasmus <nobody@spam.prevent.net>
Date: Tue, 11 Dec 2007 23:04:55 +0200
Links: << >>  << T >>  << A >>
On Tue, 11 Dec 2007 08:57:27 -0800, Peter Wallace <pcw@karpy.com>
wrote:

>On Mon, 10 Dec 2007 16:31:44 -0800, ee_ether wrote:
>
>> Hi,
>> 
>> I need a PCI parallel port card since the new PC is "legacy free".  I
>> use parallel port based JTAG debuggers and programmers for micros
>> (AVRs), CPLDs (Xilinx/Altera/Lattice) and FPGAs (Xilinx/Altera).
>> 
>> Which PCI parallel cards work or don't work for you?  Tried it under
>> Linux?
>> 
>> Seems like most PCI parallel cards are based on chipsets from Netmos --
>> any luck with these?
>> 
>> Thanks.
> 
>I have a NetMos parallel card and it works fine (at least for Xilinx
>Parallel cable III JTAG)

http://www.sunix.com.tw has a few cards that can be mapped to legacy
ports. These work without problems once mapped to the legacy ports.

Regards
  Anton Erasmus

Article: 127092
Subject: Re: Chipscope 7.1 and JTAG TAP
From: PatC <pato@patocarr.com>
Date: Tue, 11 Dec 2007 14:32:01 -0800
Links: << >>  << T >>  << A >>
Paul wrote:
> Hi
> 
> I am using Chipscope 7.1 and I have a VirtexII xc2V6000 with a
> Instruction width of 6 bits. I have a design for which I had
> automatically generated a JTAG Controller. I can successfully sythesize
> the design as well as the JTAG TAP. The problem is just that when I use
> ChipScope Pro with to connect to the device it tells me that there are 0
> Core units found in the JTAG device chain.
> 
> I have the following options when generating the JTAG TAP Controller:
> 
> Instruction Register Bid Width: 6  (this is what Chipscope pro tells me)
> Version Number: 0
> Pert Number:     0
> Manufacturer:    0
> TDI Signal name: tdi
> TDO Signal name: tdo
> TMS Signal name: tms
> TCK Signal name: tck
> TRST Signal name: trst_n
> 
> I dont think that Version number, Part Number and Manufacturer are
> critical, right? Anyone an idea what I could have been missing?
> Probably something obvious when running the synthesis with Xilinx XST?
> 
> Many thanks for helpful tips!
> Paul

Hi,

  In order to debug the basic connectivity, I would insert or
instantiate a ICON/ILA or ICON/VIO and see how that works.

  I've seen that 0 cores found problem when the generated core is newer
than the Chipscope version.

  Also, the trst_n shown is active low, is that intended for the TAP
controller?

HTH,
-P@

Article: 127093
Subject: Re: Xilinx : Incorrect PACE file generation from schematic
From: PatC <pato@patocarr.com>
Date: Tue, 11 Dec 2007 14:35:51 -0800
Links: << >>  << T >>  << A >>
Joseph wrote:
> Hi all,
> 
> I am using Xilinx 9.2i schematic entry to design a simple clock
> circuit. The schematic uses come components that i wrote and i have
> added a counter from xilinx library. WHen i implement the design and
> fit it is ok, but when i assign package pins using PACE, i only see
> the inputs/outputs of the counter and not of the whole design.

Joseph, please make sure you're compiling the top level and not just the
actual counter. This can happen if you have selected the counter file
(ie. xco) and hit the implement button. Check the *.xst logs to see
what's xst taking as a top level.

HTH,
-P@

Article: 127094
Subject: Re: GAL16V8
From: mikeandmax@aol.com
Date: Tue, 11 Dec 2007 14:41:02 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 10, 4:40 pm, "Martin Charlwood" <martincharlw...@hotmail.com>
wrote:
> Hello,
> I have a simple project in mind and have some GAL16V8 PLD's knocking around,
> could anyone suggest a design suite that still supports these devices along
> with an associated url.
>
> Many Thanks.
> Martin Charlwood

Lattice still makes the devices, and its ispLEVER Classic tools are
free d/l from the www.latticesemi.com website.  Includes ABEL, and
with Synplicity and Precision RTL included, will support VHDL or
Verilog as well.  here's the link -

http://www.latticesemi.com/products/designsoftware/isplever/ispleverclassic/index.cfm

have fun!
 Mike Thomas
Lattice FAE NY/NJ

Article: 127095
Subject: Re: Craignell and Darnaw1 Website Updates
From: ghelbig@lycos.com
Date: Tue, 11 Dec 2007 14:50:12 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 11, 12:56 pm, John Adair <g...@enterpoint.co.uk> wrote:
> John
>
> Coin diameter is 25.11mm, call it an inch for imperial synplicity.
>
> John Adair
> Enterpoint Ltd.
>


Whitworth Standard coin size?

G.

Article: 127096
Subject: Re: Craignell and Darnaw1 Website Updates
From: John_H <newsgroup@johnhandwork.com>
Date: Tue, 11 Dec 2007 16:10:36 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 11, 12:56 pm, John Adair <g...@enterpoint.co.uk> wrote:
> John
>
> Coin diameter is 25.11mm, call it an inch for imperial synplicity.
>
> John Adair
> Enterpoint Ltd.

I thought Synplicity was an american firm with some R&D and support in
India.  It's imperial?  Hmmm....  Maybe I'm over-simplifying.

Thanks for the reference.

- John

Article: 127097
Subject: Re: DDS generator with interpolated samples for Spartan3E development
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Tue, 11 Dec 2007 17:12:26 -0700
Links: << >>  << T >>  << A >>
Frank Buss wrote:
> Kevin Neilson wrote:
> 
>>   So then with little hardware you can make a first-order Taylor, and 
>> with a bit more you could even make a second-order, although rarely is 
>> this necessary.  I'll send you a Xilinx paper that explains this.  It's 
>> by Chris Dick and Fred Harris and called "Direct Digital Syhthesis - 
>> Some Options for FPGA Implementation".
> 
> Thanks, the Error Feed-Forward DDS looks interesting. But it is patented:
> 
> http://www.google.com/patents?id=AAkIAAAAEBAJ&dq=6333649
> 
> This is no problem for me, because in Germany you can't patent algorithms
> and formulaes (at least this is what I know, hope they didn't change it),
> but would be nice to have a free algorithm, because I plan to publish it on
> my website, so everyone can use and build it for whatever they want,
> without the danger of maybe paying licence costs to Xilinx.
> 
Interessant--I didn't know Chris had the patent on that.  And in this 
millenium, no less!  It's basically a truncated Maclaurin 
series--probably similar to the way Babbage cranked out sine tables on 
his Difference Engine.  But it is a great idea, and witty because you 
get the derivatives for free, and apparently no one had used it in a DDS 
before.  You can still get this feature if you use the Xilinx CoreGen 
DDS core.  (Vielleicht ist das Patent nicht gueltig, wenn ein 2nd-Order 
Polynom verwendet wird!)
-Kevin

Article: 127098
Subject: Re: DDS generator with interpolated samples for Spartan3E development
From: Brian Davis <brimdavis@aol.com>
Date: Tue, 11 Dec 2007 18:24:38 -0800 (PST)
Links: << >>  << T >>  << A >>
Kevin Neilson wrote:
>
> It's basically a truncated Maclaurin series--probably similar to the
> way Babbage cranked out sine tables on his Difference Engine.  But
> it is a great idea, and witty because you get the derivatives for free,
> and apparently no one had used it in a DDS before.
>
 For high precision sinusoids in FPGA's with multipliers,
I'd try dusting off the technique from the vintage 1970
Tierney/Rader/Gold paper [Ref 1] and doing something like :

 - Upper two{three} phase bits used for quadrant{octant} folding

 - next N phase bits look up a 'coarse' IQ value
  ( coarse phase index, yet precise amplitude )

 - next M phase bits look up a 'fine' IQ value
  ( residual rotation )

 - complex multiply rotates coarse IQ by fine IQ

Figure six of their paper has a nice graphical summary of
the technique.

 The beauty of this scheme is that it is an exact computation,
not an approximation; I haven't worked out the error terms for
18x18 or 36x36 multipliers, but I'd expect you could easily
do a computation to twenty-something bits of precision with two
comfortably-fit-in-BRAM sized lookup tables and one complex multiply.

 Their actual implementation with 1970-era TTL took some shortcuts
to conserve hardware, e.g. approximate the fine cosine values as ~1.0

 [Ref 2] is a great DDS reference that reprints that early paper,
along with summaries of other sine computation methods [Ref 3, Ref 4]

Brian

[Ref 1] "A Digital Frequency Synthesizer", Tierney/Rader/Gold,
        IEEE Transactions on Audio and Electroacoustics, March 1971

[Ref 2] "Direct Digital Frequency Synthesizers, Kroupa (ed)
        IEEE Press, 1996

[Ref 3] "The Optimization of Direct Digital Frequency Synthesizer
         Performance in the Presence of Finite Word Length Effects"
         Nicholas/Samueli/Kim,
         Proceedings of the 42nd Annual Frequency Control Symposium,
1988

[Ref 4] "Methods of Mapping from Phase to Sine Amplitude in
         Direct Digital Synthesis", Vankka
         IEEE Transactions on Ultrasonics, Ferroelectrics,
         and Frequency Control, March 1997



Article: 127099
Subject: Re: Xilinx ise 9.2i clean up project files
From: Tim P <timmy4three@gmail.com>
Date: Tue, 11 Dec 2007 19:16:35 -0800 (PST)
Links: << >>  << T >>  << A >>
How about if cleaning up project files does not help?

I would like to avoid recreating the project due to the size of the
schematic to be redrawn.  I have the same symptoms as mentioned in the
first post, except cleaning project files does not solve the problem.
However, when opening the ".ucf" file for my project, Xilinx ISE goes
through a "synthesis" before that file can be opened.  This backdoor
synthesis runs fine, but not by activating the synthesize, implement,
or generate prog. file options...

Any thoughts?



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