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Messages from 102625

Article: 102625
Subject: Clocking ZBT RAM via DCM on ML40x board
From: Tomasz Dziecielewski <tomdz@NOSPAMmultimedia.edu.pl>
Date: Thu, 18 May 2006 11:41:15 +0200
Links: << >>  << T >>  << A >>
Hello,

I'm trying to use a DCM to deskew the memory clock but find it hard
to learn which pads should be used to create the clock feedback loop.
In the board's (ML402) schematic there is the SRAM_CLK (Feedback) 
pad (AD17) which, as I reckon, is used to drive the clock signal out
of the FPGA (pls correct me if I'm wrong with this one). But which pad
brings the signal back and closes the loop?

Thanks in advance. Regards,
Tomasz Dziecielewski

Article: 102626
Subject: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
From: Andreas Ehliar <ehliar@lysator.liu.se>
Date: Thu, 18 May 2006 09:49:03 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2006-05-17, Ed McGettigan <ed.mcgettigan@xilinx.com> wrote:
> Laurent Pinchart wrote:
>> That's not the only issue. The main problem is that the Jungo driver is a
>> security hole by design: it gives applications access to PCI cards from
>> user space without any security check, making it possible for any user to
>> read from and write to any memory location. The people who designed such a
>> piece of crap should be banned from using computers for the rest of their
>> life.
>
> Can you please cite a reference that documents this issue in detail? And
> as I originally requested is there any known exploit that takes advantage
> of this, again I need a cite.   I looked and I can't find anything other
> than comments that are 4+ years old at this time.

At first I thought that I could take a shot at this, download the WinDriver
SDK and see if I could quickly figure out how the WinDriver API works.
However, I didn't have to do that since they have some nice sample programs
included in the WinDriver distribution:

-----------------------------------------------------------------------------

(This is all run as my normal user, not as root user.)

> cd WinDriver/util
> ls
files.txt  isapnp_scan  pci_diag  pci_dump  pci_scan  usb_diag  wddebug  wddebug_gui  wdreg
> ./pci_diag

PCI diagnostic utility.
Application accesses hardware using WinDriver
and a Kernel PlugIn driver (KP_PCI).

PCI main menu
--------------
1. Scan PCI bus
2. Find and open a PCI device
99. Exit
Enter option: 2
Enter vendor ID (to cancel press 'x'): 0x1002
Enter device ID (to cancel press 'x'): 0x5960

Found 1 matching device [ Vendor ID 0x1002, Device ID 0x5960 ]:

 1. Vendor ID: 0x1002, Device ID: 0x5960
    Location: Bus 0x1, Slot 0x0, Function 0x0
    Memory range [BAR 0]: base 0xE8000000, size 0x8000000
    I/O range [BAR 1]: base 0x2000, size 0x100
    Memory range [BAR 2]: base 0xF8400000, size 0x10000
    Interrupt: IRQ 10


PCI main menu
--------------
1. Scan PCI bus
2. Find and open a PCI device
3. Read/write memory and IO addresses on the device
4. Read/write the PCI configuration space
5. Enable/disable the device's interrupts
6. Register/unregister plug-and-play and power management events
99. Exit
Enter option: 3

Read/write the device's memory and IO ranges
---------------------------------------------
1. Change active address space for read/write (currently: BAR 0)
2. Change active read/write mode (currently: 32 bit)
3. Toggle active transfer type (currently: non-block transfers)
4. Read from active address space
5. Write to active address space
99. Exit menu

Enter option: 5
Enter offset to write to (to cancel press 'x'): 0x0
Enter data to write (max value: 0xFFFFFFFF) or 'x' to cancel: 0xffffffff
Wrote 0xFFFFFFFF to offset 0x0 in BAR 0

-----------------------------------------------------------------------------


At this point my upper left pixel turned white. I also managed to crash the PCI
bus (and the computer of course) by playing around with this program and reading
from the wrong address...

It seems that there are some ways around this according to comments posted at
http://freshmeat.net/projects/windriver/, but I'm not sure how you would go about
implementing that.

I wonder if the same problem will appear on the Windows version of WinDriver?
I don't really have time to test it myself at the moment though.

(And yes, I also think it would be much nicer if the Xilinx tools did not depend
on 3rd party kernel modules if it could be avoided.)

/Andreas

Article: 102627
Subject: Re: SystemACE bootloader for PowerPC on Virtex4 FX
From: "Jon Beniston" <jon@beniston.com>
Date: 18 May 2006 02:59:10 -0700
Links: << >>  << T >>  << A >>
Ah, if you has said search for dosfs by Lewin Edwards, I'm sure I would
have got it. Thanks anyway!

Compiling all of dosfs for PowerPC seems to be about 8kB. To read a
file using the systemace drivers comes to a total of about 10kB.So
quite a nice saving. Thanks.

Cheers,
Jon


Article: 102628
Subject: Re: SystemACE bootloader for PowerPC on Virtex4 FX
From: "Jon Beniston" <jon@beniston.com>
Date: 18 May 2006 03:01:24 -0700
Links: << >>  << T >>  << A >>
I only have one application to load, it is just too big for on-chip
memory, so it has to be loaded into external SDRAM.

Cheers,
Jon


Article: 102629
Subject: Re: SystemACE bootloader for PowerPC on Virtex4 FX
From: "Antti" <Antti.Lukats@xilant.com>
Date: 18 May 2006 03:39:02 -0700
Links: << >>  << T >>  << A >>
Read what Peter Ryser said:

you can have ACE file that loads the FPGA and something very small sw.
this sw can trigger ACE config from config 4 as example, and the config
4 ACE file will contain a LARGE SW only ACE setup that loads the sw
into external memory.

this is all doable without having a custom bootloader to access the CF
over systemace MPI

its not very clear from sysace generic docu that it is doable, but well
it is possible!

I guess the ml403 docu possible explains this approuch,

Antti


Article: 102630
Subject: Re: ADC implementation on FPGA ?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 18 May 2006 22:58:14 +1200
Links: << >>  << T >>  << A >>
Scope wrote:
>>What's the speed ..?
> 
> 
> up to 100 Mhz.
> 
> 
>>Voltage levels ..?
> 
> 
> analog input signal is between -1V and 1V
> 
> 
>>Cost ..?
> 
> 
> cost is not a problem
> 
> 
>>Complexity ..?
> 
> 
> What do you want to say with the term "complexity" ?
> 
> 
> 
> I need to convert it to an 8 bits format.

Linearity ?   SFDR ?

The first figure was 16 bits ?
Perhaps this is homework ?

The killer in the ADC is that letter A = Analog.
You can do digital stuff in FPGA, but not analog.
You can use the FPGA to minimise the Analog, but it cannot
be removed entirely. SigmaDelta ADCs are one path, but not
for 100MHz sample rates...
  Sawtooth + Comparitor gives a low performance ADC, a long way
from 16 bits.
  8 bits then needs a time resolve of 39ps - you get the idea....

-jg


Article: 102631
Subject: Re: Superscalar Out-of-Order Processor on an FPGA
From: "alpha" <zhg.liu@gmail.com>
Date: 18 May 2006 04:17:08 -0700
Links: << >>  << T >>  << A >>
I designed a 2-way issue out-of-order processor recently.  It has 8
slot deep reorder buffers and 4 execute unites - 2 ALUs, 1 Branch and 1
L/S. Simple branch taken scheme.
It takes about 9000 LC(s) in a Xilinx V4 FX12 FPGA running 33 MHz with
1.2-1.5 IPC.

The major implementation issue is a 2W4R RF, I have to double clock the
write port.


Article: 102632
Subject: Re: Reality of V5 as ES
From: "Marc Randolph" <mrand@my-deja.com>
Date: 18 May 2006 05:24:20 -0700
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> Jan,
>
> V5 is in ES sampling, which means that the only way to get it is direct
> from your Xilinx FAE.
>
> But, I have checked, and all the parts announced are on the shelf here
> in San Jose, so supply is not the issue (LX50, LX85, LX110).
> [...]
> If you wait for it to be on the shelf at your distributor, perhaps your
> competition isn't waiting....

... or perhaps he IS hoping the that his competition isn't waiting.  In
the past, he'd come out ahead by staying on the released products if
he:

* wants a sellable product on schedule since prototypes ES parts aren't
recommended for production design (see
http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=16760)

* needs  to have parts that are guaranteed to be bitstream compatible
with future production parts

* needs I-temp sooner than six months after the advertised date

* needs MGT's sooner than 6 months, no make that 12, oops, I mean 18,
no wait... ?? months late  (I saw your post early this week about
this... it's nice to see a public fess-up).

And that's just V4.  I believe I remember serious catches in V2Pro and
V2ProX as well.

Xilinx has taught many of us many painful lessons over the past three
years.  Not to say that we wouldn't have had the same lessons with
Altera, but engineering is about tradeoffs and having something
available to sell to hit your market window, not blindly using the
latest cool part because it just came out.

With best regards,

   Marc


Article: 102633
Subject: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
From: "Paul Leventis" <paul.leventis@gmail.com>
Date: 18 May 2006 06:29:13 -0700
Links: << >>  << T >>  << A >>
Hi Antti,

I cannot comment on announcement or release timeframes for our next-gen
product family/families.  But I'm sure you didn't expect me to answer
your question :-)

All I can tell you is that our next-gen products will be pretty cool.

Regards,

- Paul


Article: 102634
Subject: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
From: "Antti" <Antti.Lukats@xilant.com>
Date: 18 May 2006 06:35:06 -0700
Links: << >>  << T >>  << A >>
well, yes-no ;) the info about Altera 65nm press coming out this year
(end of) is directly from Altera (not from rep or disti), so if that
info is out-dated, e.g. if the Altera 65nm PR is either coming way
earlier or way later, than on that topic you may have responded. no
comment means that the assumption (end of 2006) could still be consider
best guess ?

Antti
PS hope you guy fixup the mockup with MAX2, I mean machXO beats MAX2
hands down, not that MAX2 is bad, it's pretty nice, but.. no RAM is a
real issue


Article: 102635
Subject: Re: Where can i get "Quartus II Device Information for UNIX & Linux CD"
From: "Subroto Datta" <sdatta@altera.com>
Date: Thu, 18 May 2006 14:16:19 GMT
Links: << >>  << T >>  << A >>
Where did you get the first CD from to do the install? The second CD that is 
being asked for is in the same box.

- Subroto Datta
Altera Corp.

<huymEmail@gmail.com> wrote in message 
news:1147937135.353318.81670@g10g2000cwb.googlegroups.com...
> Hi,
>
> I am tring to install Altera Quartus II v6.0 under Debian 3.1.
> During the install process, the install script ask me to insert the CD:
> Quartus II Device Information for UNIX & Linux CD, but I searched
> within the www.alter.com, I cannot find it.
> Does anyone here has got the CD?
>
> thanks.
> 



Article: 102636
Subject: OFFSET constraints with derived clocks - Xilinx FPGA
From: muthusnv@gmail.com
Date: 18 May 2006 08:37:37 -0700
Links: << >>  << T >>  << A >>
Hello,
I am using Virtex2p Xilinx FPGA. My design accepts a clock input of
25Mzh. A system clock of 75Mhz is derived from 25Mhz input with a DCM.
All of my internal logics are operating at this derived clock of 75Mhz.
And the same clock is driven as output of the FPGA on the source
synchronous interface side also.
All the IO are driven from 75Mhz clock. Similarly all the inputs will
be sampled at 75Mhz clock.
---
I have a problem here. How do give OFFSET_IN, OFFSET_OUT constraint for
my IOs? Xilinx is not accepting internal nets in OFFSET constraints. It
asks for clock input. The only clock input is 25Mhz. Since this input
clock is not having any fixed phase difference with 75Mhz clock, the
OFFSET values with respect to 25Mhz will not contrain the design
properly.

What is the solution for this?

I did lot of googling and search on xilinx web-site, and not able to
find any answers.

Any inputs would be greatly appreciated.


Thank you,
Muthu


Article: 102637
Subject: Re: Reality of V5 as ES
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 18 May 2006 08:39:14 -0700
Links: << >>  << T >>  << A >>
Marc,

Can't disagree with anything, except I did say that we are doing C and I 
grade at the same time for V5.

Hope that helps.

Austin

Marc Randolph wrote:

> Austin Lesea wrote:
> 
>>Jan,
>>
>>V5 is in ES sampling, which means that the only way to get it is direct
>>from your Xilinx FAE.
>>
>>But, I have checked, and all the parts announced are on the shelf here
>>in San Jose, so supply is not the issue (LX50, LX85, LX110).
>>[...]
>>If you wait for it to be on the shelf at your distributor, perhaps your
>>competition isn't waiting....
> 
> 
> ... or perhaps he IS hoping the that his competition isn't waiting.  In
> the past, he'd come out ahead by staying on the released products if
> he:
> 
> * wants a sellable product on schedule since prototypes ES parts aren't
> recommended for production design (see
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=16760)
> 
> * needs  to have parts that are guaranteed to be bitstream compatible
> with future production parts
> 
> * needs I-temp sooner than six months after the advertised date
> 
> * needs MGT's sooner than 6 months, no make that 12, oops, I mean 18,
> no wait... ?? months late  (I saw your post early this week about
> this... it's nice to see a public fess-up).
> 
> And that's just V4.  I believe I remember serious catches in V2Pro and
> V2ProX as well.
> 
> Xilinx has taught many of us many painful lessons over the past three
> years.  Not to say that we wouldn't have had the same lessons with
> Altera, but engineering is about tradeoffs and having something
> available to sell to hit your market window, not blindly using the
> latest cool part because it just came out.
> 
> With best regards,
> 
>    Marc
> 

Article: 102638
Subject: FPGA Configuration Question
From: Eli Hughes <emh203@psu.edu>
Date: Thu, 18 May 2006 11:44:28 -0400
Links: << >>  << T >>  << A >>
This is a very simple question, but is something that I have taken for 
granted with all of the nice tools.   For the Xilinx FPGAs (Spartan, 
Virtex), the ISE tools generated a .bit file for configuration for 
specific device.

If I wanted an MCU on my PCB to hold the configuration data and 
configure the FPGA on my target board, could I literally just send in 
the the data in the .bit file bit by bit with the CCLK, DIN, etc pins?
Or do I convert this file into a different hex file for an direct bit 
for bit configuration.


Thanks,
Eli Hughes

Article: 102639
Subject: Re: Clocking ZBT RAM via DCM on ML40x board
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Thu, 18 May 2006 08:45:09 -0700
Links: << >>  << T >>  << A >>
Hello Tomasz,

Here is part of my UCF file

NET sram_clk_pin  LOC = AF7;
NET sram_clk_pin  IOSTANDARD = LVCMOS33;
NET sram_clk_pin  DRIVE = 16;
NET sram_clk_pin  SLEW = FAST;
NET sram_clk_fb   LOC = AD17;
NET sram_clk_fb   IOSTANDARD = LVCMOS33;

As you can see, I am driving AF7 and receiving feedback on AD17.

The problem might be on the schematic that both signals are labeled with the 
same name, they have to, since they share common copper. I recall that the 
designer put a comment on AD17 indicating that it is feedback although I 
didn't trace the paths to see if there would be a difference in switching 
the two lines.

I am also using, per Xilinx instruction, two DCMs, one for the internal 
workings and one to drive the external clock pin.

I am using 100 MHz, clk90, with an initial tap delay of 55 or about 2.1ns.
Not too sure about my reset circuitry. Hope you read VHDL:

 sbuf_external_clock_pin_dcm: sram_dcm
 port map (
   clkfb_in    => sbuf_domain_m_clk_fb,
   psclk_in    => sbuf_domain_d_psclk,
   psen_in     => sbuf_domain_d_psen,
   psincdec_in => sbuf_domain_d_psinc,
   clkin_in    => sbuf_domain_m_clk,
   rst_in      => sbuf_domain_m_reset_raw,
   clk0_out    => open, -- 170 taps
   clk90_out   => sbuf_domain_m_clk_pin, -- 22 taps to 74 taps
   clk180_out  => open, -- 160 taps
   clk270_out  => open,  -- 100 taps to 120 taps
   locked_out  => sbuf_domain_m_lock,
   psdone_out  => sbuf_domain_d_psdone );

   -- Set the following:
   -- CLKIN FREQ 100 MHz
   -- PHASE DELAY VARIABLE_POSITIVE 55 taps
   -- CLKIN EXTERNAL
   -- Feedback External Single

 sbuf_domain_m_reset_delay_SRL16 : SRL16
 generic map (
  INIT => X"0000")
 port map (
  Q   => sbuf_domain_m_lock_delayed,
  A0  => '1', -- 16 clock delays
  A1  => '1',
  A2  => '1',
  A3  => '1',
  CLK => sbuf_domain_m_clk,
  D   => sbuf_domain_m_lock );

 sbuf_domain_m_reset_process: process(sbuf_domain_m_clk)
 begin
 if( sbuf_domain_m_clk'event and sbuf_domain_m_clk='1') then
   sbuf_domain_m_reset <= not( sbuf_domain_m_lock and 
sbuf_domain_m_lock_delayed );
 end if;
 end process;



Brad Smallridge
Aivision dot com




"Tomasz Dziecielewski" <tomdz@NOSPAMmultimedia.edu.pl> wrote in message 
news:p9go62lu6fp6tamet27co14fvnffognu47@4ax.com...
> Hello,
>
> I'm trying to use a DCM to deskew the memory clock but find it hard
> to learn which pads should be used to create the clock feedback loop.
> In the board's (ML402) schematic there is the SRAM_CLK (Feedback)
> pad (AD17) which, as I reckon, is used to drive the clock signal out
> of the FPGA (pls correct me if I'm wrong with this one). But which pad
> brings the signal back and closes the loop?
>
> Thanks in advance. Regards,
> Tomasz Dziecielewski 



Article: 102640
Subject: Re: FPGA Configuration Question
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Thu, 18 May 2006 17:48:15 +0200
Links: << >>  << T >>  << A >>
Eli Hughes schrieb:
> This is a very simple question, but is something that I have taken for 
> granted with all of the nice tools.   For the Xilinx FPGAs (Spartan, 
> Virtex), the ISE tools generated a .bit file for configuration for 
> specific device.
> 
> If I wanted an MCU on my PCB to hold the configuration data and 
> configure the FPGA on my target board, could I literally just send in 
> the the data in the .bit file bit by bit with the CCLK, DIN, etc pins?

Yes, this is possible. There is some rubbish at the begining of the 
file, but this is ignored, since the FPGA searches for the Sync pattern 
first.

> Or do I convert this file into a different hex file for an direct bit 
> for bit configuration.

The hex file is just fine for other tools to integrate the FPGA 
bitstream into your firmware.

Regards
Falk

Article: 102641
Subject: Re: "disappointing" performance
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 18 May 2006 08:51:56 -0700
Links: << >>  << T >>  << A >>
Peter,

It (Intel's 'multi' core) was an invited presentation at SELSE II IEEE 
workshop in Champaign-Urbana in April 2006 (U of Illinois).

I have no idea if the slides will ever appear anywhere.

IEEE workshops tend to be less strict about providing material for 
publication.

http://www.selse.org/

Austin

Article: 102642
Subject: Re: "disappointing" performance
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 18 May 2006 08:53:51 -0700
Links: << >>  << T >>  << A >>
Peter,

Found them!

http://www.selse.org/presentations/UIUC_SBorkar_April_11_2006.pdf

Austin

Peter Mendham wrote:

> Austin Lesea wrote:
> 
>> Intel proposes a future with more than 200 x86 cores on one die, with 
>> a "communications fabric" and many memories.  All on one die.  Small 
>> software problem to be solved by the need to have it solved....
> 
> 
> Do you have a ref on that (an url perhaps?) I'm really interested...
> 
> I tried Google but I'm obviously not feeding it the right keywords.
> 
> Thanks,
> 
> -- Peter

Article: 102643
Subject: Re: SystemACE bootloader for PowerPC on Virtex4 FX
From: Peter Ryser <peter.ryser@xilinx.com>
Date: Thu, 18 May 2006 09:13:10 -0700
Links: << >>  << T >>  << A >>
In that case you do not even need a bootloader. You can create an ACE 
file that contains the bitstream and the target application. System ACE 
CF will load the target application anywhere into the space addressable 
by the processor, i.e. even external memory.

You can create such an ACE file easily from the GUI or from the command 
line.

Let's say Linux (zImage.elf) is your target application. In that case 
the command to create the ACE file from the command line would be (one 
line):
$ xmd -tcl genace.tcl -board ml403 -hw implementation/download.bit -elf 
zImage.elf -ace linux.ace


- Peter


Jon Beniston wrote:
> I only have one application to load, it is just too big for on-chip
> memory, so it has to be loaded into external SDRAM.
> 
> Cheers,
> Jon
> 


Article: 102644
Subject: Re: FPGA Configuration Question
From: "dand2k" <dand@oz.net>
Date: 18 May 2006 09:17:08 -0700
Links: << >>  << T >>  << A >>
Here's a good discussion on accomplishing FPGA configuration from MCU.

http://www.fpga-faq.org/FAQ_Pages/0038_Config_FPGA_from_a_processor.htm


Article: 102645
Subject: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
From: Peter Wallace <pcw@karpy.com>
Date: Thu, 18 May 2006 10:19:57 -0700
Links: << >>  << T >>  << A >>
On Tue, 16 May 2006 16:33:35 -0700, Laurent Pinchart wrote:

> Hi,
> 
>> And you're surprized that they're not giving away their design?
> 
> Who's talking about their design ? I'm not trying to create a cheap
> clone, but to drive the programmer using free software. I don't mind
> paying $38 (or even $150) for a good USB JTAG dongle, as long as I can
> use it.
> 
>> Not to rain on your parade, but the typical FPGA engineer has spent a
>> hundred bucks or so on the part, a grand or two on the PCB, and 1/2 a
>> man-year on the code.  $38 for a JTAG dongle is down in the noise.
>> 
>> If it's hobby use you're after, you can stretch the JTAG signals off of
>> your card to another target.
>> 
>> There is an open-JTAG effort on SourceForge.  You might want to check
>> it out.
> 
> I've checked that out, but it only support parallel port bit-banging
> adapters.
> 
> I want to buy a USB JTAG programmer that I can actually use with free
> softwares. Why is there none available ?
> 
> Laurent Pinchart
 

We have a tiny FTDI 2232 based JTAG dongle, just havent got around to
buiding them yet. Supports IO voltages from 1.6V to 5V (or 1.2V to 3.3V 
using different level tranlators) Should be really cheap
~$25.00 or so, or bare PCBs for cost of shipping (Free!) I think there
are Linux drivers available for 2232.

Peter Wallace

Article: 102646
Subject: Spartan 3 Readback
From: "jvdh" <johannes.vanderhorst@gmail.com>
Date: 18 May 2006 10:24:05 -0700
Links: << >>  << T >>  << A >>
I am working on a custom configuration controller that configures a
Spartan 3 through SelectMap and verifies the configuration through
readback.

Configuration is simply writing the .bin file into the S3, no problems
there.

The trouble starts when I want to give the readback commands the the
FPGA - al commands are ignored completely, even though I am using the
same code to write to the device.  I'm currently just trying to issue a
SHUTDOWN command to the FPGA, to see if anything happens.

I've checked (and rechecked) that the data appears on the D0-D7 pins of
the FPGA (byte swapped), with CCLK merrily running along, CS_B=0,
RDWR_B=0, and I set persist=yes in bitgen.

The S3 datasheet has an interesting flowdiagram (fig 23, p37) that show
reconfiguration starting with "prog_b low after power on", then "prog_b
high" to avoid clearing the configuration.  What is happing there?

Is there anything I'm missing?  Some command (on CS_B/RDWR_B perhaps?)
that will make the FPGA aware of my intentions?

Any suggestions will be greatly appreciated.

jvdh

http://www.ee.sun.ac.za/~jvdh


Article: 102647
Subject: Re: OFFSET constraints with derived clocks - Xilinx FPGA
From: Duane Clark <junkmail@junkmail.com>
Date: Thu, 18 May 2006 18:00:09 GMT
Links: << >>  << T >>  << A >>
muthusnv@gmail.com wrote:
> Hello,
> I am using Virtex2p Xilinx FPGA. My design accepts a clock input of
> 25Mzh. A system clock of 75Mhz is derived from 25Mhz input with a DCM.
> All of my internal logics are operating at this derived clock of 75Mhz.
> And the same clock is driven as output of the FPGA on the source
> synchronous interface side also.
> All the IO are driven from 75Mhz clock. Similarly all the inputs will
> be sampled at 75Mhz clock.
> ---
> I have a problem here. How do give OFFSET_IN, OFFSET_OUT constraint for
> my IOs? Xilinx is not accepting internal nets in OFFSET constraints. It
> asks for clock input. The only clock input is 25Mhz. Since this input
> clock is not having any fixed phase difference with 75Mhz clock, the
> OFFSET values with respect to 25Mhz will not contrain the design
> properly.
> 

I hope you won't be annoyed that I don't directly answer your question.

You state that all inputs are sampled by the 75MHz clock. I assume then 
that this is using the FFs within the IOBs? If that is the case, then an 
offset_in is really irrelevant. There are only two possible offsets, one 
with the pad going through the builtin delay element to the flipflop, 
and one with the delay element bypassed. In both cases the offsets 
relative to the 75MHz clock can be found from the data sheet, and I 
would imagine is also in the timing report file.

Also, are all the outputs clocked? That is, they are all using the 
output flipflop in the IOBs? Then the same thing applies to them, except 
that there is no delay element and the only variable affecting the 
output offset is the IO standard used.

Article: 102648
Subject: Re: Spartan 3 Readback
From: "dand2k" <dand@oz.net>
Date: 18 May 2006 11:18:19 -0700
Links: << >>  << T >>  << A >>
Which Spartan3 device are you using? There is an eratta for the
XC3S1500 stating that some of the engineering sample parts have a
readback bug in them. You might want to search the Xilinx support
website for readback failures, or consult the eratta pages for the
device you are using.

Dan


Article: 102649
Subject: Re: ADC implementation on FPGA ?
From: lb.edc@telenet.be
Date: Thu, 18 May 2006 19:58:40 GMT
Links: << >>  << T >>  << A >>
I think it is all feasable. The problem is that a solution that works
for you doesn't match the needs for 99% of the other potential users.
So it is hard to obtain such a specific function to a programmable
device.
Maybe one day someone will be able to build a configurable or
programmable ADC. (Austin, is this allready patented? Otherwise I
might be a candidate) Then it will be useful on an FPGA. And this is
true for other analog functions (not to mention the process difference
between analog and digital).

Regards

Luc

On Thu, 18 May 2006 22:58:14 +1200, Jim Granville
<no.spam@designtools.co.nz> wrote:

>Scope wrote:
>>>What's the speed ..?
>> 
>> 
>> up to 100 Mhz.
>> 
>> 
>>>Voltage levels ..?
>> 
>> 
>> analog input signal is between -1V and 1V
>> 
>> 
>>>Cost ..?
>> 
>> 
>> cost is not a problem
>> 
>> 
>>>Complexity ..?
>> 
>> 
>> What do you want to say with the term "complexity" ?
>> 
>> 
>> 
>> I need to convert it to an 8 bits format.
>
>Linearity ?   SFDR ?
>
>The first figure was 16 bits ?
>Perhaps this is homework ?
>
>The killer in the ADC is that letter A = Analog.
>You can do digital stuff in FPGA, but not analog.
>You can use the FPGA to minimise the Analog, but it cannot
>be removed entirely. SigmaDelta ADCs are one path, but not
>for 100MHz sample rates...
>  Sawtooth + Comparitor gives a low performance ADC, a long way
>from 16 bits.
>  8 bits then needs a time resolve of 39ps - you get the idea....
>
>-jg



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