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Virtex-II series is a good choice!Article: 45051
Hey Shen, I hope you're doing well... I don't use Synplify, but this might work for you. When I have this problem and functional simulation works okay, the problem is usually because I made a coding error where a register is synthesized as a transparent latch instead of a D flip-flop. I can generally find the problem by looking for transparent latch warnings in the synthesis report. jeff shengyu_shen@hotmail.com (ssy) wrote in message news:<f4a5f64f.0207100455.2d0e80c5@posting.google.com>... > Hi everyone > > I am using synplify 6.2.4 to synthesis and Quartus II to P&R > > after all done, I found there are some combinational loops in my > design, but the report is based on the postsyn netlist, not on the RTL > source, so How can I know which part of my design cause these loops? > > Best RegardArticle: 45052
I got a combinatorial loop! It might not be similar to yours, but here
it is...
I'm a strong synchronous designer but ever now and then I need to pull
some coding trick to get good results.
Today I had a for loop to assign multiple bits into a "single" wire by
using a blocking operator in the for loop.
always@(inputs)
for( i=0; i<32; i=i+1 )
wide_result = wide_result | fn(inputs,i);
The "fn" is just a reference to "some" function of the inputs and the
loop variable.
The problem with the above code is that the wide_result isn't
initialized (with a blocking operator) in the always block. Adding an
initial value got rid of my combinatorial loop.
always@(inputs)
begin
wide_result = 0;
for( i=0; i<32; i=i+1 )
wide_result = wide_result | fn(inputs,i);
end
If you have HDL_Analyst with your Synplify version, take a look at the
RTL view and see what's feeding what for the element it lists. You
might see something that makes sense for your code.
ssy wrote:
>
> Hi everyone
>
> I am using synplify 6.2.4 to synthesis and Quartus II to P&R
>
> after all done, I found there are some combinational loops in my
> design, but the report is based on the postsyn netlist, not on the RTL
> source, so How can I know which part of my design cause these loops?
>
> Best Regard
Article: 45053Have you looked at the Cypress Warp package? For $150, it will put VHDL into a 16V8. And do a gate-level simulation. Worked for me. On 29 Jun 2002 12:48:41 -0700, sandeepmec@hotmail.com (Sandeep Unni) wrote: >thanks for the info. since i dont have the option of changing the >target chip, i tried the synario complier. the device issue is solved >but now i am facing another problem.. > >the synario compiler does not recognise the std_logic_unsigned >package. it keeps giving a 'the following variable has not been >declared' error. the same code compiles well in max plus. do the >Synopsys libraries (of which std_logic_unsigned is a part of) need to >be imported into Synario? if so how? >any other suggestions please? > >-Sandeep > > >Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3D1D02B0.7EFE@designtools.co.nz>... >> Sandeep Unni wrote: >> > >> > Hi, >> > >> > I am working on programming a GAL 16v8 chip. I am using the ALtera Max >> > plus compiler but i was not able to find the equivalent device. Can >> > someone shed some light on this, >> >> You cannot find it, because Altera do not make GAL16V8. >> They used to have 20 pin EP3x0 devices, but no longer. >> >> Probably your best bet, is Atmel ATF16V8BQL / ATF16V8CZ devices, >> and their free WinCUPL tool chain. >> >> -jgArticle: 45054
Ray is 100% correct. The only 2 things that the Xilinx ram can not support which must be re-designed as you migrate to the block ram are: 1. unregistered read address 2. registered output data option However, you also have the added flexibility to use distributed ram which is usually not too costly bing that you are in a small 10ke device. The distributed rams support "asynchronous" unregistered read addresses and you can add output flops as needed. -Guy Schlacter Absolute Consulting Inc. absoluteconsulting.home.attbi.com "Ray Andraka" <ray@andraka.com> wrote in message news:3D2123FE.6F45A55F@andraka.com... > Based on the responses you've gotten so far, there is a lot of > misinformation out there. > > The Altera 10KE ESB is a 4K bit memory that can be configured as 256 x 16, > 512 x 8, 1k x 4 or 2k x 2. It has separate read and write addresses so > that you can do dual port (one read, one write) access to two different > locations. The inputs and outputs may be registered or non-registered > > The Xilinx BRAM is also 4K bits, but it is true dual port (both ports > independently support read and write, so you can simultaneously write both > ports, for example), it can be configured as 4Kx1 to 256x16, and it is > synchronous only. > > If the Altera design is using the ESB memory with one of either the data > output or the read address registered, then it can be directly replaced > with the xilinx BRAM. If it is being used in an unregistered > configuration, then you will need to modify your design to accommodate the > 1 clock latency inherent in the Xilinx BRAM read. > > > > Search for knowledge wrote: > > > Hi Everyone, > > > > I inherited a design from a previous engineer which was in an Altera > > 10KE part. The new board has a VirtexE part. > > > > I have the Altera FPGA design, but when i try and replace the dual > > port block RAM in Altera (namely altdpram) with the RAM generated by > > Xilinx core generator, the design does not work on the new board. > > > > I was wondering if there is a way to convert Altera's block RAM as a > > functionally equivalent Xilinx block RAM. > > > > An early reply would be highly appreciated. > > > > Thanks, > > Searcher of Knowledge > > > > o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o > > > > The parameters passed to MaxPlusII are the following > > ----------------------------------------------------------------------- > > module dual_port_ram2 (data, rdaddress, wraddress, wren, inclock, > > rden, outclock, aclr, q) > > /* synthesis black_box > > WIDTH = 16 > > WIDTHAD = 8 > > LPM_TYPE="altdpram" */; > > > > ----------------------------------------------------------------------- > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 45055
John- Absolutely not spam you cynic... This was real solicitation by their VC group. I am looking for employment (permanent or otherwise) and really wanted to bounce it off the group on this forum. So - has anyone heard of this www.cradle.com or been contacted by anyone regarding them???? -guy "John Williams" <j2.williams@qut.edu.au> wrote in message news:3D2B989B.F1160BD9@qut.edu.au... > > > Guy Schlacter wrote: > > > > I got an email asking me to check out this new technology which is a > > cross between NP's and FPGAs to address high performance communication > > processing needs. > > > > Just curious if anyone else got a solicitation email to check them out > > (Cradle Technologies www.cradle.com ) ?? > > Nice try at a subtle spam job!Article: 45056
Guy Schlacter wrote: > > Bug off. It was real solicitation and am interested in investigating for > employement. trying to do due diligence. Steady on big fella! I didn't go in hard, just a gentle ribbing that your message sounded like spam. I've seen similar attempts before, so sorry if I got it wrong, but no need to get shirty. Regards, JohnArticle: 45057
Hi all, I am using FPGA as a memory mapped device to the processor(a DSP) in my system. The device used is XILINX Virtex 600K gate speed grade -4 and the software is ISE 4.2i. The aim is to communicate asynchronously between 256 memory locations(width 16) which is inside FPGA and the processor. For processor read operation (i.e. processor reads FPGA), the post place and route static timing report shows these values (with pad to pad timing constraint of 20ns): 1. Address_bus to Data_bus (pad to pad) delay ~= 32ns(max) 2. Memory select signal to Data_bus (pad to pad) delay ~= 17ns (max) 3. /RD to Data_bus (pad to pad) delay ~= 17ns (max) The processor I am using is a 80 MHz processor and hence I require about 3-4 wait states to read the FPGA. I want to know whether the timing values obtained are far from reality or not. Thanx in advance, Nagaraj CSArticle: 45058
Nagaraj wrote: > > Hi all, > I am using FPGA as a memory mapped device to the processor(a DSP) in > my system. The device used is XILINX Virtex 600K gate speed grade -4 > and the software is ISE 4.2i. The aim is to communicate asynchronously > between 256 memory locations(width 16) which is inside FPGA and the > processor. > For processor read operation (i.e. processor reads FPGA), the post > place and route static timing report shows these values (with pad to > pad timing constraint of 20ns): > 1. Address_bus to Data_bus (pad to pad) delay ~= 32ns(max) > 2. Memory select signal to Data_bus (pad to pad) delay ~= 17ns (max) > 3. /RD to Data_bus (pad to pad) delay ~= 17ns (max) Not sure if this is what you're asking, but anyway... Can you register these inputs? If so then enabling the "Pack IO registers/latches into IOBs" option in the Map Properties can save several couple of nanoseconds on the setup time. This is only possible if you have no logic at all between the pins and the input registers. Similar things are possible for outputs as well. > I want to know whether the timing values obtained are far from > reality or not. I think these are usually considered "worst-case" timings. The word from the wise seems to be that you'll usually get better performance than that, but don't count on it - if your supply voltage droops a bit, or the temperature drops, or whatever, your device may suddenly stop working. Hope this helps, Regards, JohnArticle: 45059
Why not try XST (Xilinx Synthesis Technology) which is free?
It can generate an EDIF netlist if you follow the instructions provided
by the following posting.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&threadm=aceeac%249fj%241%40newsreader.mailgate.org&rnum=1&prev=/groups%3Fq%3DKevin%2BEDIF%2BXST%2Bgroup:comp.arch.fpga%26hl%3Den%26lr%3D%26ie%3DUTF-8%26selm%3Daceeac%25249fj%25241%2540newsreader.mailgate.org%26rnum%3D1
Inspecting the EDIF netlist generated by FPGA Express might give
you some clues on what is going on.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
M Schreiber wrote:
>
> Laurent,
> I tried your first solution and it works fine with one of my
> blocks, but when I connect them together in a bus orientation, fpga
> express cannot figure out the port type (DATA port) for some reason.
> I had access today to another colleague's synthesis tool (Sympilfy)
> and I ran one of earlier versions of code through it with good results
> ( few warnings, but the code seems to run well on the xilinx demo
> board). So I am not sure what the problem is with fpga express, I am
> going to keep working at it and see if I can get it to work with FPGA
> express. Thanks again for your assiatence. I will let you know what
> happens.
> Thanks,
> Mike
Article: 45060
Go with a device supported by Xilinx ISE WebPACK.
The reason I recommend ISE WebPACK over other competing free/low cost (<
$300) is because you can use a crippled version (i.e., Runs slow when
simulating a large design.) of ModelSim for free.
Xilinx Spartan-II should be fine for your application since it can
connect directly to 5V TTL devices without external resistors.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Stefan Schulte wrote:
>
> Hi all!
>
> I'm a german student and want to buy an develpment-board for home.
> In the uni, we use Actel FPGAs and Synopsis on SUN-Stations.
> So I want to do some exercises at home and make some own developments
> e.g. EPP-Printerport-Interface for A/D-Converter.
>
> Now I don't know whats easier/cheaper/newer (for future-support)
> because I don't want to buy a newer one next year.
> Can you help me?
>
> Steven
Article: 45061
Guy Schlacter wrote:
>
> I am looking for employment (permanent or otherwise) and really wanted to
> bounce it off the group on this forum.
>
> -guy
>
I thought you had your own consulting business?
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 45062Hi Jeff Nice to see you, how about your companiES!! :-) I run through the functional simulation and all are OK, but the synplify tell me there are many loops, I met with this kind of problem for the first time, I had just add a DMA core from opencores to my design, anf then discover these error Thank you for your direction, I will check that Best Regard jeff@mock.com (Jeff Mock) wrote in message news:<5e72ca82.0207101842.54ac4ed@posting.google.com>... > Hey Shen, I hope you're doing well... > > I don't use Synplify, but this might work for you. When > I have this problem and functional simulation works okay, > the problem is usually because I made a coding error > where a register is synthesized as a transparent latch > instead of a D flip-flop. I can generally find the > problem by looking for transparent latch warnings in > the synthesis report. > > jeff > > > shengyu_shen@hotmail.com (ssy) wrote in message news:<f4a5f64f.0207100455.2d0e80c5@posting.google.com>... > > Hi everyone > > > > I am using synplify 6.2.4 to synthesis and Quartus II to P&R > > > > after all done, I found there are some combinational loops in my > > design, but the report is based on the postsyn netlist, not on the RTL > > source, so How can I know which part of my design cause these loops? > > > > Best RegardArticle: 45063
But I think Altera's Excalibur will be a better choice, because Altera's device have more interconnect route, this will make the netural network very happy ZhengLin <> wrote in message news:<ee77cd1.1@WebX.sUN8CHnE>... > Virtex-II series is a good choice!Article: 45064
Hi Daniel, It depends very much on your algorithm, but a possible alternative approach would be to use Handel-C to target the FPGA fabric directly. At the moment, (as far as I know) there is no add-on for Matlab to output Handel-C directly, but I notice in the latest Mathworks borchure they make a big deal of how their C/C++ output is portable and documented. Although I don't know of anyone who has tried it before, I am guessing based on this, porting their output to Handel-C (or any of the other hardware C derivitives) by hand would not be so difficult. Whether you go for a Xilinx or Altera device, they both have their 'soft' processor cores (the MicroBlze and the NIOS respectively) which we have interfaced to Handel-C in variuos applications. Using a combination of processor and FPGA logic like this would cater best for problems which combine both complex control-path and fast data processing parts. We do have a simple protoyping board available, the RC100, which has a battery-powered derivitive. It has 36 spare lines of I/O for your ADCs and DACs available on a header and uses a Xilinx Spartan-II 200 FPGA, which we have used to do some fairly complex signal processing. We have libraries available for this board to pass raw data back and forth between FPGA/on-board memory and PC via parallel port. Neil Stainton Applications Engineer Celoxica Ltd. www.celoxica.com "Daniel" <Daniel.Westerheim@Lynntech.com> wrote in message news:ee77cd1.-1@WebX.sUN8CHnE... > I am new to the world of PLDs and FPGAs and need advice on choosing a device and developement kit. > > My application will be in a portable device and therefore needs to be as low power as possible and small (BGA probably). Xilinx has an application note (#154, #155) where they put an ADC and an DAC in their Virtex FPGA. This would be a highly desirable feature in any device recommended. > > Another major feature I need is that our data is fed into a Nueral Network currently in MatLab. MatLab can export the algorithm for the ANN in C code, which i would then like to use in the FPGA. I think this would be done by essentially creating a processor on the FPGA (with command architecture) and then compiling the C into assembly and downloading into a Program Memory for the processor? > > The data rate for this particular application will probably not be very high, but I would like to use FPGA technology in future projects where speed is critical (ultrasonic measurements, impedence, etc.). I would like to pay <~$1000 for a developement board. > > All of your advice and opinions are welcome. If you need more info, please email me and I will answer to the best of my ability. > > Thanks in advance > > Daniel Westerheim > Research EngineerArticle: 45065
I wonder if someone can shed some light on where one needs dynamic addition subtraction and how frequent it is, that it warranted special logic to be added by Altera in its new device Stratix. thanx in advance... bye, Nitin.Article: 45066
Hello! We are currently comparing different variants of implementation the Layer 2 protocol of 100Mb/s Ethernet standard in our project. Mainly we consider two items: 1. using ASIC chip from Macronix (MX98728EC) whith on-chip PHY layer tranciever. 2. using Xilinx/Altera FPGA with open core media access controller (MAC) + external PHY layer tranceiver. Can anybody give any idea about what open core to choose for this taking in account FPGA price & core bugs & core size. Thanks in advance. Adel.Article: 45067
It is very common in signal processing. CORDIC rotation is one
application (see my paper: "a survey of Cordic algorithms..." available on
my website). Signed scaling accumulator multipliers (used in distributed
arithmetic filters) is another place they are needed. Altera added that
logic to compete better against the Xilinx logic which allows 4 input
arithmetic functions. The Altera structure breaks the LUTinto a pair of 3
LUTs for arithmetic, so that if you want to do any controlled arithmetic,
you are forced to two levels of logic. THe more common 3 input arithmetic
is accumulators with load or clear, and add/subtract and these have been
addressed by the added logic in the stratix architecture.
nitin wrote:
> I wonder if someone can shed some light on where one needs dynamic
> addition subtraction and how frequent it is, that it warranted special
> logic to be added by Altera in its new device Stratix.
>
> thanx in advance...
>
> bye,
> Nitin.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45068Hi, Guys I am looking for a non-pipelined signed integer divider with the reminder in fractional format. Anybody can offer any reference? Thanks a lot in advance!!! -- Jianyong Niu ----------------------------- Univ of Sheffield Email: cop00jn@shef.ac.ukArticle: 45069
I am using clk0 out from a clkdll with feedback through a bufg. The system also uses the divide by 4 output (d4 clk) from the same dll. I would like (and have tried) to use the clk90 out to keep the 4x and 1x (divide by 4) clock edges away from each other. If I route the feedback from the clk90 - thru the bufg - into the feedback, the d4 clk still has same phase relationship with clk90 as it did before when using clk0. I saw a previous post that indicated it would be nice to use the clk90 instead of the clk0 for that purpose, but I can't think of a way to do it. Did I mention, that I'm also out of bufg's at this point, although I still have 2 dll's lying around doing nothing. Part is v300e
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