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On 5 Aug, 17:33, John McCaskill <jhmccask...@gmail.com> wrote: > On Aug 4, 5:00 pm, ZHI <threeinchn...@gmail.com> wrote: > > > I am reading some papers about algorthms implementation. I noticed > > they like to compare the synthesis area of the fixed-point > > implementation. I wander where they find the area report for the > > implementation. I only see the slice percent report. I am using the > > Xilinx ISE. I want to know where to generate the area report. Any > > comment is welcome. > Are they giving the area in square mm? If so they are not talking > about FPGAs, but ASICs or custom chips. The area group reports from > ISE are still given in slices, etc, not in square mm. > > If they are talking about area group reports from ISE, you have to > apply an area group constraint to the module/component you want to get > the report for. See the constraint guide documentation for more > information on how to do this. > > Regards, > I see now. Thank you. > John McCaskillwww.fastertechnology.comArticle: 122901
On 9 Aug., 10:37, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > But my problem is > that I want to make the system such that the DEVICE would recognize > that MY_FPGA is connected to it. The problems I face are - > 1. Someone can snoop the wires and replicate the same key as MY_FPGA > writes to the DEVICE. That's what challenge-response authentication used for: the DEVICE sends a random request (x) to the FPGA, and if the FPGA can give the correct answer (e.g. hash(x+key)) it is authenticated. It's very simple in software, but probably a lot more difficult in hardware because you need a good random number source that cannot easily be manipulated. AndreasArticle: 122902
> Actually, the FPGA bit-stream is protected by AES. But my problem is > that I want to make the system such that the DEVICE would recognize > that MY_FPGA is connected to it. The problems I face are - > 1. Someone can snoop the wires and replicate the same key as MY_FPGA > writes to the DEVICE. > 2. DEVICE is an asic. I do not know what challenges are in putting a > non-volatile secured memory into a standard CMOS asic. I'm not a specialist, but... - You can use challenge/response so that no key is exchanged. You'll need some public/private key crypto. - Read this : http://www.xenatera.com/bunnie/proj/anatak/xboxmod.html (especially the part on tapping the HyperTransport bus) : a single student armed with a FPGA nuked microsoft's protection...Article: 122903
You will need to add to Austin's procedure when using Linux, i.e. you will also need to save the state of the peripheral registers. Alternatively, to get a clean restart you could work with kernel modules. Unload modules before shutting down and reload upon start. In that case peripherals get reinitialized when the kernel modules are loaded. - Peter cpope wrote: > "austin" <austin@xilinx.com> wrote in message > news:f902co$gp31@cnn.xilinx.com... >> Clark, >> >> I asked around, and no one had anything handy to do this. This is their >> recommendation: >> >> Shutdown sequence: >> 1) Trigger the shutdown sequence with an interrupt. >> 2) The shutdown routine should save all registers and state. It must >> not use the stack. Next, copy all of memory to a non-volatile storage >> device. >> 3) Write to a non-volatile memory location a flag that at next boot a >> warm-boot should be performed. I recommend a 32 bit word with a unique >> pattern. Ex: 1234_CDEFh >> 4) Processor then signals the power supply to turn off. >> >> Restart sequence: >> 1) At boot the processor checks the warm-boot flag. If set follow the >> steps below. Again, don't use the stack. >> 2) Copy the saved memory from the non-volatile storage device to system >> memory. >> 3) Restore all saved processor registers. >> 4) Execute a return from interrupt. >> >> >> >> This assumes power is lost after suspend. If power is not lost, then >> there is no need for the non-volatile memory. >> >> Austin > > Yes, this is the right sequence. In our case we have sdram that we plan to > put in self refresh mode (another issue I'm not sure how to do from the > xilinx ddr core?) so there's no need for the NV memory. > > I don't know if I mentioned that we're using Linux 2.6. There are a lot of > architectures in the kernel tree that have suspend/resume functions but > nothing for ppc405. Since every V2Pro or V4fx user needs this same function > I'm surprised there isn't some mature code out there. > > Thanks, > Clark > > >Article: 122904
Every time I make a minor change to one of my local pcores I have to do a "Clean Netlist" to ensure that the change is carried out. I find this very painful since it then rebuilds all the other IPs. Is there a way I can just compile the changed file? Is it more efficient to use a .vhdl file or a .ngd which I can generate with ISE. Would this save much time?Article: 122905
Hi, Fred wrote: > Every time I make a minor change to one of my local pcores I have to do a > "Clean Netlist" to ensure that the change is carried out. I find this very > painful since it then rebuilds all the other IPs. > > Is there a way I can just compile the changed file? OPTION CORE_STATE=DEVELOPMENT in the MPD file. Regards, JohnArticle: 122906
Fred wrote:
> Every time I make a minor change to one of my local pcores I have to do a
> "Clean Netlist" to ensure that the change is carried out. I find this very
> painful since it then rebuilds all the other IPs.
>
> Is there a way I can just compile the changed file?
>
> Is it more efficient to use a .vhdl file or a .ngd which I can generate with
> ISE. Would this save much time?
>
>
The "OPTION CORE_STATE=DEVELOPMENT", mentioned elsewhere, will cause
that particular core to always be recompiled, regardless of whether it
has changed (at least last time I tried it). Probably not what you want.
Are you still using the GUI? If you have abandoned that, then you can
edit the makefiles by hand to do this. EDK uses plain makefiles, so it
is puzzling why they don't already handle such a simple task.
Anyway, in system_incl.make, immediately after
PROGRAMCLEAN_TARGETS = ppc405_1_default_programclean
I added entries like:
MY_DDR_CLOCKS_IMPLN = implementation/my_ddr_clocks_wrapper.ngc
MY_DDR_CLOCKS_FILES = pcores/ddr_clocks_v1_00_a/hdl/vhdl/ddr_clocks.vhd \
pcores/ddr_clocks_v1_00_a/data/ddr_clocks_v2_1_0.mpd \
pcores/ddr_clocks_v1_00_a/data/ddr_clocks_v2_1_0.pao
MY_REGS_IMPLN = implementation/my_regs_wrapper.ngc
MY_REGS_FILES = pcores/plb_regs_v1_00_a/hdl/vhdl/regs_core.vhd \
pcores/plb_regs_v1_00_a/hdl/vhdl/plb_ipif_ssp1.vhd \
pcores/plb_regs_v1_00_a/hdl/vhdl/plb_regs.vhd \
pcores/plb_regs_v1_00_a/data/plb_regs_v2_1_0.mpd \
pcores/plb_regs_v1_00_a/data/plb_regs_v2_1_0.pao
MY_WRAPPER_NGC_FILES = $(MY_DDR_CLOCKS_IMPLN) \
$(MY_BITS_IMPLN)
MY_DEVELOPMENT_FILES = $(MY_DDR_CLOCKS_FILES) \
$(MY_REGS_FILES)
Then in system.make, I added immediately after:
#################################################################
# HARDWARE IMPLEMENTATION FLOW
#################################################################
$(MY_DDR_CLOCKS_IMPLN): $(MY_DDR_CLOCKS_FILES)
rm -f implementation/my_ddr_clocks_wrapper.ngc
rm -f implementation/cache/my_ddr_clocks_wrapper.ngc
$(MY_REGS_IMPLN): $(MY_REGS_FILES)
rm -f implementation/my_regs_wrapper.ngc
rm -f implementation/cache/my_regs_wrapper.ngc
Then changed the lines (note the addition of MY_WRAPPER... and
MY_DEVELOP...:
implementation/$(SYSTEM).bmm \
$(CORE_WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
$(MY_DEVELOPMENT_FILES)
@echo "****************************************************"
@echo "Creating system netlist for hardware specification.."
@echo "****************************************************"
platgen $(PLATGEN_OPTIONS) -st xst $(MHSFILE)
$(POSTSYN_NETLIST): $(MY_WRAPPER_NGC_FILES) $(CORE_WRAPPER_NGC_FILES)
implementation/$(SYSTEM).bmm
@echo "Running synthesis..."
bash -c "cd synthesis; ./synthesis.sh; cd .."
Article: 122907Jim Granville wrote: > Symon wrote: >> Anyway, if you post here on CAF and didn't get an email, clearly >> you're not a 'significant' contributor. I wonder what one has to do to >> be significant? > > My take on 'significant' was that anyone with a pulse was asked ! ;) > > -jg > Not true. I wasn't asked... :-( ken From taileb.mehdi@gmail.com Thu Aug 09 21:17:20 2007 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 09 Aug 2007 23:17:20 -0500 From: El Mehdi Taileb <taileb.mehdi@gmail.com> Subject: Re: Regional Clock Resources Newsgroups: comp.arch.fpga References: <1186547836.612742.141150@g4g2000hsf.googlegroups.com> User-Agent: Pan/0.125 (Potzrebie) Message-Id: <pan.2007.08.10.04.17.07@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: Thu, 09 Aug 2007 23:17:20 -0500 Lines: 36 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-zDUAxAUu1hNw08QaUvqBjSmY2/nM0M8FTLRHrM1+5ZoTcKlouTA2SFVd//z689TtbGMYMROldS043kK!XjwgEeFRQNJBzWoqLbn8LSgfzSEIWIOWWdLBhCFKPnNpcH3zJ76GFTp1N80= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.35 Bytes: 2558 Xref: prodigy.net comp.arch.fpga:134804 X-Received-Date: Fri, 10 Aug 2007 00:17:21 EDT (newsdbm02.news.prodigy.net) On Wed, 08 Aug 2007 04:37:16 +0000, Aida wrote: > Hi, > > I am having some trouble with implementing several serial links per IO > Bank in Virtex5. > An IO bank is about the same size as a clock region. Each clock region > has 4 BUFIO and 2 BUFR available. I am trying to implement 4 serial > links by utilizing 4 BUFIOs and 2 BUFRs in one clock region and the 2 > other BUFRs from a neighboring clock region. However, everytime I try to > specify the clock region for the BUFIO and BUFR I get mapping errors. > > The UCF looks like: > > #Locations for BUFIO > INST "RX/BUFIO" AREA_GROUP = "BUFIO_0"; AREA_GROUP "BUFIO_0" RANGE = > CLOCKREGION_X0Y3; #Location for BUFR > INST "RX/BUFR" AREA_GROUP = "BUFR_0"; AREA_GROUP "BUFR_0" RANGE = > CLOCKREGION_X0Y2; > > I get an error message during mapping where it says that the structure > is locked and the relative placment of the locked logic violates the > desired structure. The problem was found due to the relative placement > of BUFIO and BUFR. > > I wonder if anyone has tried to do similar implementations or have come > across such problems. > Basically, Im trying to find out if I can use the BUFR from the > neighboring clock region and how to assign them. > > Thank you in advance, > Aida You can get the problem solved by just instantiating BUFIO and BUFR, without any constraints. Then constraint your I/O Buffers to concrete sites. The mapper will then use the right BUFRs and BUFIOs.Article: 122908
On 2007-08-09, Mike Treseler <mike_treseler@comcast.net> wrote: |----------------------------------------------------------| |"Colin Paul Gloster wrote: | | | |> It is possible to attach screenshots to newsgroup posts.| | | |However, non-text attachments are filtered | |from usenet exchanges. An http reference to | |a graphics file works because it is a text | |pointer." | |----------------------------------------------------------| Perhaps some do, but it can be possible to propagate attachments to some news servers. E.g. some of the attachment for news:20070628162908.R82623@docenti.ing.unipi.it which I posted was available from another newsserver (e.g. HTTP://HowardK.Freenix.org/msgid.cgi?ID=118672175500 ). Regards, Colin Paul GlosterArticle: 122909
Hi, I'm using EDK/XPS 9.1.02J on Windows XP. I'm working my way through a through the document tutorial "EDK Concepts, Tools, and Techniques". I seem to have come to a problem when attempting to "Generate Libraries and BSPs". My project path has spaces in it, eg. "C:\Documents and Settings\User\My Documents\MyProject". When the make process gets to the "Running CopyFiles" stage, it fails because it is falling over the spaces in the path. An example of an error from the console: "cp: target 'Documents\MyProject/microblaze_0/libsrc/standalone_v1_00_a/' is not a directory: No such file or directory" Is there any way of trying to fool EDK into using the DOS8.3 equivalent path names? It was complaining about the ISE/EDK location during installation (as it's installed in "C:\Program Files") and so I specified "C:\Progra~1" which worked. I tried modifying the system_incl.make file, but only later realised that it is a generated file... Any suggestions would be most appreciated. I realise that this problem will disappear if I just use a path with no spaces, but I'm sure there is a workaround for this. Thanks again, PretzelX.Article: 122910
Hi Fred, XPS keeps track of the .mhs settings for each core and stores a copy for it in implementation/cache So what I usually do is to go in the implementation directory and deletes the files associated with the core. So when I work with microblaze I delete the microblaze_0_wrapper.ngc in the implementation and in implementation/cache In order to for a new system to be generated, I just touch the system.mhs file since this is a file that is used in the makefile. Now just microblaze will be regenerated when I generated a bitfile. On other option that I use with MicroBlaze is to change a parameter in the .mhs file which don't change the actual implementation. Ex. if I don't have HW debug enabled, I can freely change the number of breakpoints in the .mhs. XPS will see a difference of the parameter settings in the .mhs file compared to the cached version and will regenerate the core Göran They are stored directly under the implementaion directory and in a subdirectory called "Fred" <fred@n0spam.com> wrote in message news:46bba494$0$24750$da0feed9@news.zen.co.uk... > Every time I make a minor change to one of my local pcores I have to do a > "Clean Netlist" to ensure that the change is carried out. I find this > very painful since it then rebuilds all the other IPs. > > Is there a way I can just compile the changed file? > > Is it more efficient to use a .vhdl file or a .ngd which I can generate > with ISE. Would this save much time? >Article: 122911
This design uses the open core's I2C master. The core's CPU interface is modified from WISHBONE to AMBA/APB. The latter is done in order to test the core and its new APB interface with LEON processor. LEON is written in VHDL therefor the core's VHDL RTL design is tested. The core also contains a test bench and simulation model for slave, written in VERILOG. From the VERILOG test bench only the initialization procedure is taken and the I2C slave model is translated to VHDL. http://bknpk.no-ip.biz/I2C/leon_2.html http://bknpk.no-ip.bizArticle: 122912
Hi I want to use in my project (with Spartan3 or Cyclone2) a DDR/DDR2 DIMM module. I have chosen DDR because is avaiable and cheaper than SDR. I have no experience with memory controllers and not to big with FPGA, that's why I don't know which design solution to choose. I don't need fast data rate (least possible is enough to me) I have considered MegaCore function from Altera or solution provide by Xilinx After I read documentation to DDR/DDR2 interface core provide by Xilinx I have impression that they do it only to prove that it's possible to interface DDR with their fpgas, but they give no guarantee it will by works. Am I wrong? And MIG don't support DIMMs for Spartan3. When I compiled a DDR2 controler from MegaCore it take 3000LE. It's quite a lot. I consider too make my own DDR/DDR2 controller. I have read DDR2 specification and it seems complicated. But maybe if I make it for particular DDR2 module it will be more easier and take less LE or LUTs. Have anyone experience with solution that I mentioned? Or maybe someone may suggest me another solution? Any help is appreciated. PGWArticle: 122913
Dear Since Xilinx does not report wire utilization and technology data, I expect that Given FPGA device family : (1) There is a constant ratio of INTERCONNECT to LOGIC. (2) When amount of LOGIC increases N times, amount of INTERCONNECT increases N times. For example : Virtex-II Pro-20 contains 9280 slices and Virtex-II Pro-100 contains 44096 slices. That is, Virtex-II Pro-100 contains 4.7 times more slices. It implies that : In order to realize same ratio of INTERCONNECT to LOGIC, Virtex-II Pro-100 contains 4.7 times more interconnect than Virtex-II Pro 20. I guess that : The 'AREA' of INTERCONNECT for Virtex--II Pro 100 is MORE THAN 4.7 times larger than Virtex-II Pro. Question is that Is the AREA of INTERCONNECT for Virtex--II Pro 100 is 4.7 times larger than Virtex-II Pro?Article: 122914
Hi, I have been struggling on a Virtex II Pro in order to make the XilFatFS work properly. What I want to do is use the Compact Flash to boot the board which I did successfully by formating the CF with mkdos and also gparted using the FAT 16 format. Now I also want to use the functions fOpen, chdir, mkdir and readdir from the sysace library and I tried on a FAT 32 as the primary partition and it doesn't seem to work as the error led is still blinking but if I use the FAT 16 with or without the system.ace, it stops blinking and when I call twice mkdir it creates the dir but afterwards, doesn't seem to do much. Also, I could not make the readdir function work so if anyone had experiences with these, I would really appreciate it. Thank you, Antoine.Article: 122915
On Fri, 10 Aug 2007 04:15:09 -0700, Pasacco <pasacco@gmail.com> wrote: >Dear > >Since Xilinx does not report wire utilization and technology data, I >expect that > >Given FPGA device family : >(1) There is a constant ratio of INTERCONNECT to LOGIC. >(2) When amount of LOGIC increases N times, amount of INTERCONNECT >increases N times. > >For example : >Virtex-II Pro-20 contains 9280 slices and Virtex-II Pro-100 contains >44096 slices. >That is, Virtex-II Pro-100 contains 4.7 times more slices. > >It implies that : >In order to realize same ratio of INTERCONNECT to LOGIC, >Virtex-II Pro-100 contains 4.7 times more interconnect than Virtex-II >Pro 20. > >I guess that : >The 'AREA' of INTERCONNECT for Virtex--II Pro 100 is MORE THAN 4.7 >times larger than Virtex-II Pro. > >Question is that >Is the AREA of INTERCONNECT for Virtex--II Pro 100 is 4.7 times larger >than Virtex-II Pro? I think the logic here is flawed. If there are N elements, and the interconnect is intended to connect form any of the N elements to another of the N elements, then: if N grows, say it becomes k*N then the M interconnecting elemtns should grow to k*k*M This should not be taken as excat, but it seems to me that the interconnections don't fgrow lineraly with the logic elements. Regrads, ZaraArticle: 122916
It means.... AREA of interconnects grows super-linearly, as AREA of logic linearly grows. Thank youArticle: 122917
Thank you very much for your answer, you are totally right. This is what xilinx told me yesterday: The Embedded PPC405 is a 32bit processor architecture with 32bit register set and as such does not support 64-bit Write or Read transactions in a single cycle. Any 64-bit data read or write will be performed as two 32-bit PLB transfers. As you already know, cache transfer is 2 words (64-bit) betwen the Cache Unit and the Processor Fetch Unit. However, this is a hardware operation internal within PPC and not under control of the user except to enable/disable the cache. Additionally, a true 64bit read or write on PLB could be realised between a 64 bit Master and Slave Peripherals. Once PPC is involved, the data will always been managed as seperate 32-bit transactions.Article: 122918
Hi all, I've been targeting the general logic of Virtex-2s and Virtex-4s for years now, but I'd like to start getting into embedded stuff... specifically programming the embedded Power PCs or the Microblaze. Also, I haven't used C in a really long time. Other than getting a Embedded Development Board from xilinx, does anyone have any tips to help me learn. Any recommended training courses? Books? Websites? Anything at all.... Thanks in advance.Article: 122919
"Zara" <yozara@terra.es> wrote in message news:qgpob39hh31u3kfgmemeqashaq4p2hqa44@4ax.com... > On Fri, 10 Aug 2007 04:15:09 -0700, Pasacco <pasacco@gmail.com> wrote: > <snip> > > I think the logic here is flawed. > > If there are N elements, and the interconnect is intended to connect > form any of the N elements to another of the N elements, then: > > if N grows, say it becomes k*N > then the M interconnecting elemtns should grow to k*k*M > > This should not be taken as excat, but it seems to me that the > interconnections don't fgrow lineraly with the logic elements. > > Regrads, > > Zara I think your logic here is flawed as well. The local interconnections for each new CLB are replicated (OMUX, DOUBLE, even HEX). The long lines are simply extended though one can look at each CLB having attibuting the X and Y pitch to the next CLB of additional copper for these as well. The high end in a family shouldn't have more resources local to the CLB than the low end of the family, otherwise the software to select the routing could get pretty involved as devices are changed within a family. The possible destinations increase for each source as the part gets larger, but the structure is still similar around each CLB regardless of size. - John_HArticle: 122920
Everybody would agree that the need for interconnect grows faster than the number of things to be interconnected. Ask any urban planner or any phone company... In FPGAs, the issue is both more complex and also much simpler: More omplex: The interconenct structure in any family consists of a wide varity of different resources; direct connects, single, double, hex lines, long lines, etc. This structure is highly optimized, and is revisited every time we plan a new family. You cannot describe it with just one number. Much simpler: Within a family, the ratio od routing to logic is practically constant, mainly for softwarwe reasons. One cannot create a completely new optimized software structure for every chip size. Fundamental routability, a big issue years ago, is hardly an issue today. Routing delays are, of course, still an issue, and will always be an issue. The basic elements in an FPGA can be as fast as the ones in the most advanced dedicated chips and ASICs. It's the programmability that slows down the FPGA, but programmability is also its greatest asset... Peter Alfke On Aug 10, 7:31 am, Pasacco <pasa...@gmail.com> wrote: > It means.... > AREA of interconnects grows super-linearly, as AREA of logic linearly > grows. > Thank youArticle: 122921
Pasacco, I don't suppose that you have looked at using FPGA_EDITOR? It would answer your question. Austin (P.S. I am always amused at how people 'discover' that FPGA design is not some 'trivial task'... evidenced by the many who have tried to get into the business, and then failed.)Article: 122922
http://www.xilinx.com/support/training/abstracts/embedded-systems.htm AustinArticle: 122923
"Peter Alfke" <peter@xilinx.com> wrote in message news:1186763205.288969.56400@x35g2000prf.googlegroups.com... > Everybody would agree that the need for interconnect grows faster than > the number of things to be interconnected. Ask any urban planner or > any phone company... > > Are you sure about that Peter? I'm sure each house has one telephone wire to the exchange. All the complexity gets moved intot he exchange. So, wires are proportional to number of houses. Also, each house is on one road, has one electricity supply, one gas supply. Cheers, Syms.Article: 122924
Symon wrote: > Are you sure about that Peter? I'm sure each house has one telephone wire to > the exchange. All the complexity gets moved intot he exchange. So, wires are > proportional to number of houses. Also, each house is on one road, has one > electricity supply, one gas supply. If you want to connect two telephones, you'll need one wire. For three telephone, you'll need a switch and 3 wires. For many more telephones, you'll need a hierarchical system (in the beginning the telephone number digits itself designated the different levels of the hierarchy), if you don't want to connect each telephone with each other. This needs more wires than endpoints, maybe a logarithmic number of additional wires per endpoint, or maybe even more, if you want to handle many parallel connections (I'm not a telephone expert), in addition to the wires from the endpoints, but it doesn't increase proportional. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
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