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April 19, 2000 Hi, I'm from the U.S. I'm seeking someone that have the knowlege on programing a PCB which is in a "Stand-alone" DVD player. It's a Pioneer DV-525 dvd player. And I do have a service manual for the player. I understand that there's a existing modification for Pioneer DV-525 dvd player to codefree that would defets macrovision and CSS. Which you can program the board without having to replace the firmware or flash memory chip. According to Electronic Direct in Miami, FL. that do modification on DVD players. They said there's NO NEED of having a flash memory chip to be replace. They do it differently by re-programing the board. However, they won't tell you how in details. But they'll do it for $120.oo if I send in the dvd player to them and they'll return it within the next day. They also told me that they want me to have the original flash memory chip solder back on the PCB instead of the chip replacement that I got from England. They also told me that anyone that makes the firmware chip replacement bought it from the same japanies company that the original flash memory chip was made, and that people tried to copy others programs in the chip which turns out to be a fualty modification. Besides, the chip replacement from England is setted for region 2 discs instead of for region 1 discs. To change that, the chip from England also included a plug-in to insert it into a flat socket through a vent hole on the side of the player's cover to make multi regions. Beside the chip replacement doesn't defets the macrovision and CSS for dvd playback. No changes. I wish I would like to know how the PCB is programed because I do have a service manual for Pioneer DV-525. According to the DV-525 service manual, it shows general information TEST MODE SCREEN DISPLAY ( page 54 ) and it said to use a remote unit. ( the remote unit is CU-DV049 ) This mode should allows to program or re-program by types the chips' flash numbers on the DVDM ASSY. and regions settings. ( region 1 - 6 ) However it doesnt tell how to get to the test mode, is there a switch mode on the DVDM ASSY. on a PCB an order to displays the test mode on screen? If you know anyone who's fimilar of programing the board and how to get to the test mode display an order to re-program the board settings. Please send me an e-mail with information that you may have, would be appreciated. Thank's Eugene Cruz Seattle, Washington U.S.A. E-mail: ECruz68007@aol.com 206 - 246 - 7777Article: 22076
Call-For-Papers
Second Annual Boston SNUG 2000 (Synopsys Users Group)
Sept 20 - 22, 2000
Boston Marriot
Newton, Massachusetts
*Due to the success of our First SNUG Boston and requests from you, the
users, we have added an extra day this year to accommodate more User
presentations, Tutorials and evening events!
An Invitation to Contribute
Share your experiences... the success of our users group depends on the
active participation of users who are willing to share their experiences
with others. If you have information on high-level design methodology or
experiences with Synopsys tools that would be of interest to other
users, you are encouraged to present in one of the sessions described
below.
Submit your abstract TODAY! The Call for Papers is open from March 20
to April 28, 2000. Additional information is available at
http://www.snug-universal.org/boston/boston.htm All submissions should
be made to snug_tech@synopsys.com
Preliminary Schedule: SNUG Boston 2000
Wednesday, September 20
Morning Tutorial Sessions
Afternoon User Sessions
Evening Synopsys Night
Thursday, September 21
Morning Welcome/Introduction
Mid-Morning User Sessions
Afternoon User Sessions
Evening Vendor Fair
Friday, September 22
Morning Tutorial Sessions
Afternoon Tutorial Sessions
Preliminary topics include:
Synthesis Strategies and Experiences:
Users present ways to push Design Compiler to achieve the best results
with respect to timing, area, power and/or runtime. These techniques
will include compile options, DC variables, and HDL coding styles for
synthesis. Users share experiences with automation techniques for
synthesis. Of special interest is exploration of changes and
enhancements to Design Compiler over the last few releases. We're also
interested in user papers that discuss experiences with Library
Compiler.
Deep Submicron/Large Designs/Physical Synthesis:
This session concentrates on the unique challenges of deep submicron
design techniques that may involve large gate counts, high clock speeds,
and physical aspects. Sessions provide experience with automating
scripts for submicron design, special techniques for managing
wireloading, floorplanning, over consumption, and non-linear delay
modeling. Tell us about your design flows that tweak existing
methodologies, or create completely new methodologies to solve the
synthesis/placement iterations issues that exist in today's SOC designs.
Mixed-Signal/Low Power/Nanometer/PhysicalModeling/High Speed:
This session is different than the Physical Synthesis session, listed
above, in that it invites structured-custom IC and ASIC designers to
share how Synopsys/EPIC tools are implemented in their flows. This
session concentrates on recent and emerging challenges related to
troublesome physical effects encountered while using process
technologies 0.18um and smaller during IC design. In the race towards
high speed (GHz!) and low power (sub-volt!) designs, designers must have
solutions for accurate characterization, modeling, verification and
physical extraction.
FPGA & PLD Synthesis:
Having surveyed the user community, it was brought to our attention that
there is a desire to see more user papers on FPGA. If you have any FPGA
stories to share with us, please come forward! Concentrating on the
unique challenges of programmable logic, the tricks and techniques used
for designing and synthesizing FPGAs or PLDs will be presented.
Incremental synthesis, fanout control, and floorplanning issues relative
to FPGAs will also be part of this section.
High-Level Verification/Simulation Techniques:
The higher level a design is coded, the faster it can be simulated, thus
more verification can be done in the time-to-market window. But there
are many challenges to ensure that high-level verification also meets
the needs to ensure that you are properly testing the device. This
session calls for papers on behavioral system modeling approaches when
given design descriptions and performance goals. Also covered are
System-level strategies covering design functional verification using
HDLs and VCS or VSS. Users share experiences in developing a test bed
to verify combined hardware and software systems for large complex
designs. We're also interested in user papers that discuss experiences
with Vera and CoverMeter. Further discussion includes the
verification/simulation strategies to ensure design correctness.
Higher Levels of Abstraction/Behavioral Synthesis:
User experiences with using behavioral synthesis are explored in this
session. Topics include high-level design techniques, behavioral
scheduling, datapath synthesis, pipeline retiming, and integration with
other ASIC design and verification tools. Other topics include the
methodology for top-down design, and high-level techniques for DSP
design.
Hardware/Software Co-design:
Authors are invited to submit original papers describing recent
experiences in designing and verifying embedded processor-based ASIC/SOC
systems. This includes the methodologies used and tools required to
handle tasks of verifying both the hardware and software before physical
prototypes are available for these systems. Authors are encouraged to
share their insights on the use of the Eagle hardware/software tools,
Cyclone, VSS, and VCS from Synopsys and the overall impact on the
project. Explore system design objectives: Users experience with system
development, verification and integration.
Makefiles Methodology/Configuration Management:
This popular session addresses the increased effort to automate and
extend the synthesis process through scripting. The session includes
case studies by users who have taken advantage of the power of Make,
Perl and even Tcl to drive synthesis iterations, to extend DC Shell, and
to manage complex designs.
Design Reuse:
This session includes a practical methodology for design reuse and
Intellectual Property integration based on real-world experiences.
Issues and guidelines are explored. Does anybody really have a working
design reuse methodology in place? Let us know about it and how it
works.
Test - DFT:
This session focuses on strategies and real-world experiences
implementing a manufacturing test strategy (DFT) for large SOC-type
designs. Various SCAN and isolation techniques are explored in the
context of core-based designs. Techniques used to interface a DFT
solution (Full or Partial) with synthesis and power will be included.
Module Compiler:
This session explores the use of Module Compiler to achieve high
performance datapath designs, focusing on effective datapath synthesis
strategies, coding styles, and integration with other ASIC design tools.
User experiences with datapath synthesis are shared.
Static Timing Analysis:
This session explores strategies and user experiences using a static
verification flow, concentrating on highlights and lowlights of static
timing analysis using Primetime.
Formal Verification:
This session explores strategies and user experiences using a static
verification flow, concentrating on Formal Verification using Formality.
------------------------
Brian Kane
Boston SNUG Technical Committee Chairperson
Article: 22077Hello, I work with FPGA Express 3.3.1 (from Viewlogic, that is to say a stand alone software) For Xilinx, is Xilinx Alliance M2.1 with SP6. my target is a XCV150-4PQ240. I don't use the "don't touch" attribute, I simply use the GUI. Do you have the same warning in FpgaExpress ? The Pull up components are in the top file ? Rémi. "Jens Hildebrandt" <hil@e-technik.uni-rostock.de> a écrit dans le message news: 38FC5074.5055173D@e-technik.uni-rostock.de... > > > "Rémi SEGLIE" wrote: > > > > Hi, > > > > I was suprised when I read your mail because I used Synopsys too and it's > > work !! (I've just verified in Xilinx Editor and I see the pull up when I > > edit > > the IOB : the pull-up box is checked). > > > > "My method" is to use pull-up component perhaps your mistake is the > > connection ? > > > > My example : > > > > "C_PULLUP1: pulldown port map(O => Signal_A_Pull); > > > > Signal_A_Pull <= I_Signal_A;" > > > > where "Signal_A_Pull " is a local signal (from the architecture declarative > > part) and "I_Signal_A" a signal form the port of entity > > You'll have a warning from Synopsys : "The net I_Signal_A has more than one > > driver (FPGA-CHECK-10) but you can safely ignore it. > > > <snip> > > "Your method" was my starting point and because it didn't work (with my > Virtex-design) I started looking for other methods. > The PULLUPs dissapear after invoking Synopsys' "compile"-command > although I have set a "dont_touch" on them. > What is your target architecture and which Synopsys/Xilinx-Versions do > you use? > > JensArticle: 22078
Jean-Paul, Get an IBIS tool (www.hyperlynx.com), download the IBIS files, and click on "terminator wizard" to get the impedance of the IO. There are 15 other IBIS modeling tools, pick your favorite one. Austin Jean-Paul GOGLIO wrote: > Hi All, > > Does anyone on this group know the output impedance of a Virtex E pad using > LVTTL standard and the influence of the drive current on this impedance ? > > Thanks > > -- > J-P GOGLIO > GETRIS S.A. > 13 Chemin des Prés > 38240 Meylan > Tel : (+33) 4 76 18 52 10 > E-mail : goglio@getris.com > Fax : (+33) 4 76 18 52 01Article: 22079
Visit http://www.quicklogic.com/tools/quickcore/uart.htm Here you find a pdf file with explanations and a self extractor with a verilog and a VHDL version of a UART using the system discribed by Allan. Stefaan. * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is BeautifulArticle: 22080
Test : Please ignore...Article: 22081
Hi, I'd like to inform of a new FPGA board capable of HW/SW co-debugging capability. It can be operated under the control of the system software which has many useful functions, such as HW/SW in-circuit co-debugger, built-in logic analyzer, etc. You can use either Xilinx FPGA's or Altera FPGA's for boards. Please visit http://www.sevits.com for more info's. Cheers. Seiyang YangArticle: 22082
Hi all,
[1]
I'm writing VHDL codes using synplify (5.3.1) to interface with Altera's
LPM-RAM_IO (single IO port RAM).... I'm using Max+Plus2 9.3, device
Flek10k100e
During compilation, i encounter this warning message....
"Design doctor warning: Unknown combinatorial feedback structure detected
at primitive 'lpm_RAM_IO:9|'altram:sram|segment0_4' "
During timing simulation, it works fine... but haven't tried out on the real
hardware platform yet...
I believe the problem lies in the fact that the data bus is bidirectional.
In the VHDL module, it is always at the receiving end (config. as input)
unless it needs to write data to the RAM.... Pls advice on the warning
message.
[2]
I have a simple code below... Since j is a 12 bit counter, the execution (12
bit addition) is pretty slow. The maximum frequency this circuit can work is
ard 80+MHz on flex 10k100e-3... esp if there is an IF statement.....
To overcome this, I define a constraint
define_multicycle_path -to {j[11:0]} 3
recompile and the max frequency improves to 137MHz (in synplify 5.3.1)
I copied the edf and acf file to another directory and import to altera
max+plus2, recompile... but the timing analysis shows that the max frequency
this circuit can run is only 40+Mhz??????????
btw, I tried normal, fast & WYSIWYG, all shows frequency ard 40-50MHz!!!!!!
How can I tell explicitly max++2 that that is a multiple cycle instruction
or edf file has already taken care of that??
Pls advice. Thank you very much!!!
Regards
MK
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY test IS
PORT(
nReset : in STD_LOGIC;
MClk : in STD_LOGIC;
FIFO_Data1 : in STD_LOGIC_VECTOR(15 downto 0);
FIFO_Data2 : in STD_LOGIC_VECTOR(15 downto 0);
FIFO_DataAvail : in STD_LOGIC;
FIFO_Answer : out STD_LOGIC_VECTOR(15 downto 0);
Cntr : out STD_LOGIC_VECTOR(11 downto 0)
);
END test;
ARCHITECTURE Controller OF test IS
SIGNAL j : INTEGER RANGE 0 TO 2353;
BEGIN
MainInterface: PROCESS(nReset,MClk)
BEGIN
IF nReset='0' THEN
j<=0;
FIFO_Answer <=(OTHERS=>'0');
ELSIF (MClk'event AND MClk='0') THEN
IF FIFO_DataAvail='1' THEN
IF j=2352 THEN
j <=0;
ELSE
j<=j+1;
END IF;
FIFO_Answer <= FIFO_Data1+FIFO_Data2;
END IF;
END IF;
END PROCESS MainInterface;
Cntr <=CONV_STD_LOGIC_VECTOR(j,12);
END Controller;
Article: 22083Hi, I dont't use FPGA Express, but my Synopsys synthesis tools give me a similar warning, that my input signal "...drives wired logic.". Thats normal, because two outputs (that of the IOB and that of the PULLUP - which BTW *is* in the top entity ) are connected to the same net. This seems to get me nowhere so I will try to convince my admin to install Alliance 2.1. Even if this shouldn't help preserving the PULLUP components I can at least use the PULLUP-constraint in the .ucf-file to enable the IOB's pullup resistor (I was told about that in another answer to my question in this news group) Thanks for your help Jens "Rémi SEGLIE" wrote: > > Hello, > > I work with FPGA Express 3.3.1 (from Viewlogic, that is to say a stand alone > software) > For Xilinx, is Xilinx Alliance M2.1 with SP6. > > my target is a XCV150-4PQ240. > > I don't use the "don't touch" attribute, I simply use the GUI. > > Do you have the same warning in FpgaExpress ? > The Pull up components are in the top file ? > > Rémi. > > "Jens Hildebrandt" <hil@e-technik.uni-rostock.de> a écrit dans le message > news: 38FC5074.5055173D@e-technik.uni-rostock.de... > > > > > > "Rémi SEGLIE" wrote: > > > > > > Hi, > > > > > > I was suprised when I read your mail because I used Synopsys too and > it's > > > work !! (I've just verified in Xilinx Editor and I see the pull up when > I > > > edit > > > the IOB : the pull-up box is checked). > > > > > > "My method" is to use pull-up component perhaps your mistake is the > > > connection ? > > > > > > My example : > > > > > > "C_PULLUP1: pulldown port map(O => Signal_A_Pull); > > > > > > Signal_A_Pull <= I_Signal_A;" > > > > > > where "Signal_A_Pull " is a local signal (from the architecture > declarative > > > part) and "I_Signal_A" a signal form the port of entity > > > You'll have a warning from Synopsys : "The net I_Signal_A has more than > one > > > driver (FPGA-CHECK-10) but you can safely ignore it. > > > > > <snip> > > > > "Your method" was my starting point and because it didn't work (with my > > Virtex-design) I started looking for other methods. > > The PULLUPs dissapear after invoking Synopsys' "compile"-command > > although I have set a "dont_touch" on them. > > What is your target architecture and which Synopsys/Xilinx-Versions do > > you use? > > > > JensArticle: 22084
Hello All,
I'm using a XC95288XL-7 in a design and I have some confusion about what
Clock-to-Out timing I can expect to see. The datasheet says Tco=4.5ns and
defines it as "GCK to output valid" and this would be great.
The confusion comes in when I read the post-route timing report which says
12.7ns. I've pasted its output below.
Can anyone explain the difference to me? Is it really possible to get down
below 6ns, clock-pad-to-output-pad?
I should mention that I already have the slewrate set to fast.
Thanks in advance for your help.
----------------------------------------------------------------------------
----
Clock Pad to Output Pad (tCO) (nsec)
\ From C
\ L
\ K
\ _
\ I
\ N
\
To \------
A0 12.7
A1 12.7
A10 12.7
A11 12.7
********************************************************************
Pete Dudley
Sandia National Labs
Dept 2336 MS 0505
PO BOX 5800
Albuquerque, NM 87185
voice: 505.844.5565 fax: 505.844.2925 email: padudle@sandia.gov
http://www.sandia.gov/RADAR/sarcap.html
Signal Processing in Hardware and Software
********************************************************************
Article: 22085Pete, Are you certain that the IOB's are being used? I know in Alliance 2.1i you can open FPGA editor on the floorplanned design, and focus in on the IOB's. Take a look at yours, and check to see if the flop in the IO Pad is being used by your A Signal. There are some UCF directives as well.....which I forget off the top of my head. But first check to ensure that the IOB Flops are being used. Remember that you CAN NOT have any combinational logic after the last flop before the pin, or else the flop in the IOB will not be used. Cheers, Xanatos "Pete Dudley" <padudle@sandia.gov> wrote in message news:8dn5d6$5j1$1@sass1828.sandia.gov... > Hello All, > > I'm using a XC95288XL-7 in a design and I have some confusion about what > Clock-to-Out timing I can expect to see. The datasheet says Tco=4.5ns and > defines it as "GCK to output valid" and this would be great. > > The confusion comes in when I read the post-route timing report which says > 12.7ns. I've pasted its output below. > > Can anyone explain the difference to me? Is it really possible to get down > below 6ns, clock-pad-to-output-pad? > > I should mention that I already have the slewrate set to fast. > > Thanks in advance for your help. > > -------------------------------------------------------------------------- -- > ---- > Clock Pad to Output Pad (tCO) (nsec) > > \ From C > \ L > \ K > \ _ > \ I > \ N > \ > To \------ > > A0 12.7 > A1 12.7 > A10 12.7 > A11 12.7 > > > > ******************************************************************** > Pete Dudley > Sandia National Labs > Dept 2336 MS 0505 > PO BOX 5800 > Albuquerque, NM 87185 > voice: 505.844.5565 fax: 505.844.2925 email: padudle@sandia.gov > http://www.sandia.gov/RADAR/sarcap.html > Signal Processing in Hardware and Software > ******************************************************************** > > > > > >Article: 22086
Our lab book from GA Tech at URL http://www.amazon.com/exec/obidos/ASIN/0792386043/rapidprototofdig contains a chapter on VGA video generation and a VGA sync core on CDROM for the Altera UP1 board. It also has a character generation ROM and a simple graphics example using VHDL. We have some designs on the web at http://users.ece.gatech.edu/~hamblen/ALTERA/altera.htm gnippiks@my-deja.com wrote: > In article <8bta6v$qkc@catapult.gatech.edu>, > Anshuman Sharma <gte600f@prism.gatech.edu> wrote: > > I am designing a processor that runs the calculator game "worm". I have > > designed it in VHDL and I am going to use a Flex10k part to synthesize > > it. I want help with the VGA display. Basically if anyone can help me find > > something on how I can build a VGA module that will interact with my > > datapath and the game as a whole. > > > You may find the following page useful: > http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm > "This page contains basic information describing the use of the VGA > output port provided on the Altera UP1 Educational board. VHDL source > code for a simple VGA controller ( VgaCon ) is provided. The purpose > of VgaCon is to isolate the details of VGA signal generation from all > the other modules in a design. VgaCon allows the pixel information to > be written into its video memory using a very simple interface, while > it is alone responsible for generating the required signals for > displaying the pixel information on a VGA monitor. Thus for modules > interfacing with VgaCon, the process of drawing on the screen consists > of a request to colour a point located at any valid row and column." > (The Altera UP1 board has a FLEX10K20 on it. The VHDL code should > be re-usable.) > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 22087
I process data with a virtex and I need to send the result to a PC by a serial links. Do you know any serial input PCI boards that can receive 100Mbits/s serial input ? Using LVDS signals if possible. Thanks Marc BattyaniArticle: 22088
Jens Hildebrandt <hil@e-technik.uni-rostock.de> writes: > I dont't use FPGA Express, but my Synopsys synthesis tools give me a > similar warning, that my input signal "...drives wired logic.". Thats > normal, because two outputs (that of the IOB and that of the PULLUP - > which BTW *is* in the top entity ) are connected to the same net. > This seems to get me nowhere so I will try to convince my admin to > install Alliance 2.1. Even if this shouldn't help preserving the PULLUP > components I can at least use the PULLUP-constraint in the .ucf-file to > enable the IOB's pullup resistor (I was told about that in another > answer to my question in this news group) Did you look in the .xnf file (or the .edf, depends on your synopsys version), if the PULLUP is in there? This will show whether it's the Synthesis or the Xilinx SW. Remember, you must declare the port INOUT (and not IN only). If the port is of mode IN, and since you drive the signal internally (by the PULLUP), according to the VHDL semantics, no information may go though an IN port outwards, that is, the signal outside will not be affected, and this means, no external pullup will be inferred. chm. -- cmautner@ - Christian Mautner utanet.at - Vienna/Austria/EuropeArticle: 22089
If you are interested in developing synthesis program for FPGA/ASIC please forward your resume to me. I will pass to a startup in Silicon Valley, CA here. They have more than 5 software position (VHDL/Verilog compilers, logic optimization, Technology mapping or Good software skills like netlisters, edif writers etc) Please forward to mysorerani@hotmail.com Rao.Article: 22090
Woops, I should have also mentioned that the part I'm using is a CPLD. It only has one kind of flip-flops. You're right on FPGA's though. If the flops are not in the IOB's the clock to q can be anything.Article: 22091
The reason for the 12.7ns clock-to-q times is that I registered the control of the output enables. When I removed the register on the output enable signal I received a clock-to-q time of 5.0ns. Everything is OK now. ThanksArticle: 22092
Ian Miller wrote: > Hello, > > LavaLogic (http://www.lavalogic.com) is seeking experienced chip > designers to download a FREE beta copy of our Java to Verilog compiler. > The "Forge" allows chip designers to write high level algorithmic > descriptions of their chip directly in pure Java, then translate that > description to synthesizable Verilog. So you mean write Java with logic design in mind. I suppose that makes sense. I used to know people working on C to verilog, or C to netlist for some FPGA systems, with the thought that one could port existing C programs. In the cases that I know, C programs written for a sequential processor would not tend to generate logic with the expected parallelism. Now, java being inherently multithreaded might help, but I believe one should still write code for synthesis and not for JVM execution. -- glenArticle: 22093
In article <0A68A6C81B455F0B.3037DA0FB7BDC3EF.A16249D8B86F1CF3@lp.airnews.net>, "Marc Battyani" <Marc_Battyani@csi.com> wrote: > I process data with a virtex and I need to send the result to a PC by a > serial links. > Do you know any serial input PCI boards that can receive 100Mbits/s serial > input ? > Using LVDS signals if possible. > > Thanks > Marc Battyani > > I suppose you could overclock your 16550... But seriously, I don't know of any high speed general purpose interfaces that use LVDS. The closest thing I can think of is FireWire. Search for FireWire on the Internet to get more information. AFAIK, the XGA LCD interfaces using LVDS are 130MHz, but in this case the data is moving in the wrong direction. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22094
Marc Battyani wrote: > > I process data with a virtex and I need to send the result to a PC by a > serial links. > Do you know any serial input PCI boards that can receive 100Mbits/s serial > input ? > Using LVDS signals if possible. > > Thanks > Marc Battyani You may check IEEE-1355 100 Mbit serial point2point links. <http://www.4Links.co.uk/> <http://www.1355-association.org/> -- ===================================================== EL KOLLI Yacine | e-mail:elkolli@crf.canon.fr Canon C.R.F. | Phone: +33.(0)2.99.87.68.79 http://www.crf.canon.fr | FAX: +33.(0)2.99.84.11.30 ====================================================Article: 22095
I also have some designs that crash with internal errors unless I turn off the Quartus fitter. They run OK when I turn it off. As for the dongle problem, in the past I have seen them conflict with other dongles or a printer (if you have any of those connected). I had one system with three dongles and it only worked when they were stacked in one order - that I found by trial and error. Tim wrote: > On Thu, 30 Mar 2000 02:14:26 GMT, "M R Wheeler" > <intell-a-sys@iquest.net> wrote: > > >I am evaluating MaxPlus 9.5 and am finding that often the software can not > >seem to locate the dongle during the build process on larger designs. The > >software give me a license error message. Also, when selecting the Quartus > >fitter, I am getting internal errors (contact Altera, who never has a > >clue). Both problems occur on two different computers. Just wonder if > >anyone else is using this version yet. > > > > I haven't had any problems using our floating network license. I also > haven't had any crashes yet. Still, each new version fixes a thousand > bugs and adds a thousand more so we'll see. > > Oh, I did have to turn off the Quartus fitter to make the timing > requirement in a design that easily makes the timing requirements in > 9.3. > > Up to 25xs faster compile....the gods of marketing are feeling playful > today. > > Tim.Article: 22096
Hello all, Does anyone know if the LDVS I/O on the Virtex-E family is compatible with LVD Ultra2 SCSI? They are close, and LVD is derived from EIA-644 but I'm not quite sure if they are 100% compatible. Thank you, SteveArticle: 22097
Dear gentle persons, I'm searching for a PCI board to make material accelerators for Linux. Do you know some of this kind of board? I thank you by advance fredericArticle: 22098
Dear Gentle Persons, Does anyone know of a commercial or free version of a March II RAM or other high coverage test in VHDL or Xilinx compatible format? I could write one myself, but I would prefer to buy it. Robert Posey Raytheon Systems Company.Article: 22099
Hi!
I dont know what this Warning means Top of my head.
But there is one way, Just double click on this warning, and MaxplusII
will give you the reasons for this warning.
Also it will tell you about the seriousness of the warning, and what
steps you need to take.
As far as multicycle path or false path is concerned, i do not think
there is any way to make it known to the Altera MaxPlusII.
But i have heard ( never tried) Quartus tool, which probably has all
this features.
Rajkumar...
In article <8dlmug$m4k$1@violet.singnet.com.sg>,
"MK Yap" <mkyap@REMOVE.ieee.org> wrote:
> Hi all,
>
> [1]
>
> I'm writing VHDL codes using synplify (5.3.1) to interface with
Altera's
> LPM-RAM_IO (single IO port RAM).... I'm using Max+Plus2 9.3, device
> Flek10k100e
>
> During compilation, i encounter this warning message....
> "Design doctor warning: Unknown combinatorial feedback structure
detected
> at primitive 'lpm_RAM_IO:9|'altram:sram|segment0_4' "
>
> During timing simulation, it works fine... but haven't tried out on
the real
> hardware platform yet...
>
> I believe the problem lies in the fact that the data bus is
bidirectional.
> In the VHDL module, it is always at the receiving end (config. as
input)
> unless it needs to write data to the RAM.... Pls advice on the warning
> message.
>
> [2]
> I have a simple code below... Since j is a 12 bit counter, the
execution (12
> bit addition) is pretty slow. The maximum frequency this circuit can
work is
> ard 80+MHz on flex 10k100e-3... esp if there is an IF
statement.....
> To overcome this, I define a constraint
> define_multicycle_path -to {j[11:0]} 3
> recompile and the max frequency improves to 137MHz (in synplify 5.3.1)
>
> I copied the edf and acf file to another directory and import to
altera
> max+plus2, recompile... but the timing analysis shows that the max
frequency
> this circuit can run is only 40+Mhz??????????
> btw, I tried normal, fast & WYSIWYG, all shows frequency ard
40-50MHz!!!!!!
> How can I tell explicitly max++2 that that is a multiple cycle
instruction
> or edf file has already taken care of that??
>
> Pls advice. Thank you very much!!!
>
> Regards
> MK
>
> LIBRARY ieee ;
> USE ieee.std_logic_1164.all;
> USE ieee.std_logic_arith.all;
> USE ieee.std_logic_unsigned.all;
>
> ENTITY test IS
> PORT(
> nReset : in STD_LOGIC;
> MClk : in STD_LOGIC;
> FIFO_Data1 : in STD_LOGIC_VECTOR(15 downto 0);
> FIFO_Data2 : in STD_LOGIC_VECTOR(15 downto 0);
> FIFO_DataAvail : in STD_LOGIC;
> FIFO_Answer : out STD_LOGIC_VECTOR(15 downto 0);
> Cntr : out STD_LOGIC_VECTOR(11 downto 0)
> );
> END test;
>
> ARCHITECTURE Controller OF test IS
>
> SIGNAL j : INTEGER RANGE 0 TO 2353;
> BEGIN
>
> MainInterface: PROCESS(nReset,MClk)
> BEGIN
> IF nReset='0' THEN
> j<=0;
> FIFO_Answer <=(OTHERS=>'0');
> ELSIF (MClk'event AND MClk='0') THEN
> IF FIFO_DataAvail='1' THEN
> IF j=2352 THEN
> j <=0;
> ELSE
> j<=j+1;
> END IF;
> FIFO_Answer <= FIFO_Data1+FIFO_Data2;
> END IF;
>
> END IF;
> END PROCESS MainInterface;
>
> Cntr <=CONV_STD_LOGIC_VECTOR(j,12);
> END Controller;
>
>
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