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# Messages from 18025

Article: 18025
Subject: Re: Fineline BGAs
From: "Olaf" <Olaf_Birkeland@coldmail.com>
Date: Fri, 24 Sep 1999 10:52:42 +0200
Links: << >>  << T >>  << A >>

<steves@traclabs.com> wrote in message
news:37ea5320.168906585@client.sw.news.psi.net...
>
> Hello.  Sorry, this is not entirely FPGA related.  Has anybody used a
> 0.8mm pitch BGA on their board?  I am using the CS280 package from
> Xilinx and have some questions.  What trace/via/pad and clearances
> were used on the PCB?  Any links to guidelines on using these devices
> would be nice.  My layout guy hasn't found anything on these devices
> yet.  Thanks for your time.
>

I've done a 280-pin 0.8 mm BGA layout (not a Xilinx device......) and used
the following design rules:

* Clearance/Trace width:  0.15 mm
* Via drill: 0.3 mm (Although I've let my PCB manufacturer adjust this to
whatever will work best with the 0.55 mm via pad and the 1.6 mm card
thickness) On a thinner card, you can use a smaller drill. Drill should be >
1/6 of card thickness. Smaller drill allows smaller via pad (or better
margins).

These rules are geared towards PCB manufacturing, i.e. the largest sizes you
can have without preventing routability. But it's still not plain vanilla
stuff, so expect some additional cost. It will also be an advantage to use
solder mask via sealing to prevent solder paste shorts between pads and vias
can't claim that these rules are the best. They are anyhow the result of
discussions between my chip supplier, the PCB manufacturer and myself.

- Olaf


Article: 18026
Subject: Flex 10k: power-on initialisation of FSM. How to do?
From: micheal_thompson@my-deja.com
Date: Fri, 24 Sep 1999 10:10:28 GMT
Links: << >>  << T >>  << A >>
Hi
I have implemented a few state machines (binary encoded!)in this device
and am wondering how I get them to go to the 'init' state on power-up.
Design entry was VHDL so I'm making no assumptions on whether the FSM
init state is clear or preset. ( For example, the init state is not
always the first state in the declaration list).
As far as I understand all the Flex 10k registers will be cleared just
after configuration?
I considered an external reset-pin driven by a reset-ic. A possible
shortcoming of this though maybe that the Flex's configuration time (c.
200ms)could exceed my minimum reset pulse-width (most parts specify a
minimum 100ms pulse) so my pulse would never be seen.
Any thoughts would be appreciated!

regds
Mike

Sent via Deja.com http://www.deja.com/

Article: 18027
Subject: Re: Fineline BGAs
From: Glenn Eng <glenneng@nortelnetworks.com>
Date: Fri, 24 Sep 1999 08:43:56 -0400
Links: << >>  << T >>  << A >>


steves@traclabs.com wrote:

> Hello.  Sorry, this is not entirely FPGA related.  Has anybody used a
> 0.8mm pitch BGA on their board?  I am using the CS280 package from
> Xilinx and have some questions.  What trace/via/pad and clearances
> were used on the PCB?  Any links to guidelines on using these devices
> would be nice.  My layout guy hasn't found anything on these devices
> yet.  Thanks for your time.

We recently did a .8mm pitch design.  Although I can't quote you the
rules that were used to route the PCB, the rules we used limited a single
track between pads of the BGA.  Therefore the only way to break out the
part was to use buried/blind microvias(laser drilled) in the pad that
connected the external layer to the next internal layer.

--
Regards

Glenn Eng

glenneng@nortelnetworks.com


Article: 18028
Subject: Re: Synopsys inside Foundation 2.1i does not infer fast-adder
From: Ray Andraka <randraka@ids.net>
Date: Fri, 24 Sep 1999 08:46:45 -0400
Links: << >>  << T >>  << A >>
Xilinx has a ripple carry architecture that is faster and smaller than other
adder schemes for up to around 24-32 bits depending on design, speed-grade
and other factors.  It is faster because there is dedicated logic and
routing for the ripple carry chain which is faster than the general
interconnect and logic by an order of magnitude.

Your design apparently has 64 bit arithmetic, which makes for a very long
combinatorial ripple carry chain.  You need to either pipeline the carry
(and add skew registers to the data path) or move to a hybrid carry scheme
where you use one of the fast carry schemes (carry look-ahead, carry save or
carry skip for example) to combine partial sums from smaller arithmetic
slices.  You'll get a more compact adder without giving up speed (and
probably even gaining some) by using this hybrid scheme - again, basically
what you want to do is use the fast carry scheme to cascade smaller ripple
add segments to take advantage of the speed and density of the carry chain.
Unfortunately, the synthesizers don't currently do this, so you'll have to
modify your code to break up the adder.  If you can tolerate the latency,
the pipelining solution is smaller and less work to do.

Steve Martindell wrote:

> I'm trying to map some existing VHDL code(describing a datapath with a
> into the Virtex FPGA using Foundation2.1i on the PC.  Previously this
> data path was
> mapped to a standard ASIC library using DC(Design Compiler) on a Unix
> work station.
> When I set the clock constraint to >50MHz on the Unix version of DC, it
> inferred a "fast-
> carry" adder(used porpagate/generate terms) and the design meets timing.
>
> When I set the same clock constraint on the same VHDL code in
> Foundation2.1i
> (targetting a Virtex XVC400) it doesn't meet timing,  running somewhat
> less than
> 50MHz.  Note: the version of Synopsys Design Compiler running inside
> Foundation2.1i
> is called "FPGA Express" I believe,  and may not be the same DC that
> runs on Unix.
>
> When I reviewed the long path in the static timing analysis, it showed
> the long path
> "rippling" through 32 CLB's(each CLB =2bit adder + carryin).  This
> version of DC
> did not infer the "fast-carry" adder required to meet timing.  This is
> not a case of
> improper clock constraints because the timing analyzer reports that it
> missed the
> 50MHz target and only runs ~30MHz!
>
> Note: I do have  the following in the VHDL code:
>                                library IEEE;
>                                use IEEE.std_logic_1164.all;
>                                use IEEE.std_logic_signed.all;
>
> When Xilinx talks about fast carry generation logic apparently they mean
> generate
> a "ripple-carry" fast!?
>
> I've discussed this w/ with an engineer at Xilinx Technical Support. He
> ran a testcase
> where he described a 32-bit adder between two registers. He used the
> same code
> that I am using for the add function:
>
> SUM <= A(31 downto 0) + B(31 downto 0);
>
> with the same clock constraint on Foundation2.1i and got the same
> results: one
> big ripple-carry adder which did not meet timing.  To get around this
> problem
> I am coding the 32-bit propagate/generate fast-carry adder by hand.
> Anyone else seen this problem?
>
>          Steve Martindell
>                  s-martindell@ti.com

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18029
Subject: Problems with Xilinx Webpack 2.1
From: Klaus Falser <kfalser@durst.it>
Date: Fri, 24 Sep 1999 13:58:30 GMT
Links: << >>  << T >>  << A >>
Hello,

Does anyone use Xilinx WebPack too?
seeing it as a possibility to have always the latest fitter.

The first WebPack, based on Fitter M1.5 works fine, but the newer
versions (C.16 and C.17) do produce jedec files, which do not work.
When I fit the same EDIF file with the old fitter, they work.

From the reports it seems, that the two fitter runs produces the same
equations, but ..

Did anyone have similar problems?

Best regards
Klaus

--
Klaus Falser
Durst Phototechnik AG
I-39042 Brixen

Sent via Deja.com http://www.deja.com/

Article: 18030
Subject: test
From: Also-Antal Csaba <antalcs@mail.matav.hu>
Date: Fri, 24 Sep 1999 18:00:34 +0200
Links: << >>  << T >>  << A >>
sorry

Article: 18031
Subject: Earn free cash for only $6.00 From: "Betty Britten" <betty56@excite.com> Date: 24 Sep 1999 08:57:44 -0800 Links: << >> << T >> << A >>  Make Money for only$6.00

FORGET ALL THE OTHER SCAMS, THEY DON'T WORK, BUT THIS ONE DOES!
MAKE THOUSANDS OF  FROM JUST SIX BUX! TOTALLY FAST AND
LEGAL! HOW TO TURN $6 INTO$6,000!! OR MUCH MORE!! READING THIS
COULD CHANGE YOUR LIFE! I found this on a bulletin board and decided to try it. A
little while back, I was browsing through newsgroups, just like you are now, and came
across an article similar to this that said you could make thousands of dollars within
weeks with only an initial investment of $6.00! So I thought, "Yeah right, this must be a scam", but like most of us, I was curious, so I kept reading. Anyway, it said that you send$1.00 to each of the 6 names and address stated in the article. You then place your own
name and address in the bottom of the list at #6, and post the article in at least 200
newsgroups. (There are thousands) No catch, that was it. So after thinking it over, and
talking to a few people first, I thought about trying it. I figured: "what have I got to lose
except 6 stamps and $6.00, right?" Then I invested the measly$6.00. Well GUESS
WHAT!! within 7 days, I started getting money in the mail! I was shocked! I figured it
would end soon, but the money just kept coming in. In my first week, I made about
$25.00. By the end of the second week I had made a total of over$1,000.00! In the third
week I had over $10,000.00 and it's still growing. This is now my fourth week and I have made a total of just over$42,000.00 and it's still coming in rapidly. It's certainly worth
$6.00, and 6 stamps, I have spent more than that on the lottery!! Let me tell you how this works and most importantly, why it works....Also, make sure you print a copy of this article NOW, so you can get the information off of it as you need it. I promise you that if you follow the directions exactly, that you will start making more money than you thought possible by doing something so easy! Suggestion: Read this entire message carefully! (print it out or download it.) Follow the simple directions and watch the money come in! It's easy. It's legal. And, your investment is only$6.00 (Plus postage)
IMPORTANT: This is not a rip-off; it is not indecent; it is not illegal; and it is virtually
no risk - it really works!!!! If all of the following instructions are adhered to, you will
EXACTLY, and $50,000 or more can be yours in 20 to 60 days. This program remains successful because of the honesty and integrity of the participants. Please continue its success by carefully adhering to the instructions. You will now become part of the Mail Order business. In this business your product is not solid and tangible, it's a service. You are in the business of developing Mailing Lists. Many large corporations are happy to pay big bucks for quality lists. However, the money made from the mailing lists is secondary to the income which is made from people like you and me asking to be included in that list. Here are the 4 easy steps to success: STEP 1: Get 6 separate pieces of paper and write the following on each piece of paper "PLEASE PUT ME ON YOUR MAILING LIST." Now get 6 US$1.00 bills and place ONE inside EACH of the 6 pieces of paper so
the bill will not be seen through the envelope (to prevent thievery). Next, place one paper
in each of the 6 envelopes and seal them, MAKE SURE THAT THERE ARE ENOUGH
STAMPS ON YOUR ENVELOPES. You should now have 6 sealed envelopes, each with
a piece of paper stating the above phrase, your name and address, and a $1.00 bill. What you are doing is creating a service. THIS IS ABSOLUTELY LEGAL! You are requesting a legitimate service and you are paying for it! Like most of us I was a little skeptical and a little worried about the legal aspects of it all. So I checked it out with the U.S. Post Office (1-800-725-2161) and they confirmed that it is indeed legal! Mail the 6 envelopes to the following addresses: #1) Marcos Medrano 6581 Bellhurst Ln. - Castro Valley, CA. 94552 #2) Jeremy Ortego 8009 Katella Way Citrus Heights CA 95621 #3) Dan Hayes - 444 Snyder Hall, 206 E. Peabody Drive - Champaign, IL #4) Connie - 6276 Wismer Circle - Dublin, OH 43016 #5) Logan Parks - 316 San Carlos Circle - Lafayette, LA 70506 #6) Betty Britten PO Box 1625 - Camarillo, CA 93011-1625. STEP 2: Now take the #1 name off the list that you see above, move the other names up (6 becomes 5, 5 becomes 4, etc...) and add YOUR Name as number 6 on the list. STEP 3: Change anything you need to, but try to keep this article as close to original as possible. Now, post your amended article to at least 200 newsgroups. (I think there are close to 24,000 groups) All you need is 200, but remember, the more you post, the more money you make! ** EVERYBODY AROUND THE WORLD CAN DO IT, BUT REMEMBER TO PUT ENOUGH STAMPS ON YOUR EVELOPES!!!!** This is perfectly legal! If you have any doubts, refer to Title 18 Sec.1302 & 1341 of the Postal lottery laws. Keep a copy of these steps for yourself and, whenever you need money, you can use it again, and again. PLEASE REMEMBER that this program remains successful because of the honesty and integrity of the participants and by their carefully adhering to the directions. Look at it this way. If you are of integrity, the program will continue and the money that so many others have received will come your way. NOTE: You may want to retain every name and address sent to you, either on a computer or hard copy and keep the notes people send you. This VERIFIES that you are truly providing a service. (Also, it might be a good idea to wrap the$1 bill in dark paper to reduce the risk of mail theft.) So, as each
post is downloaded and the directions carefully followed, six members will be
reimbursed for their participation as a List Developer with one dollar each. Your name
will move up the list geometrically so that when your name reaches the #1position you
will be receiving thousands of dollars in CASH!!! What an opportunity for only $6.00 ($1.00 for each of the first six people listed above) Send it now, add your own name to
the list and you're in business! --
-DIRECTIONS ----- FOR HOW TO POST TO NEWSGROUPS------------ Step 1) You do
not need to re-type this entire letter to do your own posting. Simply put your cursor at the
beginning of this letter and drag your cursor to the bottom of this document, and select
'copy' from the edit menu. This will copy the entire letter into the computer's memory.
Step 2) Open a blank 'notepad' file and place your cursor at the top of the blank page.
From the 'edit' menu select 'paste'. This will paste a copy of the letter into notepad so that
want to do your postings in different settings, you'll always have this file to go back to.
Step 4) Use Netscape or Internet explorer and try searching for various newsgroups
(on-line forums, message boards, chat sites, discussions.) Step 5) Visit these message
boards and post this article as a new message by highlighting the text of this letter and
selecting paste from the edit menu. Fill in the Subject, this will be the header that
everyone sees as they scroll through the list of postings in a particular group, click the
post message button. You're done with your first one! Congratulations...THAT'S IT! All
you have to do is jump to different newsgroups and post away, after you get the hang of
it, it will take about 30 seconds for each newsgroup! **REMEMBER, THE MORE
NEWSGROUPS YOU POST IN (Message-boards etc.) THE MORE MONEY YOU
WILL MAKE!! BUT YOU HAVE TO POST A MINIMUM OF 200 That's it! You will
begin receiving money from around the world within days! You may eventually want to
rent a P.O.Box due to the large amount of mail you will receive. If you wish to stay
anonymous, you can invent a name to use, as long as the postman will deliver it. **JUST
MAKE SURE ALL THE ADDRESSES ARE say I receive only 5 replies (a very low
example). So then I made $5.00 with my name at #6 on the letter. Now, each of the 5 persons who just sent me$1.00 make the MINIMUM 200 postings, each with my name
at #5 and only 5 persons respond to each of the original 5, that is another $25.00 for me, now those 25 each make 200 MINIMUM posts with my name at #4 and only 5 replies each, I will bring in an additional$125.00! Now, those 125 persons turn around and post
the MINIMUM 200 with my name at #3 and only receive 5 replies each, I will make an
additional $626.00! OK, now here is the fun part, each of those 625 persons post a MINIMUM 200 letters with my name at #2 and they each only receive 5 replies, that just made me$3,125.00!!! Those 3,125 persons will all deliver this message to 200
newsgroups with my name at #1 and if still 5 persons per 200 newsgroups react I will
receive $15,625,00! With an original investment of only$6.00! AMAZING! When your
name is no longer on the list, you just take the latest posting in the newsgroups, and send
out another $6.00 to names on the list, putting your name at number 6 again. And start posting again. The thing to remember is: do you realize that thousands of people all over the world are joining the internet and reading these articles everyday?, JUST LIKE YOU are now!! So, can you afford$6.00 and see if it really works?? I think so... People have
said, "what if the plan is played out and no one sends you the money? So what! What are
the chances of that happening when there are tons of new honest users and new honest
people who are joining the internet and newsgroups everyday and are willing to give it a
try? Estimates are at 20,000 to 50,000 new users, every day, with thousands of those
joining the actual internet. Remember, play FAIRLY and HONESTLY and this will
really work. You might have already been thinking how are you going to stop people
from copying this message with their name at #6 and not sending a dollar to the first six
on there. Here's the deal. The six people own the rights to this service, now they aren't the
only ones that own these rights. To get these rights you have to purchase them from the
six people on this list. Why do you have to buy them from all 6 you ask? That's what
makes this service work. If you decide to break these rules, that's when it becomes illegal,
and that is why you must be fair to everyone! This is like, so awesome! So try it right
now! You will NOT regret it. make huge bucks in just short weeks!
Posted by   on 09/14/99 at 20:32:22 PDT
FORGET ALL THE OTHER SCAMS, THEY DON'T WORK, BUT THIS ONE DOES!
MAKE THOUSANDS OF  FROM JUST SIX BUX! TOTALLY FAST AND
LEGAL! HOW TO TURN $6 INTO$6,000!! OR MUCH MORE!! READING THIS
COULD CHANGE YOUR LIFE! I found this on a bulletin board and decided to try it. A
little while back, I was browsing through newsgroups, just like you are now, and came
across an article similar to this that said you could make thousands of dollars within
weeks with only an initial investment of $6.00! So I thought, "Yeah right, this must be a scam", but like most of us, I was curious, so I kept reading. Anyway, it said that you send$1.00 to each of the 6 names and address stated in the article. You then place your own
name and address in the bottom of the list at #6, and post the article in at least 200
newsgroups. (There are thousands) No catch, that was it. So after thinking it over, and
talking to a few people first, I thought about trying it. I figured: "what have I got to lose
except 6 stamps and $6.00, right?" Then I invested the measly$6.00. Well GUESS
WHAT!! within 7 days, I started getting money in the mail! I was shocked! I figured it
would end soon, but the money just kept coming in. In my first week, I made about
$25.00. By the end of the second week I had made a total of over$1,000.00! In the third
week I had over $10,000.00 and it's still growing. This is now my fourth week and I have made a total of just over$42,000.00 and it's still coming in rapidly. It's certainly worth
$6.00, and 6 stamps, I have spent more than that on the lottery!! Let me tell you how this works and most importantly, why it works....Also, make sure you print a copy of this article NOW, so you can get the information off of it as you need it. I promise you that if you follow the directions exactly, that you will start making more money than you thought possible by doing something so easy! Suggestion: Read this entire message carefully! (print it out or download it.) Follow the simple directions and watch the money come in! It's easy. It's legal. And, your investment is only$6.00 (Plus postage)
IMPORTANT: This is not a rip-off; it is not indecent; it is not illegal; and it is virtually
no risk - it really works!!!! If all of the following instructions are adhered to, you will
EXACTLY, and $50,000 or more can be yours in 20 to 60 days. This program remains successful because of the honesty and integrity of the participants. Please continue its success by carefully adhering to the instructions. You will now become part of the Mail Order business. In this business your product is not solid and tangible, it's a service. You are in the business of developing Mailing Lists. Many large corporations are happy to pay big bucks for quality lists. However, the money made from the mailing lists is secondary to the income which is made from people like you and me asking to be included in that list. Here are the 4 easy steps to success: STEP 1: Get 6 separate pieces of paper and write the following on each piece of paper "PLEASE PUT ME ON YOUR MAILING LIST." Now get 6 US$1.00 bills and place ONE inside EACH of the 6 pieces of paper so
the bill will not be seen through the envelope (to prevent thievery). Next, place one paper
in each of the 6 envelopes and seal them, MAKE SURE THAT THERE ARE ENOUGH
STAMPS ON YOUR ENVELOPES. You should now have 6 sealed envelopes, each with
a piece of paper stating the above phrase, your name and address, and a $1.00 bill. What you are doing is creating a service. THIS IS ABSOLUTELY LEGAL! You are requesting a legitimate service and you are paying for it! Like most of us I was a little skeptical and a little worried about the legal aspects of it all. So I checked it out with the U.S. Post Office (1-800-725-2161) and they confirmed that it is indeed legal! Mail the 6 envelopes to the following addresses: #1) Aaron Mitton-195 West Main St.-Oakley, ID 83346 #2) Marcos Medrano 6581 Bellhurst Ln. - Castro Valley, CA. 94552 #3) Jeremy Ortego 8009 Katella Way Citrus Heights CA 95621 #4) Dan Hayes - 444 Snyder Hall, 206 E. Peabody Drive - Champaign, IL #5) Connie - 6276 Wismer Circle - Dublin, OH 43016 #6) Logan Parks - 316 San Carlos Circle - Lafayette, LA 70506 STEP 2: Now take the #1 name off the list that you see above, move the other names up (6 becomes 5, 5 becomes 4, etc...) and add YOUR Name as number 6 on the list. STEP 3: Change anything you need to, but try to keep this article as close to original as possible. Now, post your amended article to at least 200 newsgroups. (I think there are close to 24,000 groups) All you need is 200, but remember, the more you post, the more money you make! ** EVERYBODY AROUND THE WORLD CAN DO IT, BUT REMEMBER TO PUT ENOUGH STAMPS ON YOUR EVELOPES!!!!** This is perfectly legal! If you have any doubts, refer to Title 18 Sec.1302 & 1341 of the Postal lottery laws. Keep a copy of these steps for yourself and, whenever you need money, you can use it again, and again. PLEASE REMEMBER that this program remains successful because of the honesty and integrity of the participants and by their carefully adhering to the directions. Look at it this way. If you are of integrity, the program will continue and the money that so many others have received will come your way. NOTE: You may want to retain every name and address sent to you, either on a computer or hard copy and keep the notes people send you. This VERIFIES that you are truly providing a service. (Also, it might be a good idea to wrap the$1 bill in dark paper to reduce the risk of mail theft.) So, as each post is downloaded
and the directions carefully followed, six members will be reimbursed for their
participation as a List Developer with one dollar each. Your name will move up the list
geometrically so that when your name reaches the #1position you will be receiving
thousands of dollars in CASH!!! What an opportunity for only $6.00 ($1.00 for each of
the first six people listed above) Send it now, add your own name to the list and you're in
business! ---DIRECTIONS ----- FOR HOW TO POST TO NEWSGROUPS------------
Step 1) You do not need to re-type this entire letter to do your own posting. Simply put
your cursor at the beginning of this letter and drag your cursor to the bottom of this
document, and select 'copy' from the edit menu. This will copy the entire letter into the
computer's memory. Step 2) Open a blank 'notepad' file and place your cursor at the top
of the blank page. From the 'edit' menu select 'paste'. This will paste a copy of the letter
as a .txt file. If you want to do your postings in different settings, you'll always have this
file to go back to. Step 4) Use Netscape or Internet explorer and try searching for various
newsgroups (on-line forums, message boards, chat sites, discussions.) Step 5) Visit these
message boards and post this article as a new message by highlighting the text of this
letter and selecting paste from the edit menu. Fill in the Subject, this will be the header
that everyone sees as they scroll through the list of postings in a particular group, click
the post message button. You're done with your first one! Congratulations...THAT'S IT!
All you have to do is jump to different newsgroups and post away, after you get the hang
of it, it will take about 30 seconds for each newsgroup! **REMEMBER, THE MORE
NEWSGROUPS YOU POST IN (Message-boards etc.) THE MORE MONEY YOU
WILL MAKE!! BUT YOU HAVE TO POST A MINIMUM OF 200 That's it! You will
begin receiving money from around the world within days! You may eventually want to
rent a P.O.Box due to the large amount of mail you will receive. If you wish to stay
anonymous, you can invent a name to use, as long as the postman will deliver it. **JUST
MAKE SURE ALL THE ADDRESSES ARE say I receive only 5 replies (a very low
example). So then I made $5.00 with my name at #6 on the letter. Now, each of the 5 persons who just sent me$1.00 make the MINIMUM 200 postings, each with my name
at #5 and only 5 persons respond to each of the original 5, that is another $25.00 for me, now those 25 each make 200 MINIMUM posts with my name at #4 and only 5 replies each, I will bring in an additional$125.00! Now, those 125 persons turn around and post
the MINIMUM 200 with my name at #3 and only receive 5 replies each, I will make an
additional $626.00! OK, now here is the fun part, each of those 625 persons post a MINIMUM 200 letters with my name at #2 and they each only receive 5 replies, that just made me$3,125.00!!! Those 3,125 persons will all deliver this message to 200
newsgroups with my name at #1 and if still 5 persons per 200 newsgroups react I will
receive $15,625,00! With an original investment of only$6.00! AMAZING! When your
name is no longer on the list, you just take the latest posting in the newsgroups, and send
out another $6.00 to names on the list, putting your name at number 6 again. And start posting again. The thing to remember is: do you realize that thousands of people all over the world are joining the internet and reading these articles everyday?, JUST LIKE YOU are now!! So, can you afford$6.00 and see if it really works?? I think so... People have
said, "what if the plan is played out and no one sends you the money? So what! What are
the chances of that happening when there are tons of new honest users and new honest
people who are joining the internet and newsgroups everyday and are willing to give it a
try? Estimates are at 20,000 to 50,000 new users, every day, with thousands of those
joining the actual internet. Remember, play FAIRLY and HONESTLY and this will
really work. You might have already been thinking how are you going to stop people
from copying this message with their name at #6 and not sending a dollar to the first six
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Article: 18032
Subject: Instanciating Altera LPMs in Leonardo Spectrum
From: "Jonah Probell" <jonah@lexra.com>
Date: Fri, 24 Sep 1999 13:34:52 -0400
Links: << >>  << T >>  << A >>
I know how to instanciate an LPM in my design using Synplify's // synthesis
black_box directive.  I am trying to compile my code in Leonardo Spectrum
for the sake of comparing the two tools.  I have been unable to find any
help on how to instanciate an Altera LPM RAM.

If anyone knows, your help would be much appreciated.


Article: 18033
Subject: Re: Modelsim,synplify,Leonardo,MAX+plus, you name it!!
From: Jabberwork <jabberwork@gmx.net>
Date: Fri, 24 Sep 1999 19:55:09 +0200
Links: << >>  << T >>  << A >>
Every good hacker can make you this keys. Even for Cadence or synopsys
but the use of this keys is not legal and you will have no support.

Jabberwork

jabberwork@gmx.net

>Can you or your company afford paying 10000$at least for these >programs ?!!? If you can then ignore this posting, otherwise I can >offer an alternative at 1/100 th of the original price. I offer perfect >solutions for small enterprizes and I would like to emphasize on >perfect. > >Just send me an e-mail to freelicenses@hotmail.com or flexlm666@my- >deja.com > > >Sent via Deja.com http://www.deja.com/ >Share what you know. Learn what you don't.  Article: 18034 Subject: Re: Synopsys inside Foundation 2.1i does not infer fast-adder From: "Andy Peters" <apeters.nospam@nospam.noao.edu.nospam> Date: Fri, 24 Sep 1999 11:37:23 -0700 Links: << >> << T >> << A >>  Steve Martindell wrote in message <37EAC358.F1F8FAF8@_nospamm_ti.com>... >I'm trying to map some existing VHDL code(describing a datapath with a >32bit adder) >into the Virtex FPGA using Foundation2.1i on the PC. Previously this >data path was >mapped to a standard ASIC library using DC(Design Compiler) on a Unix >work station. >When I set the clock constraint to >50MHz on the Unix version of DC, it >inferred a "fast- >carry" adder(used porpagate/generate terms) and the design meets timing. > >When I set the same clock constraint on the same VHDL code in >Foundation2.1i >(targetting a Virtex XVC400) it doesn't meet timing, running somewhat >less than >50MHz. Note: the version of Synopsys Design Compiler running inside >Foundation2.1i >is called "FPGA Express" I believe, and may not be the same DC that >runs on Unix. > >When I reviewed the long path in the static timing analysis, it showed >the long path >"rippling" through 32 CLB's(each CLB =2bit adder + carryin). This >version of DC >did not infer the "fast-carry" adder required to meet timing. This is >not a case of >improper clock constraints because the timing analyzer reports that it >missed the >50MHz target and only runs ~30MHz! > >Note: I do have the following in the VHDL code: > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_signed.all; > >When Xilinx talks about fast carry generation logic apparently they mean >generate >a "ripple-carry" fast!? > >I've discussed this w/ with an engineer at Xilinx Technical Support. He >ran a testcase >where he described a 32-bit adder between two registers. He used the >same code >that I am using for the add function: > >SUM <= A(31 downto 0) + B(31 downto 0); > >with the same clock constraint on Foundation2.1i and got the same >results: one >big ripple-carry adder which did not meet timing. To get around this >problem >I am coding the 32-bit propagate/generate fast-carry adder by hand. >Anyone else seen this problem? This may or may not be helpful to you because I'm using a 4013XLA part, but I ran into the same problem. I needed a 32-bit adder to work at 80 MHz, and the 1.5i tools wouldn't do it, not even with an instantiated CORE adder. When going to 2.1i, magically (same code! a <= b + c; where a, b and c are all 32-bit signed integers) it ran at > 95 MHz. I even add a level of complexity (a mux selects the sum or difference of the two input signals) and it still meets timing. I also was not concerned about overflow. This is using FPGA Express v3.2, which is what comes with 2.1i. one thing to check: is the input to the adder from a flip-flop or just the chip input pad? For instance, if you build a little test-case where a and b are the chip inputs you may have problems. My adder looks like the following: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- hooray! entity adder is port ( clk : in std_logic; reset : in std_logic; a, b : in std_logic_vector(31 downto 0); c : out std_logic_vector(31 downto 0)); end entity adder; architecture top_level of adder is signal a_s, b_s : signed (31 downto 0); signal sum : signed (31 downto 0); begin -- sync the inputs: sync : process (clk, reset) is begin if reset = '1' then a_s <= (others => '0'); b_s <= (others => '0'); elsif rising_edge (clk) then a_s <= signed(a); b_s <= signed(b); end if; end process sync; -- the adder: adder : process (clk, reset) is begin if reset = '1' then sum <= (others => '0'); elsif rising_edge (clk) then sum <= a + b; end if; end process adder; c <= std_logic_vector(sum); end architecture top_level; hope this helps, a -- ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu "Creation Science" is oxymoronic.  Article: 18035 Subject: Re: Synplfy 5.21 and 5.08a From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb) Date: Fri, 24 Sep 1999 20:29:06 GMT Links: << >> << T >> << A >> On Thu, 23 Sep 1999 18:51:58 -0700, Andrew Dauman <andrew@synplicity.com> wrote: >Stuart is a distributor of the Exemplar product, a direct competitor of >ours. No? Really Andrew? That's why my sig says who I work for and what I do. from http://www.synplicity.com/downloads/platform.html I quote: "Select r515a.exe for Windows 95, Windows98 or WindowsNT A self-extracting archive of our latest PC release." Paint me stupid, but how exactly could I misconstrue that? Whatever. Cheers Stuart An employee of Saros Technology: Model Technology, Exemplar Logic, TransEDA, Renoir. www.saros.co.uk  Article: 18036 Subject: Help for viewlogic73! From: himalayas-1@263.net Date: Sat, 25 Sep 1999 00:44:28 GMT Links: << >> << T >> << A >> hi,would someone please tell me how to export XNF file(to be used in Xilinx Foundation Series 2.1) from viewlogic(workview office 7.3) schematic files? Sent via Deja.com http://www.deja.com/ Before you buy.  Article: 18037 Subject: Re: Help for viewlogic73! From: "Adam J. Elbirt" <aelbirt@nac.net> Date: Fri, 24 Sep 1999 21:09:54 -0400 Links: << >> << T >> << A >> You have to run the Xilinx tool WIR2XNF to export your wire files to XNF format. The tool comes with Xilinx, not Viewlogic. Adam himalayas-1@263.net wrote: > hi,would someone please tell me how to export XNF > file(to be used in Xilinx Foundation Series 2.1) > from viewlogic(workview office 7.3) schematic > files? > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- "Sometimes I think the surest sign that there's intelligent life on other planets is that none of it has tried to contact us." - Calvin, "Calvin and Hobbes"  Article: 18038 Subject: Re: Help for viewlogic73! From: fliptron@netcom.com (Philip Freidin) Date: 25 Sep 1999 04:01:45 GMT Links: << >> << T >> << A >> In article <7sh5ta$vvf$1@nnrp1.deja.com>, <himalayas-1@263.net> wrote: >hi,would someone please tell me how to export XNF >file(to be used in Xilinx Foundation Series 2.1) >from viewlogic(workview office 7.3) schematic >files? I am assuming you mean F2.1i and Viewlogic Viewdraw 7.3 (part of WVO 7.3) WIR files. For this flow, you need to pass an EDIF file from Viewdraw to the F2.1i tools. Tragically, the far more easy to use and understand XNF format is being discontinued by Xilinx, although it is true that there is still XNF input possible for F2.1i, because some synthesis vendors are still producing XNF rather than EDIF. There used to be support for XNF from Viewdraw to the xilinx tools, called WIR2XNF, but this stopped being supported with Xilinx's M1 release, and Viewlogic's first release of WVO. Running WIR2XNF while still possible (under significant duress, and extremely poor performance) really makes no sesne, given the current direction and support for the EDIF path. (One real advantage of the EDIF path is it is MUCH faster than the XNF path, but that is due to problems/bugs within WIR2XNF) The following is for the WVO 7.53 version of this stuff, but it hasn't changed much. Maybe it is time for you to update your stuff? To create the EDIF file, find the EDIF button in your WVO task bar, or from the start menu. Select "EDIF Netlist Writer", for the design file, select your top level page, the output should be the same name but with an EDN extension, and in the "LEVEL" box, type "Xilinx". The Netlist option should be set to "Hierarchial". Click "Apply" It will be done pretty quickly, and should say "0 errors and 0 warnings". There is no "close" button, so click "cancel". This is stupid, and has been reported multiple times to VL, but nothing happens. The EDN file created is then the input to your F2.1i stuff. This stuff can also be run from the command line in a DOS box with a command like edifneto toppage -L xilinx in the project directory. Philip Freidin  Article: 18039 Subject: How can I use an Altera .gdf file in my text file? From: "John Becich" <johnbecich@csi.com> Date: Fri, 24 Sep 1999 21:43:27 -0700 Links: << >> << T >> << A >> I have composed a large source file using Altera's version 9.3 of Max+Plus. It is a ".tdf" file. I have used a few megafunctions in this file, by "including" the related ".inc" file for each megafunction I desired. I had to create my own FIFO circuit, because the megafunctions provided by Altera were inappropriate. I use graphic schematic entry, and saved the file as a ".gdf" file. I wanted to compile that file and simulate it by itself, but the compiler protested all the illegal inputs, outputs, etc. I would be satisfied just to put this circuit in my larger design and just simulate the whole thing. I can't figure out how to get a .gdf file into my .tdf file. Can you tell me how to do this? Thanks, John  Article: 18040 Subject: Evolvable Hardware From: "Stephen Kempenaers" <stephenk6@excite.com> Date: Sat, 25 Sep 1999 13:09:28 +0200 Links: << >> << T >> << A >> Hi, I have to write a thesis about evolvable hardware, but everywhere i look, i find other defenitions, can somebody refer me to a site where i can find detailed information about this subject thxs in advance  Article: 18041 Subject: Re: Fineline BGAs From: dss96@aol.com (DSS96) Date: 25 Sep 1999 11:27:11 GMT Links: << >> << T >> << A >> for the best advice you should contact your board house and see what they recommend. After all, they're the ones making it.  Article: 18042 Subject: Re: Altera's MaxplusII: incremental compilation From: "Dmitry Kuznetsov" <dkuzn@orc.ru> Date: 25 Sep 1999 11:35:59 GMT Links: << >> << T >> << A >> Hi! -- Possible try to add constraints in the file "*.ACF" (Assignment & Configuration File) in Max+. If beside you are saved files from the previous design, execute "Back-Annotate Project" (menu "Assign") for "Chips, Logic Cells, Pins & Devices" and carry received "*.ACF" in your new design. Possible, will come to delete or change some assignments, which touch a changeable fragment. If you can not do this (have lost necessary files) possible also try to extract these constraints from the file ".FIT" or from the file ".RPT" (from sections INPUTS, OUTPUTS and BURIED LOGIC). In this case is necessary will create a special program for automations of process (for such large design) carrying the assignments from the previous design in the new design in the manner of constraints. By! << In theory there is no difference between theory and practice. << In practice, there is. Dmitry Kuznetsov, Moscow, http://www.orc.ru/~dkuzn/index.htm -- Prashant Arora <arora@ics.uci.edu> ... > We have synthesized a design for Altera's Flex10k family fpga > (EPF10K100ABC600-1) starting from VHDL. We are using Synopsys for > synthesis and Maxplus II ver 9.25 for place and route. This returns pin > assignments for the IO ports in our design. Our FPGA is located on a PCB. > > We fixed the pin assignments and hence the PCB routing using one of the > synthesis runs that met our clock requirements (50Mhz). Subsequently, we > have discovered a bug in our design that needs a small change to > fix (adding a flip-flop). Now since the PCB routing is fixed, we have to > provide Maxplus with pin constraints (otherwise it produces a totally > different pin assignment). This causes Maxplus to give us a best case > clock of 33MHz and the p&r takes more than 10 hrs even though the change > to the design is minimal. > > 1) Is there a way to retain most of the placed and routed design from a > previous run and add a small 'patch' to the design in Maxplus without > affecting the existent placement and routing? > > 2) Is there a way in which the p&r algorithm can be made to provide the > same pin assignment as we got for the previous run without constraining it > with pin assignments?  Article: 18043 Subject: Re: basic Altera simulation questions From: "John Becich" <johnbecich@csi.com> Date: Sat, 25 Sep 1999 05:37:50 -0700 Links: << >> << T >> << A >> It worked! Thanks. John bob elkind <eteam@aracnet.com> wrote in message news:37EA8CA5.2A4FFDD2@aracnet.com... > Open .SCF file (waveform editor) > > Menu bar: File/End_time > > enter value. > > Voila! > (BTW, I agree that if you don't know where to look, it's almost > impossible to find!) You're right about that! > > -- Bob Elkind > > John Becich wrote: > > > > I am using the Altera Baseline Max+Plus software, version 9.3, as recently > > downloaded from Altera. I have designed a few state machines, and I would > > like to simulate their performance. > > > > I have created an .scf file using the Waveform Editor, and I configured it > > so that my waveform simulation would show several input and output signals, > > as found in the project .snf file (I used Node menu, Enter Nodes from SNF). > > So far, so good. > > > > I notice that the span of time covered during the simulation is 1 us (i.e., > > microsecond). I would like to change this span to me much longer, perhaps 1 > > second. I can't figure out how to do this. > > > > Could anyone please tell me what to do? > > > > ********************** > > > > I have read some of the HELP available, and it has told me to find a > > "Processing menu in the Compiler." I haven't been able to find any such > > "Processing Menu" anywhere. Can anyone tell me where to look? Or is such > > menu available only in other software than what I am using? > > > > Thanks, > > John Becich  Article: 18044 Subject: Re: Flex 10k: power-on initialisation of FSM. How to do? From: nospam_martin_thompson@yahoo.com Date: Sat, 25 Sep 1999 16:10:30 GMT Links: << >> << T >> << A >> Mike, I've used the INIT_DONE or CONF_DONE (can't remember which, I'm not at work at the mo') pins out of the 10K. If you have a signal called reset internally, feed the x_DONE pin into whichever pin this signal comes out on. The compiler usually puts it on a global input. I seem to remember needing an inverter somewhere, as some of the LPM's I was using expected an active high reset, but the DFF's didn't. Or something. If that helps, great. If not, let me know and I'll dig out some details from work (try me on martin.thompson2@lucasvarity.com for best success!) HTH, Martin On Fri, 24 Sep 1999 10:10:28 GMT, micheal_thompson@my-deja.com wrote: >Hi >I have implemented a few state machines (binary encoded!)in this device >and am wondering how I get them to go to the 'init' state on power-up. >Design entry was VHDL so I'm making no assumptions on whether the FSM >init state is clear or preset. ( For example, the init state is not >always the first state in the declaration list). >As far as I understand all the Flex 10k registers will be cleared just >after configuration? >I considered an external reset-pin driven by a reset-ic. A possible >shortcoming of this though maybe that the Flex's configuration time (c. >200ms)could exceed my minimum reset pulse-width (most parts specify a >minimum 100ms pulse) so my pulse would never be seen. >Any thoughts would be appreciated! > >regds >Mike > > >Sent via Deja.com http://www.deja.com/ >Before you buy.  Article: 18045 Subject: absolut Newbie From: "Stephan Diemer" <s.diemer@gmx.de> Date: Sat, 25 Sep 1999 19:44:58 +0200 Links: << >> << T >> << A >> Hello friends i am an absolut newbie so i dont know anything about programmable logic but i am very interested in this issue. What i want to do is building or programming a PCI card with some algorithms (for RC5 decoding). I know that it would be a wonder if i get this working so i am searching someone with the same interests who could help me or do it. If someone want to help me please visit www.ditributed.net so you will see why i want to build this and e-mail me! thanx  Article: 18046 Subject: Re: absolut Newbie From: "Steven K. Knapp" <sknapp@optimagic.com> Date: Sat, 25 Sep 1999 11:43:45 -0700 Links: << >> << T >> << A >> You may be interested in the material available on The Programmable Logic Jump Station at http://www.optimagic.com. In particular, there are some commercially-available boards that might already meet your needs (see http://www.optimagic.com/boards.html). There is also a section on the various research into reconfigurable computing (see http://www.optimagic.com/research.html). -- ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Stephan Diemer <s.diemer@gmx.de> wrote in message news:7sj1nj$g4i\$1@news.online.de...
> Hello friends i am an absolut newbie so i dont know anything about
> programmable logic but i am very interested in this issue. What i want to
do
> is building or programming a PCI card with some algorithms (for RC5
> decoding). I know that it would be a wonder if i get this working so i am
> searching someone with the same interests who could help me or do it.
> If someone want to help me please visit www.ditributed.net so you will
> see why i want to build this and e-mail me!
>
> thanx
>
>


Article: 18047
Subject: Re: Evolvable Hardware
From: Steve Holmes <sholmes@mindspring.com>
Date: Sat, 25 Sep 1999 19:19:34 -0400
Links: << >>  << T >>  << A >>
Lets see I type "Evolve FPGA Circuit" into hotbot and bingo:

2.  Adrian Thompson's Hardware Evolution Page.
Adrian Thompson Contact: COGS, University of Sussex, Brighton, BN1 9QH
UK Tel: 44 1273 678754 FAX: 44 1273 678535 email: adrianth@ :
cogs.susx.ac.uk Hardware
Evolution My main research interest is hardware evolution (also know as
evolvable..
See results from this site only.

Probably the best site there is.  Have you tried using a search
engine yourself?

Stephen Kempenaers wrote:
>
> Hi,
> I have to write a thesis about evolvable hardware, but everywhere i look, i
> find other defenitions, can somebody refer me to a site where i can find
>

--
------------------------------------------------------
Steve Holmes
sholmes@mindspring.com
http://www.mindspring.com/~sholmes

Article: 18048
Subject: Altera hierarchical design
From: "John Becich" <johnbecich@csi.com>
Date: Sat, 25 Sep 1999 21:53:48 -0700
Links: << >>  << T >>  << A >>
It seems, when one works exclusively with text entry, that in order to build
hierarchical designs using Max+Plus 9.3, one must INCLUDE
"'smaller-design'.inc";
where 'smaller-design' is the name of some lower level module that we wish
to use within the file we are building.

Simply put, that means I have to have an ".inc" file for the smaller module,
or building a hierarchical design won't work!
Does anyone agree or disagree with this observation?

Megafunctions and megafunctions that I modify seem to render .inc files OK.
I have not, however, been able to produce .inc files from the graphic or
textual files that I create from scratch, without using the "Megawizard."

Am I missing something?

Thanks,
John


Article: 18049
Subject: New to fpga's can you help
From: "Keith Tobin" <keith@suparule.com>
Date: Sun, 26 Sep 1999 08:46:02 +0100
Links: << >>  << T >>  << A >>
I want to learn VHDL to be used on fpga's , what i wand to
know is any good sites with info ,

Thanking Ye .....