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On 03/23/2010 08:26 PM, Jason Thibodeau wrote: > As I mentioned in another message, I am attempting to implement an IWLS > benchmark on a spartan3e. I wrote definitions for all the undefined > gates, and it now synthesizes just fine. > > However, I am attempting to manually place and route some main blocks in > the design. When I go into PlanAhead, I do not see my benchmark listed > in the primitives. This benchmark has an lfsr feeding it (the lfsr is > also not able to be seen in PlanAhead), and the ourputs are tied to a > signal, but are not tied to pins on the fpga. > > What am I doing wrong? I think i figured it out. If the outputs to the benchmark are not routed, the gates are being optimized out. I assigned the output vector to an output on the chip (while not actually assigning pins), and all the instances showed up after synthesis. -- Jason ThibodeauArticle: 146626
Patrick Maupin <pmaupin@gmail.com> wrote: >On Mar 23, 1:45=A0pm, n...@puntnl.niks (Nico Coesel) wrote: >> After getting used to the not so obvious layout and terms I understood >> the underlying ideas which are really nifty. > >There's a term for that: "Stockholm Syndrome" Ah, no well-founded remarks so I must be right. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 146627
> The idea of using WISHBONE was two-fold: > > 1) It's simplicity and openness > These were essentially the main characteristics that attracted me the most, even though I still didn't understand how you handle two buses with two different bus clocks, would you need a bridge between the two or is it meant to be handled by two different bus controllers? > 2) If the OpenCores community would standardise on it, we could > potentially > develop "wrappers" or "bridges" to other buses, such as AHB and OPB > for example. > I believe that wrappers or bridges will be needed only if the IP core will be hierarchically below the wishbone interface. But as jt_eaton said: > DO NOT create a wishbone interface and then place your core logic below it > in the hierarchy. If you do and then later want to support a different bus > then you are screwed. If you keep the wishbone in one module then it is > alot easier to take that module and convert it into something like a AHB > bus. and I tend to agree with his approach. In this case the IP core may have several interfaces without the need of going through a wrapper or bridge. > If you are developing an IP Core for deposit on OpenCores, it would > make sense > to use WISHBONE, if it will be technically feasible. > As far as I see it should not be so difficult and I agree that a more widely use of this standard will help a lot. I believe that universities and institutes should contribute to it the most since they are the more in need of an open environment to fully contribute at any research level. What I'm a bit skeptical about is that after almost 8 years since the last revision there hasn't been much of a spread and I would like to understand why and whether if there's something that "we", as a community, need to do in order to boost it's usage. Cheers, Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 146628
Am Sat, 20 Mar 2010 09:49:44 -0000 schrieb HT-Lab: > "Thorsten Kiefer" <info@tokis-edv-service.de> wrote in message > news:14ezponmgfjcm$.16aouitl2celg$.dlg@40tude.net... >> Am Fri, 19 Mar 2010 21:06:04 +0100 schrieb Thorsten Kiefer: >> >>> Am Fri, 19 Mar 2010 17:00:09 -0000 schrieb HT-Lab: >>> >>>> "Thorsten Kiefer" <info@tokis-edv-service.de> wrote in message >>>> news:17niij03a6nx9.1h1jj0j0b8jgk.dlg@40tude.net... >>>>> Hi, >>>>> I wrote a small example for the Digilent Spartan 3 Starter Kit. >>>>> It uses the sram to store graphics data. >>>>> Actually basing on this module I wanted to code a fractal generator. >>>>> Here is the link, maybe someone finds it useful : >>>>> http://tokis-edv-service.de/index.php/beispiele/spartan-3-example-1 >>>> >>>> Why would anybody find this useful? You only provide a bit file for one >>>> particular prototype board. I would add the code or at least add some >>>> comments >>>> on the lessons learned writing for this board. >>>> >>>> Hans >>>> www.ht-lab.com >>>> >>>> >>>>> The last test is a rather long time ago. >>>>> >>>>> Best Regards >>>>> Thorsten >>> >>> Right it's not too useful. I'll provide the code I coded myself. >>> But I cannot provide the source code, that I took from the book. >>> Thanks for the comment ! >>> >>> Thorsten >> >> I added 2 files of source now. >> Is it more useful now ? >> >> Thorsten > > Much better, however, there shouldn't be a problem listing the code from an > educational book provided you acknowledge/credit the author. > > Hans > www.ht-lab.com I contacted the author. He says that the copyright is owned by the publisher, not by himself. And the publisher denies publishing that code. Regards ThorstenArticle: 146629
On 23/03/10 12:23, jjplaw wrote:
> Newbie here. I'm running a program that invokes a tcl file. I'm trying to
> execute the xilinx tcl commands from that tcl script.
>
> In the tcl script, i only have the following code.
>
> source $env(XILINX)/bin/xilinx-init.tcl
>
> But i received the following error when the script gets invoked:
>
> error reading package index file C:/Xilinx/10.1/ISE/bin/pkgIndex.tcl: load:
> Cannot match with any static package.
> Try "load_unsupported" to load dynamic packages into statically wrapped
> applications.
> error reading package index file C:/Xilinx/10.1/ISE/bin/pkgIndex.tcl: load:
> Cannot match with any static package.
> Try "load_unsupported" to load dynamic packages into statically wrapped
> applications.
> can't find package xilinx
> while executing
> "package require xilinx"
> (file "C:\Xilinx\10.1\ISE/bin/xilinx-init.tcl" line 30)
> invoked from within
> "source $env(XILINX)/bin/xilinx-init.tcl"
> ...........
> ....
>
OK, now I understand.
I tried this on Linux (Fedora 12 with Xilinx 11.1) and it appeared to work.
So I suggest you raise the issue with Xilinx,
regards
Alan
P.S. This is what I did. The first 2 errors don't seem to have caused a
problem.
[apf@apfitch2 ~]$ tclsh
% source $env(XILINX)/bin/xilinx-init.tcl
ERROR:Scripting:2 - While trying to add a wrapper for TCL type int, an error
occured: 1. This probably means that the TCL type has already been
registered.
ERROR:Scripting:2 - While trying to add a wrapper for TCL type int, an error
occured: 1. This probably means that the TCL type has already been
registered.
% help project
Tcl command: project (create and manage projects)
The project command creates and manages ISE projects. A project contains
all files and data related to a design. You can create a project to
manage all of the design files and to enable different processes to work
on the design.
Syntax: % project <subcommand>
Project subcommands:
archive (archive all files belonging to the current ISE project)
clean (remove system-generated project files)
close (close the ISE project)
get (get project properties)
get_processes (get project processes)
new (create a new ISE project)
open (open an ISE project)
properties (list project properties)
save_as (save project as another ISE project)
set (set project properties, values, and options)
set device (set device)
set family (set device family)
set package (set device package)
set speed (set device speed)
set top (set the top-level module or entity)
For help on a particular subcommand, type:
% help project <subcommand>
%
--
Alan Fitch
Article: 146630Hi, I am planning to use a Spartan 6 FPGA (XC6SLX9) in my new design. Could someone suggest a reprogrammable PROM to configure this device, like the capacity of the Flash PROM needed ?Article: 146631
Peter wrote: > That was another unfortunate product - their windoze version could not > properly import DOS Orcad schematics (really clever). DOS Orcad was a great improvement on its successors. (with kind regards to Tony Hoare) >> We ran 4 Compaq '286s overnight to possibly get a working 30[249]0 the next morning. > > What is that? XC-3020, 3040, 3090. (regular expressions) Ooops, wasn't that a 3042, really? GerhardArticle: 146632
On Mar 24, 1:32=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > Patrick Maupin <pmau...@gmail.com> wrote: > >On Mar 23, 1:45=3DA0pm, n...@puntnl.niks (Nico Coesel) wrote: > >> After getting used to the not so obvious layout and terms I understood > >> the underlying ideas which are really nifty. > > >There's a term for that: =A0"Stockholm Syndrome" > > Ah, no well-founded remarks so I must be right. No, seriously. "After getting used to the not so obvious layout" =3D "I used to think it was crap" but then, later: "I understood the underlying ideas which are really nifty." =3D "I underwent a religious conversion." Now this is partway tongue-in-cheek, but when you start off by spouting bullshit like "I have read the other responses but what I read there is: I don't know Eclipse and I don't want to learn." I really don't know what kind of a response you expect, because that's not a real argument either, just projection about your experience. In short, that's your *interpretation* of what people wrote, and so my *response* to your provocative interpration of what others wrote is that my *interpretation* of what you wrote is that the Borg has taken over your brain. My experience is that the most highly technical people are most comfortable with an editor and a command line. A good software analogue for RTL development is something like Linux Kernel Hacking. There are several guides for this, for example: http://kernelnewbies.org/KernelHackingTools The only guides where somebody talks about using an IDE are for some embedded crap like code warrior where the vendor is pushing their IDE to people who are on the fringe of development. An IDE can be useful for somebody who doesn't want a deep understanding of some piece of code and just wants to go in and make a change. However, I don't want that person working on my hardware!!! Regards, PatArticle: 146633
On Mar 24, 3:59=A0pm, Aditi <aditi...@gmail.com> wrote: > Hi, > > I am planning to use a Spartan 6 FPGA (XC6SLX9) in my new design. > Could someone suggest a reprogrammable PROM to configure this device, > like the capacity of the Flash PROM needed ? Actually I have found a Xilinx Platform Flash XCF04S (4M bit), but could some one suggest if there is an alternative vendor who manufactures Xilinx compatible Flash PROMs of the same or higher capacity but smaller size (preferably less than 6x6mm)? Aditi.Article: 146634
Gerhard Hoffmann <usenet@hoffmann-hochfrequenz.de> wrote >Peter wrote: > > > That was another unfortunate product - their windoze version could not > > properly import DOS Orcad schematics (really clever). > >DOS Orcad was a great improvement on its successors. >(with kind regards to Tony Hoare) What happened to Orcad? Did they go the way of Protel (retreat into massively bloated $10,000 product suites which few people buy)? > >>> We ran 4 Compaq '286s overnight to possibly get a working 30[249]0 the next morning. >> >> What is that? > >XC-3020, 3040, 3090. (regular expressions) > >Ooops, wasn't that a 3042, really? I saw a 286 PC run for an hour or two, routing some small 3k device. But by the time I was doing this for real, on a 386 /486, it was much faster. How did you spread the job over four machines??Article: 146635
Aditi <aditimis@gmail.com> wrote: > Hi, > I am planning to use a Spartan 6 FPGA (XC6SLX9) in my new design. > Could someone suggest a reprogrammable PROM to configure this device, > like the capacity of the Flash PROM needed ? Use SPI Flash, like M25P32. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 146636
Patrick Maupin <pmaupin@gmail.com> wrote: >On Mar 24, 1:32=A0pm, n...@puntnl.niks (Nico Coesel) wrote: >> Patrick Maupin <pmau...@gmail.com> wrote: >> >On Mar 23, 1:45=3DA0pm, n...@puntnl.niks (Nico Coesel) wrote: >> >> After getting used to the not so obvious layout and terms I understood >> >> the underlying ideas which are really nifty. >> >> >There's a term for that: =A0"Stockholm Syndrome" >> >> Ah, no well-founded remarks so I must be right. > >No, seriously. "After getting used to the not so obvious layout" =3D "I >used to think it was crap" > >but then, later: "I understood the underlying ideas which are really >nifty." =3D "I underwent a religious conversion." > >Now this is partway tongue-in-cheek, but when you start off by >spouting bullshit like "I have read the other responses but what I >read there is: I don't know Eclipse and I don't want to learn." I >really don't know what kind of a response you expect, because that's >not a real argument either, just projection about your experience. In My experience is that people don't like change and like to stay stuck in old unproductive methods. Sometimes you need to push people forward. >to people who are on the fringe of development. An IDE can be useful >for somebody who doesn't want a deep understanding of some piece of >code and just wants to go in and make a change. However, I don't want Thats rubbish. Perhaps true for the simple IDEs intended to give people a quick start. I don't like those either. Eclipse is a whole other story though. It is designed to aid working on complex projects. I have several projects that share a common code base and some of those projects result in 10 to 20 slightly different binaries. Eclipse helps me to organize such projects. A makefile keeping all the defines and projects definitions apart would be a nightmare. And that is besides the many aids Eclipse provides like having a list of types, variables, defines and functions from a file, showing call hierarchies, shading parts that are not getting compiled, refactoring (renaming symbols), comparing versions from a version control repository, etc, etc. Ofcourse you can do all this with a command line tools but it is way less productive and more prone to errors than having everything presented to you in a GUI. I never liked developing while peeking through a key-hole. When I need to work on an software project I always load the source into Eclipse because it allows me to examine the structure of a piece of software very quickly. Where is this function called from? Just open the call hierarchy. What is this define? Just move over it with the mouse pointer. Where is the define or symbol declared? Shift-click and you'll have the answer. Open a .h file for examination by shift-clicking on it. Not to mention debugging. Its all there. And I forgot the best thing: Eclipse works the same way for different languages. Writing and debugging a C/C++ program works the same way as debugging a PHP script. Eclipse is about learning one workflow and apply it to any language. Bottom line is: I really wish Xilinx would drop ISE and move on to Eclipse. ISE is a typical example of an IDE that is intended to get a quick start but runs out of air very quickly. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 146637
Nico Coesel wrote: > My experience is that people don't like change My experience is that people apreciate things that work and does not distract them from their work. Re-learning, re-configuring, re-mastering new tools all the time is what makes engineering a terrible job today. > and like to stay stuck > in old unproductive methods. If it works, it's productive. Then why would there be a thread on comp.arch.fpga about someone selling his own old tools ? > Sometimes you need to push people forward. yeah, obsolete their tools and force them to switch, renew the license and get some more cash from the cow. > Ofcourse you can do all this with a command line tools but it is way > less productive and more prone to errors than having everything > presented to you in a GUI. but you can't automate a GUI. where is my productivity when I have to spend minutes clicking on dialogs, on boxes and on "OK" buttons everytime I recompile my VHDL in Actel's Libero ??? oh, and because it's a rather complex piece of pieces of SW, I have to _wait_ for each tool to complete, before I am allowed to click on the next dialog for the next tool in the chain. > Bottom line is: I really wish Xilinx would drop ISE and move on to > Eclipse. ISE is a typical example of an IDE that is intended to get a > quick start but runs out of air very quickly. so you propose to replace it with another ... bloated interface ? Oh yest it's based on Java so it must be much better... yg -- http://ygdes.com / http://yasep.orgArticle: 146638
As I think, many FPGA-designers have also to deal with EMC, I hope someone can help me here. We have currently some discussions (and doubts) regarding EMC-topics. As many people have different opinions on this subject, and it is quite hard to objectively verify, I would like to ask for some comments about following: 1. Filtering of IC-supply-voltage While it is quite standard to filter e.g. the PLL-supply voltages of a FPGA, there are some suggestions to filter the supply-voltage of every IC (CPU, FPGA, memory, ...) on the PCB with a ferrite-bead + C. (Consequently, this also means that every IC has it's own Vdd-island in the power-plane.) Does this work? 2. Return-path on Vdd-plane It is pretty clear that a solid ground-plane is required for return- path of I/O-signals. Most people also agree, that a power-plane will also do this job. But is this only because of the bypass-caps? Or is the "native" return-current flowing on ground when the output-driver is sinking and on Vdd when the output-driver is sourcing (assuming a high-impedance destination), i.e. it would be perfect to have both planes close to the signal-line? 3. Shields of connectors, chassis ground Most PCBs have one or more connectors with shields (e.g. USB, RJ45, VGA, RS-232,...) Do you connect these directly to circuit-ground? Or with C and R in parallel? Or do you have some kind of "frame-ground"? Have you the mounting holes grounded to the chassis? All or just one? Thanks, ThomasArticle: 146639
I have a 5 inverter ring oscillator, with its output being fed to a counter. This is run in a continuous process, that is to say it is run at 'gate speed', it is not clocked. I have an enable signal to activate the oscillator, which currently runs for 100ms. I can then clear the counter, and run it again, for 100ms. When I run this on my spartan 3e, I get different values for each and every run. I would assume these values would stay the same. What explanation is there for their differences? Power fluctuations? Any insight would be great. This is just an experiment, so no practical use. Thanks. -- Jason ThibodeauArticle: 146640
Jason Thibodeau wrote: > I have a 5 inverter ring oscillator, with its output being fed to a > counter. This is run in a continuous process, that is to say it is run > at 'gate speed', it is not clocked. I have an enable signal to activate > the oscillator, which currently runs for 100ms. I can then clear the > counter, and run it again, for 100ms. > > When I run this on my spartan 3e, I get different values for each and > every run. I would assume these values would stay the same. What > explanation is there for their differences? Power fluctuations? > > Any insight would be great. This is just an experiment, so no practical > use. Ring oscillators are VERY sensitive devices. The same old trio applies : power variations, process variations, temperature. I would expect measurements to vary by 50% or more... I'm even sure that the frequency will change by putting your fingers on the chip's surface, due to capacitive effects. Now, i'll let the specialists speak^Wwrite ;-) > Thanks. yg -- http://ygdes.com / http://yasep.orgArticle: 146641
Hi Thomas, 1) Yes. That will keep noise from coupling between devices. 2) Only nutters have power planes. They use up valuable space in which you could more profitably use a ground plane. 3) Bond it all together. Unless you have to have isolation from dangerous voltages. If anyone wants to disagree with this advice, I want a specific, first person example where what I suggest is wrong. I don't want to hear what some 'guru' told you on a course you paid for. :-) Symsx. On 3/25/2010 1:10 AM, Thomas Entner wrote: > As I think, many FPGA-designers have also to deal with EMC, I hope > someone can help me here. We have currently some discussions (and > doubts) regarding EMC-topics. As many people have different opinions > on this subject, and it is quite hard to objectively verify, I would > like to ask for some comments about following: > > 1. Filtering of IC-supply-voltage > While it is quite standard to filter e.g. the PLL-supply voltages of a > FPGA, there are some suggestions to filter the supply-voltage of every > IC (CPU, FPGA, memory, ...) on the PCB with a ferrite-bead + C. > (Consequently, this also means that every IC has it's own Vdd-island > in the power-plane.) Does this work? > > 2. Return-path on Vdd-plane > It is pretty clear that a solid ground-plane is required for return- > path of I/O-signals. Most people also agree, that a power-plane will > also do this job. But is this only because of the bypass-caps? Or is > the "native" return-current flowing on ground when the output-driver > is sinking and on Vdd when the output-driver is sourcing (assuming a > high-impedance destination), i.e. it would be perfect to have both > planes close to the signal-line? > > 3. Shields of connectors, chassis ground > Most PCBs have one or more connectors with shields (e.g. USB, RJ45, > VGA, RS-232,...) Do you connect these directly to circuit-ground? Or > with C and R in parallel? Or do you have some kind of "frame-ground"? > Have you the mounting holes grounded to the chassis? All or just one? > > Thanks, > > ThomasArticle: 146642
On Mar 24, 6:57=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > My experience is that people don't like change and like to stay stuck > in old unproductive methods. Sometimes you need to push people > forward. My experience is that learning a new tool is only worthwhile if you are going to use it a LOT and gain a LOT from it. My experience is also that a cursory examination of a tool can usually give you a reasonable feel for whether this is going to happen or not. > Thats rubbish. Perhaps true for the simple IDEs intended to give > people a quick start. I don't like those either. See, those are the ONLY ones I like. > Eclipse is a whole other story though. It is designed to aid working > on complex projects. I have several projects that share a common code > base and some of those projects result in 10 to 20 slightly different > binaries. Eclipse helps me to organize such projects. A makefile > keeping all the defines and projects definitions apart would be a > nightmare. And that is besides the many aids Eclipse provides like > having a list of types, variables, defines and functions from a file, > showing call hierarchies, shading parts that are not getting compiled, > refactoring (renaming symbols), comparing versions from a version > control repository, etc, etc. No, the nightmare is finding the configuration button to set the project exactly right. IMHO, if you delegate the complex stuff to an engine like this, you lose control over it rather than gain control. And once again, I will refer you to Linux -- is your project really more complicated, with more options, than the kernel? Do you really think all the kernel hackers are Luddites? > Ofcourse you can do all this with a command line tools but it is way > less productive and more prone to errors than having everything > presented to you in a GUI. I never liked developing while peeking > through a key-hole. When I need to work on an software project I > always load the source into Eclipse because it allows me to examine > the structure of a piece of software very quickly. Where is this > function called from? Just open the call hierarchy. What is this > define? Just move over it with the mouse pointer. Where is the define > or symbol declared? Shift-click and you'll have the answer. Open a .h > file for examination by shift-clicking on it. You haven't described anything in this paragraph that can't be done with a decent modern editor. > Not to mention debugging. Its all there. And I forgot the best thing: > Eclipse works the same way for different languages. Writing and > debugging a C/C++ program works the same way as debugging a PHP > script. Eclipse is about learning one workflow and apply it to any > language. Ahh, THERE is a difference between editors and IDEs. Yes, debugging. Well, I write most of my software in Python and spend very little time debugging. Most of my Verilog tests are self-checking, and I sometimes look at waveforms, but very little else. I don't think I have personally set a breakpoint in about 15 years, since I used to have to write C/C++, so this is not very high on my priority list (and wasn't really that high back when I WAS writing C). But I do know a lot of people who start off writing really crappy software and then debug it into shape, and most of them DO swear by their IDEs. > > Bottom line is: I really wish Xilinx would drop ISE and move on to > Eclipse. ISE is a typical example of an IDE that is intended to get a > quick start but runs out of air very quickly. While I think ISE has a lot of room for improvement, I think it's really pretty good for what I want -- get a quick start, then copy the command lines over to a real, text-based, diffable, version controlled batch environment. Having said that, the primary reason I even use ISE for this task is because some of Xilinx's documentation really, REALLY sucks. For example, try to find documentation on using impact in batch mode to generate ACE files. It exists -- as an unorganized collection of HTML one-liners designed to be invoked as help files from within impact GUI mode. Of course, one probable reason for that is that somebody started to document how impact works in batch mode, and gave up because the software sucks so badly that you can't accurately describe its behavior without calling attention to just how bad it really is. Regards, PatArticle: 146643
On Wed, 24 Mar 2010 13:59:56 -0700 (PDT), Aditi <aditimis@gmail.com> wrote: >Hi, > >I am planning to use a Spartan 6 FPGA (XC6SLX9) in my new design. >Could someone suggest a reprogrammable PROM to configure this device, >like the capacity of the Flash PROM needed ? We're using a NuMonics serial flash chip, M25P16, SO-8, 16 mbits, to program a Spartan6/45. Works fine. We just use a .BIT file in a B&K USB programmer. We actually solder the SO-8 to a small adapter board so we can plug it into a dip socket. Check the Xilinx lit to see how many config bits you need. The /45 needs around 10 mbits. For some reason I do have to erase them before I program them. I thought flash didn't need that. JohnArticle: 146644
Jason Thibodeau <jason.p.thibodeau@gmail.com> wrote: > I have a 5 inverter ring oscillator, with its output being fed to a > counter. This is run in a continuous process, that is to say it is run > at 'gate speed', it is not clocked. I have an enable signal to activate > the oscillator, which currently runs for 100ms. I can then clear the > counter, and run it again, for 100ms. > When I run this on my spartan 3e, I get different values for each and > every run. I would assume these values would stay the same. What > explanation is there for their differences? Power fluctuations? How big are the counts? If it runs at a few hundred megahertz, which might be possible, your counts are on the orders of tens of millions. If it changes by 1 part in 1e7 then the count will be different. Do this a few hundred times and graph the distribution. Also compute mean and standard deviation. -- glenArticle: 146645
On Mar 24, 9:10=A0pm, Thomas Entner <thomas.ent...@entner- electronics.com> wrote: > As I think, many FPGA-designers have also to deal with EMC, I hope > someone can help me here. We have currently some discussions (and > doubts) regarding EMC-topics. As many people have different opinions > on this subject, and it is quite hard to objectively verify, I would > like to ask for some comments about following: > > 1. Filtering of IC-supply-voltage > While it is quite standard to filter e.g. the PLL-supply voltages of a > FPGA, there are some suggestions to filter the supply-voltage of every > IC (CPU, FPGA, memory, ...) on the PCB with a ferrite-bead + C. > (Consequently, this also means that every IC has it's own Vdd-island > in the power-plane.) Does this work? > > 2. Return-path on Vdd-plane > It is pretty clear that a solid ground-plane is required for return- > path of I/O-signals. Most people also agree, that a power-plane will > also do this job. But is this only because of the bypass-caps? Or is > the "native" return-current flowing on ground when the output-driver > is sinking and on Vdd when the output-driver is sourcing (assuming a > high-impedance destination), i.e. it would be perfect to have both > planes close to the signal-line? > > 3. Shields of connectors, chassis ground > Most PCBs have one or more connectors with shields (e.g. USB, RJ45, > VGA, RS-232,...) Do you connect these directly to circuit-ground? Or > with C and R in parallel? Or do you have some kind of "frame-ground"? > Have you the mounting holes grounded to the chassis? All or just one? > > Thanks, > > Thomas 1) Filtering independent islands will help pushing VCC noise out to other chips and provide less of a radiation footprint. Another benefit for smaller islands: the resonance of that small section of board is now *much* higher in frequency. Having too many islands with too many signals jumping over the straits between land can create problems as well. 2) Return path works because of decoupling. The drivers have to be well decoupled to work so launching into power or ground referenced planes has no issue. Crossing from one plane reference to another - including changing through vias - needs a decoupling capacitor *somewhere* nearby to avoid having too large an effective antenna loop for EMI and crosstalk. A signal switching from external ground plane referenced microstrip to an internal ground and power sandwiched stripline still requires that some of the return current be shared with the power plane. If you have signals crossing between planes in the X-Y or the Z direction, decoupling needs to be nearby. There's no reason it would be perfect to have both planes nearby. The ground still has to share return current with power and vice-versa. Decoupling on-chip is common as well. I've seen information that suggests there's little effect external decoupling has on frequency content above 30MHz; on-chip resources are needed for those fast transitions. 3) Shields are one of the nastiest forms of black art. What we tended to do for the printers designed at my previous company was include spots to solder in our choice of resistor (including 0 ohm), capacitor, or ferrite. The choice was made during initial EMI scans but the island was always chassis ground through the metal mounting plate openings. I ended up having to do some expensive mechanical/electrical alterations to a board I did in a company before then because of a couple millivolts of noise injected into the COAX shield from the local ground plane. EMI was not happy. If I didn't have the fluctuation on the plane in the first place, things would have been happier.Article: 146646
On Mar 24, 9:41=A0pm, Jason Thibodeau <jason.p.thibod...@gmail.com> wrote: > I have a 5 inverter ring oscillator, with its output being fed to a > counter. This is run in a continuous process, that is to say it is run > at 'gate speed', it is not clocked. I have an enable signal to activate > the oscillator, which currently runs for 100ms. I can then clear the > counter, and run it again, for 100ms. > > When I run this on my spartan 3e, I get different values for each and > every run. I would assume these values would stay the same. What > explanation is there for their differences? Power fluctuations? > > Any insight would be great. This is just an experiment, so no practical u= se. > > Thanks. > -- > Jason Thibodeau I'm surprised you're getting such a wide variation as long as your enable guarantees one and only one edge is moving through the ring. Start with a double-check there. It might take some time for a second edge to go away. How do you have a counter that's not clocked? I used a 3-bit Gray count on the first stage of my 8-LUT ring, just in case, and my delays were pretty stable. The values I got from the single-CLB ring were around 450ps average (having spent some time to make sure the 8 inter- LUT routing delays were lowest overall). The variation was surprisingly only about 10% with freeze spray (and heat gun?); I expected a bit more. Interesting item: the delay measurement could turn the FPGA into a switch sensor: pressing the eraser tip of a pencil against the top of the package produced a noticeable change in the delay that came back when released, a change much larger than the natural variation. I used a Spartan3E starter kit and updated the LCD at probably 100ms intervals (it's been a while) to deliver my delay values visually.Article: 146647
On Mar 25, 1:41=A0pm, Jason Thibodeau <jason.p.thibod...@gmail.com> wrote: > > When I run this on my spartan 3e, I get different values for each and > every run. I would assume these values would stay the same. What > explanation is there for their differences? Power fluctuations? ?? Err ? 'stay the same' - did you really mean what you wrote ? Of course they will change. Even an Atomic clock varies... Smarter would be to post numbers on how much they changed, as 'different values' has no useful information. A ring oscillator, is a Thermometer, and a Voltmeter, and a process-quantifier - all coming out in one number. -jgArticle: 146648
> So, maybe it's just be perceived market size and/or lack of qualified > Linux driver people. =A0But if they'd just document their interface, we > could do it with libusb. =A0I'm too old to have the patience to reverse > engineer this kind of stuff any more. =A0In the same email thread two > years ago, I asked about documention, but they ignored that, and > figured (correctly) that I would forget about it if I were promised a > Linux driver a few months later. =A0But it's been two years since I > asked, and a year and a half since they said it was going to be > available. > > We've probably bought 30 or 40 of their Nexys/Nexys2 boards at work, > but they would be a lot more useful, and I'd buy a lot more, if I > could just use them from Linux. > > Regards, > Pat I've got a freeware app for Win32 that includes some public-domain code to configure the FPGA on a Nexys2 via its USB port and subsequently transfer data through it. Someone could port the nexys2.cpp module used by the TI.EXE application at http://www.ke5fx.com/gp= ib/readme.htm to Linux with a whole lot less work than it would take to build it from scratch. (The GPIB Toolkit setup program copies the source code to the same directory where it installs the executables.) Most of the work would involve porting the USB driver calls from cyusb to libusb, rather than changing anything specific to the Nexys2 itself. Similarly, the JTAG-over-USB implementation for the Cypress 8051 core would not need to be altered. I doubt it would take a Linux- literate C programmer more than a day or so to get it working. No reverse-engineering was necessary, just a lot of manual-reading and head-scratching. The Nexys2 is somewhat unique in that it comes with full schematics that tell you how to make the Cypress USB chip talk to the JTAG interface. Big two thumbs up to Digilent for making a board that people can actually use to build stuff! -- john, KE5FX From prenom.nom@gmail.com Thu Mar 25 00:46:25 2010 Path: unlimited.newshosting.com!s03-b03.iad!npeersf02.iad.highwinds-media.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!news4.google.com!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!cleanfeed3-a.proxad.net!nnrp19-1.free.fr!not-for-mail Date: Thu, 25 Mar 2010 09:46:25 +0100 From: Matthieu Michon <prenom.nom@gmail.com> Newsgroups: comp.arch.fpga Subject: Re: wishbone Message-Id: <20100325094625.c381b16b.prenom.nom@gmail.com> References: <fc3e6150-3e2b-4e9e-8d99-99078be700d4@n39g2000prj.googlegroups.com> <1Q0pn.62021$0t.53425@newsfe17.ams2> <ho5olb$mhn$1@speranza.aioe.org> <3d23e8c1-0ce3-498e-aa6c-544b21edf844@g28g2000prb.googlegroups.com> <hodqsj$c9t$1@speranza.aioe.org> X-Newsreader: Sylpheed 2.7.1 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 29 Organization: Guest of ProXad - France NNTP-Posting-Date: 25 Mar 2010 09:46:25 MET NNTP-Posting-Host: 213.215.9.6 X-Trace: 1269506785 news-1.free.fr 24353 213.215.9.6:56124 X-Complaints-To: abuse@proxad.net Xref: unlimited.newshosting.com comp.arch.fpga:99590 X-Received-Date: Thu, 25 Mar 2010 08:47:26 UTC (s03-b03.iad) On Wed, 24 Mar 2010 20:58:15 +0100 Alessandro Basili <alessandro.basili@cern.ch> wrote: (...) > > As far as I see it should not be so difficult and I agree that a more > widely use of this standard will help a lot. I believe that universities > and institutes should contribute to it the most since they are the more > in need of an open environment to fully contribute at any research level. > What I'm a bit skeptical about is that after almost 8 years since the > last revision there hasn't been much of a spread and I would like to > understand why and whether if there's something that "we", as a > community, need to do in order to boost it's usage. > Hi >From where I stand, Wishbone and Avalon (used by Altera) buses aren't so different. IMO the lack of traction of the Wishbone bus can be explained by (amongst other things): - No external devices (PHYs, memories, ...) supports Wishbone (I believe the chicken/egg issue is one the reasons). Looking at the number of open SPI/I2C/CAN cores around, such external devices would fuel the development of the Wishbone bus for sure (if the maker didn't go bankroupt yet). - A lot of design units start "simple" (not even in a dedicated unit), where a simple dataflow I/F (data, strobe, ready/busy, request/grant, ...) would due the job. It's later that using a re-usable I/C bus is thought of. These where my 2 cents. -- Matthieu Michon <prenom.nom@gmail.com>Article: 146649
John Larkin <jjlarkin@highnotlandthistechnologypart.com> wrote: > On Wed, 24 Mar 2010 13:59:56 -0700 (PDT), Aditi <aditimis@gmail.com> > wrote: > >Hi, > > > >I am planning to use a Spartan 6 FPGA (XC6SLX9) in my new design. > >Could someone suggest a reprogrammable PROM to configure this device, > >like the capacity of the Flash PROM needed ? > We're using a NuMonics serial flash chip, M25P16, SO-8, 16 mbits, to > program a Spartan6/45. Works fine. We just use a .BIT file in a B&K > USB programmer. We actually solder the SO-8 to a small adapter board > so we can plug it into a dip socket. You can also load the FPGA with some core and program the SPI Flash via JTAG with that core. This works with Impact and (sourceforge) xc3sprog. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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