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On 9/18/11 10:02 PM, Andrew Reilly wrote:
> On Sun, 18 Sep 2011 18:26:45 -0700, Bakul Shah wrote:
>
>> On 9/18/11 12:38 AM, nmm1@cam.ac.uk wrote:
>>> In article<4E74F69C.5080009@bitblocks.com>,
>>> Bakul Shah<usenet@bitblocks.com> wrote:
>>>>
>>>> I have not seen anything as elegant as CSP& Dijkstra's Guarded
>>>> commands and they have been around for 35+ years.
>>>
>>> Well, measure theory is also extremely elegant, and has been around for
>>> longer, but is not a usable abstraction for programming.
>>
>> Your original statement was
>> > Despite a lot of effort over the years, nobody has ever thought of a
>> > good way of abstracting parallelism in programming languages.
>>
>> I gave some counter examples but instead of responding to that, your
>> bring in some random assertion. If you'd used Erlang or Go and had
>> actual criticisms that would at least make this discussion interesting.
>> Ah well.
>
> I've read the language descriptions of Erlang and Go and think that both
> are heading in the right direction, in terms of practical coarse-grain
> parallelism, but I doubt that there is a compiler (for any language) that
> can turn, say, a large GEMM or FFT problem expressed entirely as
> independent agents or go-routines (or futures) into cache-aware vector
> code that runs nicely on a small-ish number of cores, if that's what you
> happen to have available. It isn't really a question of language at all:
> as you say, erlang, go and a few others already have quite reasonable
> syntaxes for independent operation. The problem is one of compilation
> competence: the ability to decide/adapt/guess vast collections of
> nominally independent operations into efficient arbitrarily sequential
> operations, rather than putting each potentially-parallel operation into
> its own thread and letting the operating system's scheduler muddle
> through it at run-time.
Now I am not sure what Nick meant by "abstracting parallelism".
I asked but he didn't clarify. I thought he meant "expressing the
essential properties of parallelism". And here I think CSP/guarded
commands do an excellent job). I think you are talking about is
"placement" -- mapping an N-parallel algorithm to a smaller number
of cores and in general making optimum use of available resources.
But these are implementation issues, not abstraction ones. I agree
that compilers have a long way to go.
Once easy to use parallel languages become widely available and we
gain some experience I am hoping that
a) better implementations will follow.
b) we will find ways to extract parallelism in the language itself
c) they will lead to much *simpler* h/w structures. Seems to me a
lot of the h/w complexity is due to wanting to dynamically extract
parallelism.
Article: 152626In article <j564dn$1l6$1@speranza.aioe.org>, glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: >In comp.arch.fpga Andrew Reilly <areilly---@bigpond.net.au> wrote: > >>> Despite a lot of effort over the years, nobody has ever thought of a >>> good way of abstracting parallelism in programming languages. > >> That's not really all that surprising though, is it? Hardware that >> exhibits programmable parallelism has taken many different forms over the >> years, especially with many different scales of granularity of the >> parallelisable sequential operations and inter-processor communications, > >Yes, but programs tend to follow the mathematics of matrix algebra. > >A language that allowed for parallel processing of matrix operations, >independent of the underlying hardware, should help. There are several. APL is one (very limited) classic, but there were quite a lot of engineering languages in the 1960s and 1970s, and then there are Matlab and modern Fortran. None of those specify parallel processing, but all allow it. Now, all of those abstract only dense, rectangular matrix algebra; sparse is a lot trickier, and others are worse still. >> The entire issue of parallelism is essentially orthogonal to the >> sequential Turing/von-Neuman model of computation that is at the heart of >> most programming languages. It's not obvious (to me) that a single >> language could reasonably describe a problem and have it map efficiently >> across "classical" cross-bar shared memory systems (including barrel >> processors), NuMA shared memory, distributed shared memory, clusters, and >> clouds (the latter just an example of the dynamic resource count vs known- >> at-compile-time axis) all of which incorporate both sequential and vector >> (and GPU-style) resources. > >Well, part of it is that we aren't so good at thinking of problems >that way. Us (people) like to think things through one step at a >time, and von-Neumann allows for that. That is the problem. I disagree that parallelism is orthogonal to the serial Von Neumann model, because there are several forms of parallelism that don't match that and some that essentially require it (in both cases, even just compared with functional). Regards, Nick Maclaren.Article: 152627
In article <9do0nhF1s4U1@mid.individual.net>, Andrew Reilly <areilly---@bigpond.net.au> wrote: > >I've read the language descriptions of Erlang and Go and think that both >are heading in the right direction, in terms of practical coarse-grain >parallelism, ... What is currently called coarse-grain parallelism isn't really an abstraction in terms of a programming interface. All of the forms I have seen are merely APIs for a collection of communicating sequential processes, for the few current communication techniques. The theoretical work isn't one, either, and is a mathematical model for reasoning about such systems. At BEST, it is the assembler of parallelism. A relevant abstraction would be comparable to procedures or arrays, both of which predate computing but have been incorporated very sucessfully as a programming model. 'Futures' are a possibility, but aren't new and didn't get very far in their previous incarnations. I don't think that ANY form of communicating sequential processes can be made into even a decent programming model, as it is far too close to the (current) hardware and far too far away from the mathematical formulation of real problems. Someone (maybe you?) mentioned networks and trees. I fully agree, and regard them as VERY badly handled by any current programming language I know of, serial or otherwise. I have some ideas on how to improve matters, but the extra generality makes the problem vastly more complicated. Regards, Nick Maclaren.Article: 152628
"Test01" <cpandya@yahoo.com> wrote in message news:5c7fd64e-6027-4e2b-adbd-fb6dba0e24f4@o15g2000vbe.googlegroups.com... >There hardware from bittec/altera at this link that takes in DVI 29 >pin connector. It seems to include analog RGB signal inputs also. So >in that case DVI connector is superset of VGA connector And this >particular board can digitize the VGA video. In other words I should >be able to use this board as a reference board. Does that make sense? >http://www.bitec.ltd.uk/hsmc_dvi_1080p_csc_c120.pdf I would strongly avoid the digitizing process if you can. If it is acceptable for you to work with digital (DVI/HDMI or Displayport), I would recommend that. The process of correctly digitizing an analogue video signal is hard to get right because finding the correct sampling frequency and phase is difficult and often a manual process. Some of the problems you will meet (especially at higher VGA resolution) are: -sampling frequency can not be directly decided without visual trial and failure -digitizing phase is cable length sensitive -bad SNR (pixels are not square at analogue level. Transmission lines are more critical than for analogue viewing).Article: 152629
Jon Elson <elson@pico-systems.com> wrote: >Nico Coesel wrote: > > >> >> IMHO this is the wrong solution. Actually it is not a solution at all. >> You really should get in touch with someone who has experience in this >> field in order to solve the problem at the root. >> >You have to understand this is a REALLY small business. I have an >old Philips pick & place machine in my basement, and reflow the boards >in a toaster oven, with a thermocouple reading temperature of the boards. >I can't afford to have a $3000 a day consultant come in, and they'd just >laugh when they saw my equipment. In that case you'll have to experiment yourself or have the boards produced by an assembly house. Soldering lead-free is more difficult to get right because the temperature tolerances are much narrower. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 152630
On Sun, 18 Sep 2011 17:18:53 -0500, Jon Elson wrote: > Jon Elson wrote: > > Hmmm, one additional tidbit. Some boards reflowed at the same time have > been stored in a lab environment. These boards in question were stored > in my basement for six months. The lab env. boards show no sign of the > whiskers. Conditions in my basement are not bad at all, but it is > likely more humid down there than in the lab. You mention humidity, but not temperature. Is there a possibility that the temperature fell below 10C during that storage period? http://en.wikipedia.org/wiki/Tin_pest#Napoleon.27s_buttons - BrianArticle: 152631
In article <9dol8bF5p6U1@mid.individual.net>, Andrew Reilly <areilly---@bigpond.net.au> wrote: > >> I have some ideas on how to improve matters, but the extra generality >> makes the problem vastly more complicated. > >I think that is a large part of the "rub": we're in what might be a local >minimum (or at least inflection) of the language space, and the trouble >with heading in what seems to be the right direction is that performance >gets significantly worse until the runtime/compilation systems are a >*lot* more sophisticated than we have at the moment. So we don't go >there, and they don't get developed. Actually, no. That's true of a lot of proposals, but I regard them as demented - because they are almost always assuming improvements in the solution to known intractable problems. My ideas are very different, but would involve programmers changing their approaches to mapping mathematics into code! I don't think that efficiency is necessarily a problem. >Someone is probably working on the right answer, somewhere, already. If >I can imagine it then brighter people than me are bound to be giving it a >go: my first rule of the internet... It is vanishingly unlikely that there IS a 'right answer', any more than there is for serial languages. Also, I don't believe in simple solutions to known intractable problems, though they do occasionally arise. Regards, Nick Maclaren.Article: 152632
On Mon, 19 Sep 2011 08:01:52 +0100, nmm1 wrote: > I have some ideas on how to improve matters, but the extra generality > makes the problem vastly more complicated. I think that is a large part of the "rub": we're in what might be a local minimum (or at least inflection) of the language space, and the trouble with heading in what seems to be the right direction is that performance gets significantly worse until the runtime/compilation systems are a *lot* more sophisticated than we have at the moment. So we don't go there, and they don't get developed. Someone is probably working on the right answer, somewhere, already. If I can imagine it then brighter people than me are bound to be giving it a go: my first rule of the internet... Cheers, -- AndrewArticle: 152633
I reply to myself as I asked the same question on a Xilinx forum and got an= answer. IBUF_DLY_ADJ is only available on the combinational path of the IOB. This i= s maybe not so obvious from the simplified IOB block diagram, but ug331 fig= ure 10.10 and the text following it clearly states this. In my case, I will= have to use the IFD_DELAY_VALUE. --=20 SvennArticle: 152634
"Brian Drummond" <brian@shapes.demon.co.uk> wrote in message news:j575ot$d20$1@dont-email.me... > On Sun, 18 Sep 2011 17:18:53 -0500, Jon Elson wrote: > >> Jon Elson wrote: >> >> Hmmm, one additional tidbit. Some boards reflowed at the same time have >> been stored in a lab environment. These boards in question were stored >> in my basement for six months. The lab env. boards show no sign of the >> whiskers. Conditions in my basement are not bad at all, but it is >> likely more humid down there than in the lab. > > You mention humidity, but not temperature. Is there a possibility that > the temperature fell below 10C during that storage period? > > http://en.wikipedia.org/wiki/Tin_pest#Napoleon.27s_buttons I guess stress on the pads are also a parameter that may influence growth of whiskers..Article: 152635
On Sep 19, 2:09=A0am, Bryan <bryan.fletc...@avnet.com> wrote: > The Avnet-designed Virtex-6 LX130T Evaluation Kit is no longer > available. =A0The ML605 has PCIe and SFP. > =A0www.xilinx.com/ml605 Thanks, the ML605 might be a good starting point. I should have been more specific, SFP+ is what is needed for 10G, and the ML605 doesn't have that. It looks like there are not a lot of Virtex-6 off the shelf board suppliers out there. What about the Altera Stratix IV, does it have a larger supplier base?Article: 152636
Can anyone steer me in the right direction of an article how one is meant to determine if a SIM card is of the 1.8V, or the 3V variety? Many thanks in advance. -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.ukArticle: 152637
>What about the Altera Stratix IV, does it have a larger supplier base? Why not checking www.altera.com?Article: 152638
rupertlssmith@googlemail.com <rupertlssmith@googlemail.com> wrote: > What about the Altera Stratix IV, does it have a larger supplier base? There's the Terasic DE4 board <http://tinyurl.com/5uvky9r> which you can combine with this mezzanine card: <http://tinyurl.com/6dov782> -aArticle: 152639
On Sep 19, 8:42=A0am, "rupertlssm...@googlemail.com" <rupertlssm...@googlemail.com> wrote: > On Sep 19, 2:09=A0am, Bryan <bryan.fletc...@avnet.com> wrote: > > > The Avnet-designed Virtex-6 LX130T Evaluation Kit is no longer > > available. =A0The ML605 has PCIe and SFP. > > =A0www.xilinx.com/ml605 > > Thanks, the ML605 might be a good starting point. I should have been > more specific, SFP+ is what is needed for 10G, and the ML605 doesn't > have that. > > It looks like there are not a lot of Virtex-6 off the shelf board > suppliers out there. > > What about the Altera Stratix IV, does it have a larger supplier base? In order to interface with a 10G SFP+ module you will need a board that uses the Virtex-6 HXT family. Xilinx did not release Virtex-6 HXT board with both PCIe and SFP+ capabilities. Ed McGettigan -- Xilinx Inc.Article: 152640
On 09/19/2011 03:28 AM, Nico Coesel wrote: > In that case you'll have to experiment yourself or have the boards > produced by an assembly house. Soldering lead-free is more difficult > to get right because the temperature tolerances are much narrower. > I've been doing lead-free boards on my commercial products, and after some trouble, mostly with solder wetting, I now have the process working quite well. But, the boards have to be made with FR-406 and lead-free finish to make it work. Since the research products I make are intended to have a much longer operating life (like 20+ years) I have been making them with Sn/Pb solder, but components are very hard to get in this finish. Anyway, these existing boards were not made for lead-free temperatures, and so I CAN'T run them at 250 C or they will likely delaminate. JonArticle: 152641
On 09/19/2011 05:33 AM, Brian Drummond wrote: > On Sun, 18 Sep 2011 17:18:53 -0500, Jon Elson wrote: > >> Jon Elson wrote: >> >> Hmmm, one additional tidbit. Some boards reflowed at the same time have >> been stored in a lab environment. These boards in question were stored >> in my basement for six months. The lab env. boards show no sign of the >> whiskers. Conditions in my basement are not bad at all, but it is >> likely more humid down there than in the lab. > > You mention humidity, but not temperature. Is there a possibility that > the temperature fell below 10C during that storage period? > Nope, no way. This is a living space, and I am in there for several hours every day. Temps below 20 C might be possible, but not below that. JonArticle: 152642
On Mon, 19 Sep 2011 18:14:22 +0100, Mike Perkins wrote: > Can anyone steer me in the right direction of an article how one is > meant to determine if a SIM card is of the 1.8V, or the 3V variety? > > Many thanks in advance. A few minutes search found this datasheet... http://www.ti.com/lit/ds/symlink/txs02326.pdf which says... "Configure the SIM1 regulator to 1.8V" ... "If there is lack of communication ... the SIM1 interface must be powered- down and then ... configuring it to 2.95V" I suppose it works. - BrianArticle: 152643
On 20/09/2011 10:26, Brian Drummond wrote: > On Mon, 19 Sep 2011 18:14:22 +0100, Mike Perkins wrote: > >> Can anyone steer me in the right direction of an article how one is >> meant to determine if a SIM card is of the 1.8V, or the 3V variety? >> >> Many thanks in advance. > > A few minutes search found this datasheet... > http://www.ti.com/lit/ds/symlink/txs02326.pdf > which says... > > "Configure the SIM1 regulator to 1.8V" ... > "If there is lack of communication ... the SIM1 interface must be powered- > down and then ... configuring it to 2.95V" > > I suppose it works. > > - Brian > Many thanks. I had already spend far more than a few minutes searching and believed there might have been a more subtle way of finding out, rather than a "does it work at 1.8V, and if not, let's try at 3V"!! -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.ukArticle: 152644
On 9/18/2011 3:31 PM, Nico Coesel wrote: > Jon Elson<elson@pico-systems.com> wrote: > >> Jon Elson wrote: >> >> Hmmm, one additional tidbit. Some boards reflowed at the >> same time have been stored in a lab environment. These boards >> in question were stored in my basement for six months. The lab env. boards >> show no sign of the whiskers. Conditions in my basement are >> not bad at all, but it is likely more humid down there than >> in the lab. So, I guess this means don't store lead-free >> boards in humid conditions. > > IMHO this is the wrong solution. Actually it is not a solution at all. > You really should get in touch with someone who has experience in this > field in order to solve the problem at the root. There is a really good reason why the Aerospace and Military have been exempted from the ROHS mandates. That's because under extreme environments (maybe including humid basements), ROHS doesn't work well. It is well known that it grows Tin Whiskers. It is a real PITA for those industries because suppliers would rather drop the old parts. Every component gets a review by our manufacturing experts to determine if it compatible with our soldering processes. Sometimes we go to the trouble of 're-balling' parts to get the 'right' kind of solder that is known to work. Sometimes they just reject the component outright and tell us to find another one... By all means you should understand your issue - maybe there is room for some process improvement. I'm just suspicious that there is no solution, yet. Rob.Article: 152645
Hello all, I'm just starting into FPGA's, and have access to a Spartan-3 Starter board. Even though it dates back to 2004 and is no longer supported by Xilinx, I expect I should be able to at least learn some fundamentals of VHDL, or Verilog HDL, and a bit more, like just to get a simple 4-digit hex up/down counter, controlled by switches. My lap top doesn't have a parallel port to comunicate with it. I've also downloaded Xilinx's WebPack v 13.2, and installed it, but because of obsolence, I don't see this kit listed in the platform menu in the project setup. What could suggest that I read to quickly get going with this toy, and get a good idea of the big picture? Digital logic circuits, C programming, DSPs, etc. are not new to me, but FPGAs are. Thanks very much, AleksArticle: 152646
On 09/22/2011 06:09 AM, alekceywk wrote: > Hello all, > > I'm just starting into FPGA's, and have access to a Spartan-3 Starter > board. Even though it dates back to 2004 and is no longer supported > by Xilinx, I expect I should be able to at least learn some > fundamentals of VHDL, or Verilog HDL, and a bit more, like just to get > a simple 4-digit hex up/down counter, controlled by switches. My lap > top doesn't have a parallel port to comunicate with it. I've also > downloaded Xilinx's WebPack v 13.2, and installed it, but because of > obsolence, I don't see this kit listed in the platform menu in the > project setup. What could suggest that I read to quickly get going > with this toy, and get a good idea of the big picture? Digital logic > circuits, C programming, DSPs, etc. are not new to me, but FPGAs are. > > Thanks very much, > > Aleks Hi Aleks, I started with pretty much the same kit a few years back. Take a look at digilentinc.com, they have a couple of very inexpensive options for USB programmers. One is compatible with the Xilinx official USB programmer, and the other is proprietary to Digilent Inc, which I was originally avoiding because it lacked Linux support, but they have recently included Linux support, so there is no need for a parallel port regardless of which OS you are on! Before the cheap USB ones were available I had to use an expresscard parallel port for my old laptop, sadly. As for compatibility with ISE 13, I don't believe you are going to have a problem getting the Spartan 3 to work, it is not yet phased out. On the other hand, I designed a board with a Virtex 2 on it about two years ago only to find that the family got dropped from ISE from 11 on, and I had to go back to ISE 10 to program it. Basically ISE/webpack does not include "support" for specific dev boards, but rather for the actual chip that is on that board. Depending where you got the board from, it will be either XC3S200 or XC3S1000 in a 256 pin package. So when you create your project, you can select that from the Spartan 3 family. Then, you will need to add your pin assignments to a .ucf (user constraints file) which will be included in your project. You can find out what the correct pin assignments are for the on board clock, each LED, switch, etc. in the user manual for the starter kit. Also, please be sure to learn how to write testbenches and simulate your designs before downloading them to an FPGA. It will save you a lot of headaches to see that your design is working right first! I hope that helps! Steve BattazzoArticle: 152647
On 21 Sep., 23:09, alekceywk <alekce...@gmail.com> wrote: > Hello all, > > I'm just starting into FPGA's, and have access to a Spartan-3 Starter > board. =A0Even though it dates back to 2004 and is no longer supported > by Xilinx, I expect I should be able to at least learn some > fundamentals of VHDL, or Verilog HDL, and a bit more, like just to get > a simple 4-digit hex up/down counter, controlled by switches. =A0My lap > top doesn't have a parallel port to comunicate with it. =A0I've also > downloaded Xilinx's WebPack v 13.2, and installed it, but because of > obsolence, I don't see this kit listed in the platform menu in the > project setup. What could suggest that I read to quickly get going > with this toy, and get a good idea of the big picture? =A0Digital logic > circuits, C programming, DSPs, etc. are not new to me, but FPGAs are. > > Thanks very much, > > Aleks Hi Aleks, The platform selection menu is new in ISE 13.x. But like before you can select the desiret target device manually. Just look in the S3-Starter board documentation for details about FPGA type, case and speed grade. Have a nice synthesis EilertArticle: 152648
Hi, I am using xilinx spartan3 xc3s4000 in my design. It is interfaced with 2 national Gigabit PHYs. So i receive a packet from phy A and transmit it to PHY B and vice versa. Now the problem i am facing is that one of the bytes in the packet randomly gets corrupt after a while.. First the packet drop was very frequent at high speeds, then i checked the power requirements of my PHYs and got to know that my regulator couldn't source that much current. Then i changed the regulator and now the problem occurs very rarely or it doesnt occur at all. I have some checks in the RTL to identify if the error is FCS or buffer overflow.So every time the packet drops, my fcs flag is raised. So i viewed the incoming packet and saw that it always had some random corrupt byte. Like i was sending packets with known pattern, so after a while some random byte is getting corrupt. I don't know what to look for from now onwards. I thought maybe it was the heat issue so used heat gun but nah it wasn't the heat problem. My ground noise is 80mv peak-to-peak. Need some pointers.. Regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152649
the xilinx says it has 500,000 gates, the altera says it has 22,320 Logic elements (LEs) 594 Embedded memory (Kbits) 66 Embedded 18 x 18 multipliers 4 General-purpose PLLs so are these two fpga's comparable in size/ computing power/ ability to support the same VHDL or what?
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