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Messages from 70925

Article: 70925
Subject: Re: Altera SOPC Master Peripheral Design?
From: pinod01@sympatico.ca (Pino)
Date: 1 Jul 2004 14:30:52 -0700
Links: << >>  << T >>  << A >>
Jesse,

    I sent you an e-mail directly but in case I would like to see
those system files if you have them.  Although my suspicion is that
your file contains a NIOS master(cpu) which will function correctly
and allow SOPC builder to automatically connect the interfaces
seemlinglessly.  However, I did not experience this with my designed
Master.  All controllers (slave peripherals) used are directly from
Altera taken from within the SOPC builder system content menu.  I am
aware of the two modes to configure the SDRAM, but neither functions
correctly with my master peripheral; however, only with the cpu (NIOS)
does it automatically connect with no errors.  The question I still
ponder on is that whether you can indeed design a Master peripheral
using the Avalon Bus or does SOPC builder by default assume that the
only Master peripheral for the automatic connectivity is the "cpu" (ie
NIOS)?   If you have a chance I sent you my Master.vhd file and you
can monitor the error I'm getting.  Again, it's for this reason why I
have hypothesized my comment in the latter.  Don't know if I have done
something erroneous.

Regards,
Pino

kempaj@yahoo.com (Jesse Kempa) wrote in message news:<95776079.0406300951.753e78cb@posting.google.com>...
> pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0406291101.30563548@posting.google.com>...
> <snip>
> > 
> > tri_state_bridge_0/avalon_slave is not connected to any Master. 
> > Please connect it to a master of type avalon.
> > 
> > Note that the Master peripheral defined is of type avalon and so is
> > the SDRAM controller (as defined within the Memory devices in the
> > System Contents directory tree).
> > 
> > Can someone explain how I can properly connect a Master peripheral
> > (user-defined of course) to the SDRAM controller slave?   Why does the
> > tristate bridge not allow this connection to occur?
> > 
> > P.S.  If this same excercise is done using a NIOS processor master +
> > tristate bridge + SDRAM controller everything is connected with no
> > errors.  The only difference that I see is that my Master is a
> > user-defined peripheral.
> > 
> > 
> > Regards,
> > Pino
> 
> Hi Pino,
> 
> I believe the problem here is because of the various ways you can
> construct a system with SDRAM. First, are you using Altera's SDRAM
> controller that comes with Nios/SOPC Builder? Our controller has two
> modes of operation with respect to its external pins:
> 
> 1. No pin 'sharing'. This is the default behavior, and is what you'd
> select if your board had I/O pins dedicated to SDRAM and SDRAM only.
> In this mode, your master (or a CPU) connects directly to the SDRAM
> controller. There should be no tri-state bridge in between (in fact,
> SOPC Builder shouldn't let you make this connection legally, perhaps
> this is where the issue is...)
> 
> 2. SDRAM controller shares some of its pins with a tri-state bus. This
> allows you to save FPGA I/O if your system also has some other
> external memory (Flash, SRAM, etc.). Specifically the dq/dqm/address
> pins are shared. This is activated with a checkbox in the SDRAM
> controller GUI in SOPC Builder. In this mode, Avalon masters *must
> also* directly connect to the controller (your logic, Nios, etc.), but
> in addition, there will be a "More <sdram name> Settings" Page in SOPC
> Builder that appears, and allows you to choose which (if more than
> one) tri-state bridge you wish to route the shared I/O through. In
> this case, the Avalon master/slave connections you make will be
> similar to the first mode I described above: The master (your logic)
> would connect directly to the SDRAM controller, in addition to the
> tri-state bridge.
> 
> I just made a simple test-case to verify this using QII4.0/SOPCB4.0
> and it generates fine/no warning messages. If you want, feel free to
> email me and I will send you the system's files.
> 
> Jesse Kempa
> Altera Corp.
> jkempa at altera dot com

Article: 70926
Subject: Re: Altera SOPC Master Peripheral Design?
From: pinod01@sympatico.ca (Pino)
Date: 1 Jul 2004 14:41:22 -0700
Links: << >>  << T >>  << A >>
kempaj@yahoo.com (Jesse Kempa) wrote in message news:<95776079.0406300951.753e78cb@posting.google.com>...
> pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0406291101.30563548@posting.google.com>...
> <snip>
> > 
> > tri_state_bridge_0/avalon_slave is not connected to any Master. 
> > Please connect it to a master of type avalon.
> > 
> > Note that the Master peripheral defined is of type avalon and so is
> > the SDRAM controller (as defined within the Memory devices in the
> > System Contents directory tree).
> > 
> > Can someone explain how I can properly connect a Master peripheral
> > (user-defined of course) to the SDRAM controller slave?   Why does the
> > tristate bridge not allow this connection to occur?
> > 
> > P.S.  If this same excercise is done using a NIOS processor master +
> > tristate bridge + SDRAM controller everything is connected with no
> > errors.  The only difference that I see is that my Master is a
> > user-defined peripheral.
> > 
> > 
> > Regards,
> > Pino
> 
> Hi Pino,
> 
> I believe the problem here is because of the various ways you can
> construct a system with SDRAM. First, are you using Altera's SDRAM
> controller that comes with Nios/SOPC Builder? Our controller has two
> modes of operation with respect to its external pins:
> 
> 1. No pin 'sharing'. This is the default behavior, and is what you'd
> select if your board had I/O pins dedicated to SDRAM and SDRAM only.
> In this mode, your master (or a CPU) connects directly to the SDRAM
> controller. There should be no tri-state bridge in between (in fact,
> SOPC Builder shouldn't let you make this connection legally, perhaps
> this is where the issue is...)
> 
> 2. SDRAM controller shares some of its pins with a tri-state bus. This
> allows you to save FPGA I/O if your system also has some other
> external memory (Flash, SRAM, etc.). Specifically the dq/dqm/address
> pins are shared. This is activated with a checkbox in the SDRAM
> controller GUI in SOPC Builder. In this mode, Avalon masters *must
> also* directly connect to the controller (your logic, Nios, etc.), but
> in addition, there will be a "More <sdram name> Settings" Page in SOPC
> Builder that appears, and allows you to choose which (if more than
> one) tri-state bridge you wish to route the shared I/O through. In
> this case, the Avalon master/slave connections you make will be
> similar to the first mode I described above: The master (your logic)
> would connect directly to the SDRAM controller, in addition to the
> tri-state bridge.
> 
> I just made a simple test-case to verify this using QII4.0/SOPCB4.0
> and it generates fine/no warning messages. If you want, feel free to
> email me and I will send you the system's files.
> 
> Jesse Kempa
> Altera Corp.
> jkempa at altera dot com

Jesse,

    Thanks for the response. Just so you are aware I have only been
using the SDRAM controller from within the Altera library within the
system contents window.  I have configured this slave peripheral as
per your option #2, and used the tristate bridge.   In this particular
case, I do obtain something that SOPC can connect with no errors if
and only if I use a NIOS (cpu) master peripheral.  If I use my
developed master peripheral, SOPC builder raises an error in that it
can not see the Master and highlights that it can not be connected to
it.  This raises a question on whether or not I am able to use any
other master peripheral than the NIOS master peripheral?  Does SOPC
builder recognize anything else?  I have sent you my Master peripheral
"Master.VHD" file so that you can include this as "User defined Logic"
as a Avalon Master and monitor the type of error I have seen.

     If anyone knows of any knows of anyway to connect a generic
Master peripheral using SOPC builder, this would be appreciated!


Regards, 
Pino

Article: 70927
Subject: Re: Compact FPGA Board?
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Thu, 1 Jul 2004 23:26:52 +0100
Links: << >>  << T >>  << A >>
>> "Daragoth" <daragoth@kuririnmail.com> wrote in message
>> news:317379a8.0406302118.32829ee1@posting.google.com...

>>> -The most important thing is that it all fits within a 40 mm x 30
>>> mm x 10 mm volume or less.

Should be possible.  The boards here:

    http://www.rockylogic.com/files/AntGuts_LoRes.jpg

are 50mm x 30mm.  The one on the left has an XC2S50E on the reverse
side, and the power supply is a switcher.  The other board has an
XC2S30 on the reverse side, and a linear power supply.



Article: 70928
Subject: Re: *RANT* Ridiculous EDA software "user license agreements"?
From: Sander Vesik <sander@haldjas.folklore.ee>
Date: Thu, 1 Jul 2004 22:58:32 +0000 (UTC)
Links: << >>  << T >>  << A >>
In comp.arch.fpga bko-no-spam-please@ieee.org wrote:
> license_rant_master <none@nowhere.net> writes:
> 
> > I am an ASIC engineer who frequently 'takes work home' with me.
> > ...  According to the
> > language/legalese of the license-agreement, a license 'seat'
> > is tied to a physical location called 'site.'
> 
> Here's a hint: like a lot of things in life, these restrictions are negotiable
> if you are a big enough customer.

The trend of "unless you are going to fork us over some more megabucks and 
are a large company anyways we will disallow doing resonable things" in 
software licences is rather disturbing.

-- 
	Sander

+++ Out of cheese error +++

Article: 70929
Subject: Re: *RANT* Ridiculous EDA software "user license agreements"?
From: Stephen Williams <spamtrap@icarus.com>
Date: Thu, 01 Jul 2004 16:14:04 -0700
Links: << >>  << T >>  << A >>
license_rant_master wrote:

 > Since I can't use the company's tools on *my* home machine, I
 > started investigating various low-cost Verilog simulators to run
 > under Windows.  (I can't use Icarus because it fails to compile a
 > lot of our company's Verilog RTL.)

Hve you filed bug reports? I know the Icarus Verilog bug database
is getting pretty large :-(  but it does get looked at and worked
down.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


Article: 70930
Subject: Re: Trouble with $readmemh in ModelSim
From: Chris Carlen <crcarle@BOGUS.sandia.gov>
Date: Thu, 01 Jul 2004 17:25:39 -0700
Links: << >>  << T >>  << A >>
Brian Philofsky wrote:
> On a related but slightly off-topic note, Chris mentions that he is 
> using 5.2i but using 5.7c of ModelSim-XE.  If memory serves, 5.7c was 
> the version of ModelSim-XE designed to be used with 6.1i.  It is 
> important to keep the MTI-XE release in sync with the ISE version used 
> because MTI-XE comes with pre-compiled libraries for the version of ISE 
> it is released with.  It is possible problems can arise later when 
> post-translate, post-map or post-par (timing) simulation is performed as 
> the simulation netlist will be created by 5.2i but the pre-compiled 
> libraries are for 6.1i if MTI-XE 5.7c is used.  Since updates are 
> periodically necessary in the timing parameters and interfaces to the 
> models, it is never suggested to mix netlists generated with one version 
> of ISE with libraries from another.


Maybe that's why I can't seem to do a post-timing simulation.  But I 
haven't needed to yet since I'm only doing CPLD stuff at relatively slow 
clock rates.  I had terrible problems with 6.1i, so I downgraded.

Thanks for the input.


Good day!


-- 
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov


Article: 70931
Subject: Re: *RANT* Ridiculous EDA software "user license agreements"?
From: "JJ" <her@her.com>
Date: Fri, 02 Jul 2004 02:03:29 GMT
Links: << >>  << T >>  << A >>
Ever hear of VPN?


"license_rant_master" <none@nowhere.net> wrote in message
news:SGMEc.2916$486.1576@newssvr25.news.prodigy.com...
> I am an ASIC engineer who frequently 'takes work home' with me.
> Recently, I began using ssh to remotely login to our company's
> servers to run some Verilog/VHDL simulations.  Launching
> sims (from the UNIX command line) is fairly easy and painless,
> but any kind of interactive (GUI) operations are pitifully
> slow over an WAN/internet connection.  In the past, I
> haven't needed to do much more than check on running jobs,
> restart them, then logout.  Now, I find the need to do some
> interactive debugging work (waveform viewing, code editing,
> etc.)
>
> So I thought, ok, I'll just install Linux at home and check
> out a license remotely from the company.  The system
> administrator told me "NO!" this is forbidden, due to the license
> agreements of just about every EDA-tool vendor.  According to the
> language/legalese of the license-agreement, a license 'seat'
> is tied to a physical location called 'site.'
>
> There are minor differences among the 'site-radius', but the
> end-result is the same ... no executing the tool on hardware outside
> of the radius:
>
> Cadence : 1 mile radius within licensed machine-node
>            (Sysadmin told me this...didn't double-check myself.)
>
> Synopsys: 5 mile radius within licensed machine-node
>            (couldn't find the agreement, but found this on Solvnet.)
>
> Model/Mentor: 800 meter (0.5mi) radius within licensed machine-node
>            (Download the user's manual for any Modelsim product.)
>
> ...
>
> At this point, I think, well alright, most of these EDA tools
> are $100,000 USD and up, so it's reasonable for the vendor to impose
> these terms.  EDA companies don't want 1 company buying a huge site-wide
> (100+) licenses, then randomly 'renting' them out over the internet.
>
> I mentally used this analogy to convince myself this is ok:
> I buy broadband internet service for my household.
> It's "unlimited" for my household -- not my neightborhood or someone
> driving by on a WiFi laptop.  Fair enough...
>
> Since I can't use the company's tools on *my* home machine, I
> started investigating various low-cost Verilog simulators to run
> under Windows.  (I can't use Icarus because it fails to compile a
> lot of our company's Verilog RTL.)
>
> /RANT ON
>
> 1) Modelsim/PE "Personal Edition" -- *exact* same license agreement
>     as their premiere Modelsim/SE.
>
> "Mentor Graphics
> grants to you, subject to payment of appropriate license fees, a
> nontransferable, nonexclusive license to use
> Software solely: (a) in machine-readable, object-code form; (b) for your
> internal business purposes; and (c) on
> the computer hardware or at the site for which an applicable license fee
> is paid, or as authorized by Mentor
> Graphics. A site is restricted to a one-half mile (800 meter) radius."
>
>     *RIDICULOUS*  If I were a design-consultant, and my laptop were
>     my primary compute platform, how am I supposed to comply with a
>     'site' radius?  By their language, I can't run Modelsim
>     if I drive more than 0.5mi from my home-residence/business?!?
>
> 2) ok, so next I move on to Cadence's "Verilog Desktop"
>
>     Wow, same story -- the language of their license agreement brings
>     me to the same conclusion.  Install on laptop -- automatic
>     non-compliance with their agreement (unless you 'lock down' the
>     laptop with a 1-mile chain.)  Funny how their salesman now use
>     x86-laptops for nearly *all* customer-site product demos?!?
>
> 3) I may investigate Verilogger Pro or Simucad, but I figure why bother.
>     I'll probably just end up getting angrier...
>
> ...
>
> /RANT OFF
>
> Any comments?
> What pisses me off the most, is those Cadence/Synopsys/Mentor
> "travelling salesman."  They come to our company-site, armed with
> laptops and LCD-projectors -- then show off how a small x86-laptop
> now runs jobs faster than a low-end Sun/IBM RISC workstation.
> These EDAs need to be sued for false advertising.  At a minimum,
> someone needs to challenge their ridiculous license agreement
> for products aimed at 'personal' use.
>
> For now, I've simply told my supervisor 'project schedule slip.'
> And I've given up on doing real work at home (now mostly just
> catching on documentation and inline RTL-comments.)
>



Article: 70932
Subject: Re: reduced power =?iso-8859-1?Q?Xilinx=AE?= Spartan-3(TM) FPGAs
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 01 Jul 2004 22:31:30 -0400
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> 
> rickman wrote:
> > rickman wrote:
> >
> >>I just read a press release about "power reduced" Spartan 3s.  They
> >>don't give much in the way of numbers, they just say the quiescent power
> >>is reduced by *up to* 66%.  The last time I checked the data sheets,
> >>there were no power figures.  Anyone know what actuals might be attached
> >>to this value?  Just how much quiescent power do these chips suck down?
> >>Numbers on the XC3S400 would be useful.
> >
> >
> > I checked the web site and there are new numbers for the quiescent
> > power.  For the XC3S400, Vccint = 35 mA typ, Vcco = 1.5 mA typ and
> > Vccaux = 20 mA typ.
> 
> Are these the 'reduced' values, or the standard devices ?
> 
> The new Lattice devices also show typicals only, and they too are
> many 10's of mA.
> Last time I saw a leading edge MAX, it was hundreds of mA....
> 
>   Sounds like they may be doing do a 'current bin', just like they do
> 'speed bins'.
> It will, of course, mean that the non reduced ones have higher typicals,
> as all the 'good ones' have been removed :)

These are the standard numbers that they added to the data sheet on the
last go around.  Not exactly bad numbers when you consider the possibly
Watts these chips will consume in normal use. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 70933
Subject: Re: *RANT* Ridiculous EDA software "user license agreements"?
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 01 Jul 2004 22:35:37 -0400
Links: << >>  << T >>  << A >>
JJ wrote:
> 
> Ever hear of VPN?

I'm not sure what you are trying to suggest.  If you mean he should run
the programs on an office machine using interface software from home,
that is what he wants to get away from.  If you are talking about
checking out the license over the network, that is what is forbidden by
the license.  

What are you suggesting?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 70934
Subject: Re: *RANT* Ridiculous EDA software "user license agreements"?
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Fri, 02 Jul 2004 12:51:43 +1000
Links: << >>  << T >>  << A >>
On Thu, 01 Jul 2004 19:21:28 +0200, Lasse Langwadt Christensen
<langwadt@ieee.org> wrote:

>I think some companies (big ones) can a special license, I know one that share
>worldwide and I would think they have a pool of licenses

This was certainly the case when I was at Agilent.  We had three
license server triads (three each in Germany, US and Singapore) that
served the company's global license needs.

It sucked a bit that we were in Melbourne, and the closest server was
several thousand km away.  The time taken to acquire a license was so
long that some users would simply not close the gui (e.g. in Modelsim)
and use up a license all day even when they didn't need to use the
tool.

Regards,
Allan.

Article: 70935
Subject: Re: *RANT* Ridiculous EDA software "user license agreements"?
From: mx <mx@mx.com>
Date: Fri, 02 Jul 2004 03:47:09 GMT
Links: << >>  << T >>  << A >>
Rene Tschaggelar wrote:
> The whole is solved by a notebook being the work machine at
> the expense of reduced performance.

UMMM *NO* the original-poster mentioned somewhere in his rant that
the license terms of Mentor, Cadence, and Synopsys
are *tied* to a physical site.  Actually the software license is bound 
to 3 specific items:

a) authorized hardware (license node/server)
<AND>
b) physical site (company location, with defined 'distance radius')
<AND>
c) the party/persons/company named on the purchase-order

That's *AND* (not OR.)  Change any 1 of the above, and you have to 
contact the vendor to renew/re-validate your license. (This doesn't
automatically mean you have to *repurchase* the software...)

(b) Buying a laptop, taking it on the road, and using it to run the
EDA sofware falls under 'running the software outside of the
physical site.'  All you've done with your laptop, is place
both the license-server and execution-machine in the same
machine (your laptop), instead of just taking the execution-machine

  The physical-site limitation is so restrictive, that technically
speaking, if a customer merely relocates its office more than a
few miles, their software-liense is invalidated.  Obvioualy,
no EDA-vendor requires the customer to repurchase the software.  They
merely update the license contract with the customer's new (street)
address.

(c) If the customer is acquired (purchased) by another company, the
EDA-software is non-transferrable.  Thankfully within industry, the 
standard practice is for the vendor to permit the ownership transfer, as
long as the new owner continues to pay the maintenance/support contract
obligations.  This is cheaper for the new owner, because they don't
have to 're-purchase' the licenses (large one-time non-recurring 
expense), rather merely pay the quarterly/yearly support-fee (smaller 
recurring expense.)


Article: 70936
Subject: Re: Xilinx $99 Spartan-3 kit
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Fri, 02 Jul 2004 04:05:40 GMT
Links: << >>  << T >>  << A >>
On Wed, 30 Jun 2004 16:53:28 +0100, "Leon Heller"
<leon_heller@hotmail.com> wrote:

>Xilinx has a Spartan-3 kit selling for $99, via their web site. Price from
>Insight (UK) will be 70 GBP, but they don't know when they will be in stock.
>
>Leon

I ordered one of these yesterday, received it today.  All in all, it's
a nice little testing platform.

One thing to note: my board came with ES silicon.  I downloaded the
errata from the Xilinx site, and saw nothing I was particularly
concerned with: a couple of minor DCM bugs and a few other piddly
things (yet other bugs have been promoted to features, and are
described in the data sheet).  If you plan to buy the board, you may
want to take a look at the ES errata sheet first.

Bob Perlman
Cambrian Design Works


Article: 70937
Subject: Re: Xilinx $99 Spartan-3 kit
From: soar2morrow@yahoo.com (Tom Seim)
Date: 1 Jul 2004 21:06:13 -0700
Links: << >>  << T >>  << A >>
"Georgi Beloev" <gbH8SPAM@beloev.net> wrote in message news:<YIKdnU5Pla_Br3nd4p2dnA@megapath.net>...
> "Tim" <tim@rockylogic.com.nooospam.com> wrote in message
> news:cbv012$fhr$1$8302bc10@news.demon.co.uk...
> > Steven K. Knapp wrote:
> > > The Xilinx online store has stock will ship boards to practically
> > > anywhere on this planet.
> >
> > Alightly off-topic, but it would be really really helpful if
> > the online store could move into the 20th century and start
> > selling FPGAs.  No need to stock all speed grades or compete
> > on price.
> >
> > And, as I've said before, if X management don't want to handle
> > this, subcontract it to Amazon or DigiKey or whoever.  Just make
> > it possible for designers to order prototype quantities without
> > going through the distributor tarpit - it would help your overall
> > business.
> 
> Try www.nuhorizons.com for small quantities.
> 
> -- Georgi

I would avoid Nu Horizons at all costs.

Article: 70938
Subject: Does Xilinx have the worst web site on the planet?
From: soar2morrow@yahoo.com (Tom Seim)
Date: 1 Jul 2004 21:12:31 -0700
Links: << >>  << T >>  << A >>
Is it me, or do the rest of you have major frustratinos using Xilinx's web site?

Just today they had a broken link TO THEIR OWN SITE!!!

Believe me, I have talked to Xilinx managers who have admitted as much.

Article: 70939
Subject: Re: Does Xilinx have the worst web site on the planet?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 02 Jul 2004 16:36:06 +1200
Links: << >>  << T >>  << A >>
Tom Seim wrote:
> Is it me, or do the rest of you have major frustratinos using Xilinx's web site?
> 
> Just today they had a broken link TO THEIR OWN SITE!!!
> 
> Believe me, I have talked to Xilinx managers who have admitted as much.

  I find it adequate.

  When looking for actual chips, I do get a wry smile as it looks like 
the web authors had a bet going, to see if they could aviod using the 
word Chip or Device, so we get :
"Products and Services " > "Silicon products and solutions" > "CPLD 
Portfolio" - and finally "datasheets"!

Q: So what's the difference between a Silicon product and a Silicon 
solution ? :)

Their datasheet web page itself is well done: it shows the Date/Size and 
splits the data into more downloadable chunks.

-jg


Article: 70940
Subject: Compile 30% of my multipliers with LUT?
From: "Kelvin" <student@nowhere.com>
Date: Fri, 2 Jul 2004 13:37:44 +0800
Links: << >>  << T >>  << A >>
Hi, there:

I am compiling a partial design with XST. I can only use 24 multipliers in
my portion of a V2-6000 chip...
However, the RTL has 35 multipliers...
Now I need to compile the other 11 multipliers with LUT, but I don't want to
modify the RTL codes...
How may I handle this situation?

"-mult_style LUT" makes all multipliers with LUT...AUTO and BLOCK makes all
multipliers with
block multiplers...sigh...

Thanks for your suggesiton...

Kelvin





Article: 70941
Subject: Why this statement renders TWO multipliers in XST?
From: "Kelvin" <student@nowhere.com>
Date: Fri, 2 Jul 2004 14:34:54 +0800
Links: << >>  << T >>  << A >>
Terrible! How may I optimize it in RTL codes?

assign tmp1 = en ? din_a_abs * din_b_abs : 16'b0;
assign dout = sign ? ~tmp1 + 1'b1 : tmp1;

Best Regards,
Kelvin





Article: 70942
Subject: Re: *RANT* Ridiculous EDA software "user license agreements"?
From: Marko <cantsay@here.com>
Date: Fri, 02 Jul 2004 06:46:39 GMT
Links: << >>  << T >>  << A >>
Here is my solution...

I use ModelSim PE.  It's relatively cheap and works well on my PC.
The license is controlled by a dongle, so I can legally run it on any
machine I please - including my home computer.  I presume the same
approach will work with ModelSim SE.  The dongle works with Windows
platforms - not sure about Linux.

If you prefer Cadence or Synopsys, you can explain your situation and
ask them for a waiver.  I'm pretty sure they would agree - if you
asked before you purchased it.  Once they've got your money, it's
another story.

I think you can get a free version of ModelSim from Xilinx.  I'm not
sure if you have to buy anything or not.  In anycase, your Xilinx FAE
should be able to set up a free demo.  I guess ModelTech will do the
same with ModelSim.  

Hope this helps.

BTW, is it possible to buy a "used" VerilogXL license from someone?
There must be thousands that are no longer being used.  I have one.

Marko





On Thu, 01 Jul 2004 04:46:42 GMT, license_rant_master
<none@nowhere.net> wrote:

>I am an ASIC engineer who frequently 'takes work home' with me.
>Recently, I began using ssh to remotely login to our company's
>servers to run some Verilog/VHDL simulations.  Launching
>sims (from the UNIX command line) is fairly easy and painless,
>but any kind of interactive (GUI) operations are pitifully
>slow over an WAN/internet connection.  In the past, I
>haven't needed to do much more than check on running jobs,
>restart them, then logout.  Now, I find the need to do some
>interactive debugging work (waveform viewing, code editing,
>etc.)
>
>So I thought, ok, I'll just install Linux at home and check
>out a license remotely from the company.  The system
>administrator told me "NO!" this is forbidden, due to the license
>agreements of just about every EDA-tool vendor.  According to the
>language/legalese of the license-agreement, a license 'seat'
>is tied to a physical location called 'site.'
>
>There are minor differences among the 'site-radius', but the
>end-result is the same ... no executing the tool on hardware outside
>of the radius:
>
>Cadence : 1 mile radius within licensed machine-node
>           (Sysadmin told me this...didn't double-check myself.)
>
>Synopsys: 5 mile radius within licensed machine-node
>           (couldn't find the agreement, but found this on Solvnet.)
>
>Model/Mentor: 800 meter (0.5mi) radius within licensed machine-node
>           (Download the user's manual for any Modelsim product.)
>
>...
>
>At this point, I think, well alright, most of these EDA tools
>are $100,000 USD and up, so it's reasonable for the vendor to impose 
>these terms.  EDA companies don't want 1 company buying a huge site-wide 
>(100+) licenses, then randomly 'renting' them out over the internet.
>
>I mentally used this analogy to convince myself this is ok:
>I buy broadband internet service for my household.
>It's "unlimited" for my household -- not my neightborhood or someone
>driving by on a WiFi laptop.  Fair enough...
>
>Since I can't use the company's tools on *my* home machine, I
>started investigating various low-cost Verilog simulators to run
>under Windows.  (I can't use Icarus because it fails to compile a
>lot of our company's Verilog RTL.)
>
>/RANT ON
>
>1) Modelsim/PE "Personal Edition" -- *exact* same license agreement
>    as their premiere Modelsim/SE.
>
>"Mentor Graphics
>grants to you, subject to payment of appropriate license fees, a 
>nontransferable, nonexclusive license to use
>Software solely: (a) in machine-readable, object-code form; (b) for your 
>internal business purposes; and (c) on
>the computer hardware or at the site for which an applicable license fee 
>is paid, or as authorized by Mentor
>Graphics. A site is restricted to a one-half mile (800 meter) radius."
>
>    *RIDICULOUS*  If I were a design-consultant, and my laptop were
>    my primary compute platform, how am I supposed to comply with a
>    'site' radius?  By their language, I can't run Modelsim
>    if I drive more than 0.5mi from my home-residence/business?!?
>
>2) ok, so next I move on to Cadence's "Verilog Desktop"
>
>    Wow, same story -- the language of their license agreement brings
>    me to the same conclusion.  Install on laptop -- automatic
>    non-compliance with their agreement (unless you 'lock down' the
>    laptop with a 1-mile chain.)  Funny how their salesman now use
>    x86-laptops for nearly *all* customer-site product demos?!?
>
>3) I may investigate Verilogger Pro or Simucad, but I figure why bother.
>    I'll probably just end up getting angrier...
>
>...
>
>/RANT OFF
>
>Any comments?
>What pisses me off the most, is those Cadence/Synopsys/Mentor 
>"travelling salesman."  They come to our company-site, armed with
>laptops and LCD-projectors -- then show off how a small x86-laptop
>now runs jobs faster than a low-end Sun/IBM RISC workstation.
>These EDAs need to be sued for false advertising.  At a minimum,
>someone needs to challenge their ridiculous license agreement
>for products aimed at 'personal' use.
>
>For now, I've simply told my supervisor 'project schedule slip.'
>And I've given up on doing real work at home (now mostly just
>catching on documentation and inline RTL-comments.)


Article: 70943
Subject: Re: Why this statement renders TWO multipliers in XST?
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Fri, 02 Jul 2004 17:13:17 +1000
Links: << >>  << T >>  << A >>
On Fri, 2 Jul 2004 14:34:54 +0800, "Kelvin" <student@nowhere.com>
wrote:

>Terrible! How may I optimize it in RTL codes?
>
>assign tmp1 = en ? din_a_abs * din_b_abs : 16'b0;
>assign dout = sign ? ~tmp1 + 1'b1 : tmp1;

As part of its logic simplifications, the synthesiser is expanding
tmp1 in the expression being assigned to dout as follows:

assign dout = sign ? ~(en ? din_a_abs * din_b_abs : 16'b0) + 1'b1 :
(en ? din_a_abs * din_b_abs : 16'b0);

and there are your two multipliers.

You need to tell the synthesiser not to expand the expression in this
way.  This can be done with a keep attribute on tmp1.

// synthesis attribute keep of tmp1 is true;

Regards,
Allan.

Article: 70944
Subject: Re: *RANT* Ridiculous EDA software "user license agreements"?
From: news@sulimma.de (Kolja Sulimma)
Date: 2 Jul 2004 03:48:44 -0700
Links: << >>  << T >>  << A >>
license_rant_master <none@nowhere.net> wrote in message 
> /RANT ON
> 
> 1) Modelsim/PE "Personal Edition" -- *exact* same license agreement
>     as their premiere Modelsim/SE.
[...]
>   At a minimum,
> someone needs to challenge their ridiculous license agreement
> for products aimed at 'personal' use.

(Disclaimer: IANAL)
Site wide licenses definitely are licenses and the two companies
involved can agree basically on any ridiculous licensee term that they
can up with, but this might not be the case for a personal edition.

For example if you can manage to buy modelsim PE in a shop or order it
online without clicking through the license agreement than you just
made a regular purchase and there is no license agreement involved.
Even if you click through the license agreement it is very doubtfull
that it is valid. Basically a purchase is a purchase not matter what
you call it and the first sale doctrine applies, which means that the
rightholder can not control the use of an item after the first sale.

This means that you can move your software around (both from place to
place on the same computer, but also from computer to computer)
Also, your company can sell the software to you and you sell it back
later. There is no way the tool vendor can interfere with that. (for
purchased, not rented software) Once you have license files for both
computers you can change ownership easily as often as you want. But
remember to deinstall the software each time.

Kolja Sulimma

Article: 70945
Subject: Re: Compile 30% of my multipliers with LUT?
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Fri, 2 Jul 2004 13:12:00 +0100
Links: << >>  << T >>  << A >>
"Kelvin" <student@nowhere.com> wrote in message
news:40e4f466@news.starhub.net.sg...
> Hi, there:
> I am compiling a partial design with XST. I can only use 24 multipliers in
> my portion of a V2-6000 chip...
> However, the RTL has 35 multipliers...
> Now I need to compile the other 11 multipliers with LUT, but I don't want
to
> modify the RTL codes...
> How may I handle this situation?
> "-mult_style LUT" makes all multipliers with LUT...AUTO and BLOCK makes
all
> multipliers with
> block multiplers...sigh...
> Thanks for your suggesiton...
> Kelvin


If you leave the sythesis tool to its own devices does it not use as many
dedicated multipliers as it can then implement the rest combinatorially?

That's what I would have expected to happen.



Nial.

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
Cyclone Based 'Easy PCI' proto board
www.nialstewartdevelopments.co.uk



Article: 70946
Subject: Re: Xilinx $99 Spartan-3 kit
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Fri, 2 Jul 2004 13:22:36 +0100
Links: << >>  << T >>  << A >>
"Tom Seim" <soar2morrow@yahoo.com> wrote in message
news:6c71b322.0407012006.2b8e4c5c@posting.google.com...
> > Try www.nuhorizons.com for small quantities.
> >
> > -- Georgi
>
> I would avoid Nu Horizons at all costs.


Tom,

You're really not that keen on them, are you?

;-)

Nial.



Article: 70947
Subject: Re: DCM ISE6.2.3 sim problem
From: "jakab tanko" <jtanko@ics-ltd.com>
Date: Fri, 2 Jul 2004 08:31:41 -0400
Links: << >>  << T >>  << A >>
Do you have your modelsim resolution set to ps?
"wolfgang" <wolfgang.hofmann@arcs.ac.at> wrote in message
news:cc14ut$on9$1@newsreader1.utanet.at...
> hey guys!
>
> i trie to simulate a dcm design with modelsim, but the dcm doesn't start.
i
> tried to reset the dcm after applying clkin, it seems, that the dcm is
> working, but clkfx is only a amount of spikes instead of a 50:50 clock but
> at the right frequency. clkin is a 60%:40% clock with 33 MHz.
>
> anyone out there with the same problem?
>
> thx
>
> wolfgang
>
>



Article: 70948
Subject: Re: Compile 30% of my multipliers with LUT?
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Fri, 2 Jul 2004 13:52:18 +0100
Links: << >>  << T >>  << A >>
Kelvin wrote:
> I am compiling a partial design with XST. I can only use 24
> multipliers in my portion of a V2-6000 chip...
> However, the RTL has 35 multipliers...
> Now I need to compile the other 11 multipliers with LUT, but I don't
> want to modify the RTL codes...
> How may I handle this situation?
>
> "-mult_style LUT" makes all multipliers with LUT...AUTO and BLOCK
> makes all multipliers with
> block multiplers...sigh...

Tell the synth that you are compiling for a smaller chip?



Article: 70949
Subject: Re: Does Xilinx have the worst web site on the planet?
From: rrr@ieee.org (Rajeev)
Date: 2 Jul 2004 06:00:20 -0700
Links: << >>  << T >>  << A >>
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<WC5Fc.5764$NA1.536835@news02.tsnz.net>...

> Q: So what's the difference between a Silicon product and a Silicon 
> solution ? :)

A: Software tools that work ;-)

-rajeev-



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