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On Jan 2, 3:28=A0pm, General Schvantzkoph <schvantzk...@yahoo.com> wrote: > On Thu, 30 Dec 2010 12:57:06 -0800, rickman wrote: > > The spam in Google groups has only gotten worse lately and there seems > > to be no end in sight. =A0This group is getting hard to find the real > > posts in and some of the other groups are just plain unusable with five > > or ten spam messages to every real message. > > > Rather than to add spam filters as most newsgroup access providers do, > > Google has invented an entirely new interface with an entirely new look= , > > with the ability to flag a post as spam (or otherwise inappropriate) an= d > > it is hidden from your view. > > > That would be great, except that the new interface sucks compared to th= e > > old one. =A0Maybe it is just that I'm used to the old one, but I have > > tried the new one in one of the groups I access and I don't seem to be > > liking it any more than when I first saw it. > > > For a company that is so good at search engines, why can't they > > understand anything about how newsgroups should work? > > > Rick > > I use news.individual.net, it costs 10 Euros/year. I don't see any spam i= n > this newsgroup or in any of the Linux newsgroups that I frequent. I use > PAN as a newsreader. Google groups is an awful way to access news groups, > not only is it SPAM ridden but the UI is unusable. You should be using a > real newsreader with a properly filtered news server. Are there any "real newsreaders" with a web-only interface? I'd pay good money for that. If not, I don't want to clutter up my work machine with more applications and downloaded news. Google seemed to be the best web interface I could find. -- GaborArticle: 150251
On Wed, 05 Jan 2011 08:43:09 -0800, Gabor wrote: > On Jan 2, 3:28Â pm, General Schvantzkoph <schvantzk...@yahoo.com> wrote: >> On Thu, 30 Dec 2010 12:57:06 -0800, rickman wrote: >> > The spam in Google groups has only gotten worse lately and there >> > seems to be no end in sight. Â This group is getting hard to find the >> > real posts in and some of the other groups are just plain unusable >> > with five or ten spam messages to every real message. >> >> > Rather than to add spam filters as most newsgroup access providers >> > do, Google has invented an entirely new interface with an entirely >> > new look, with the ability to flag a post as spam (or otherwise >> > inappropriate) and it is hidden from your view. >> >> > That would be great, except that the new interface sucks compared to >> > the old one. Â Maybe it is just that I'm used to the old one, but I >> > have tried the new one in one of the groups I access and I don't seem >> > to be liking it any more than when I first saw it. >> >> > For a company that is so good at search engines, why can't they >> > understand anything about how newsgroups should work? >> >> > Rick >> >> I use news.individual.net, it costs 10 Euros/year. I don't see any spam >> in this newsgroup or in any of the Linux newsgroups that I frequent. I >> use PAN as a newsreader. Google groups is an awful way to access news >> groups, not only is it SPAM ridden but the UI is unusable. You should >> be using a real newsreader with a properly filtered news server. > > Are there any "real newsreaders" with a web-only interface? I'd pay > good money > for that. If not, I don't want to clutter up my work machine with more > applications > and downloaded news. Google seemed to be the best web interface I could > find. > > -- Gabor No there aren't any real newsreaders that are web based. However you could use Thunderbird which combines mail and news.Article: 150252
>> I would use a synchronous design with only one clock, 200Mhz.
>> No constraints necessary.
>>
>> -- Mike Treseler
On 1/4/2011 6:06 PM, Benjamin Couillard wrote:
> In a perfect world, that's what I would do, but this is not a new
> design, I need to add processing blocks in an almost finished FPGA.
> Almost everything else in on the 100 MHz clock. In order to save some
> space on the FPGA,my plan was to transfer the data to the 200 MHz
> clock, perform the filtering operations, and then align the data to
> the 100 MHz clock (by converting the data_out_valid on 200 MHz to 100
> MHz). That way I will use less resources than performing the filtering
> operations at 100 MHz.
Either strategy can be made to work. The question is which will take
longer to design and debug.
Adding a fifo where there was none before, adds several reset test cases
to consider. These cases are often found late in the game. That's why I
might spend some time to create synchronous clock enables for the "known
good" 100MHz rate stuff instead. That way I would also avoid having to
specify and test the PLL delay constraints.
Good luck.
-- Mike Treseler
Article: 150253
Rick and Kevin,
thanks for your answers.
Kevin explained very well why I may get warnings on one implementation
and not the other. Naive error.
Rick, you are right my signal goes down exactly on the rising edge of
the clock (being async, it just happened in my simulation).
I have changed how the design not to react to posedge of the reset
signal, not sure if this will solve the metastability side.
So from:
...
always @(posedge fx2_clk or posedge resetpin)
if (resetpin)
begin
//dashout <= 1'b0;
//cntdash <= 4'b0;
dashstate <= 4'b0000;
end
else
case (dashstate)
4'b0000: begin
...
To:
...
always @(posedge fx2_clk)
if (resetpin)
begin
//dashout <= 1'b0;
//cntdash <= 4'b0;
dashstate <= 4'b0000;
end
else
case (dashstate)
4'b0000: begin
...
This "solved" the warnings. About metastability and such, I didn't find
much examples on how to handle the external async reset signal to
initialize FSM.
I am trying to design a simple keyer and corresponding selfchecking
testbench.
I wanted to set conditions based on the WPM speed (words per minute) and
check high level keyer behavior.
For example I would like to be sure it will always generate dots and
dashes of the set length with the desired space between them.
I need to check that pressing the dot or dashes while already operating,
will generate the corresponding dot or dash after the current operation,
acting like a sort of small buffer.
I would like to check that the sidetone (700Hz) is correctly generated
only when the output is set.
My idea is to loop from the lowest WPM to the highest WPM and check
several conditions while I implement more complex features.
I currently having big troubles learning testbenches, and 10.1 webise
complains as soon I implement concurrent tasks, so I am using also 12.4
on windows 7 64 bit and there at least the workbench operates without
errors (so far).
Don't know much about stating timing analisys, I look at waveforms and
try to automate checks, I only have webise.
I see there is a "Static Timing Report" there but there is nothing wrong
there (0 errors).
On the other side, I didn't set any constraints, I don't know what I
could ask for at them moment, is a very simple project.
Giuseppe Marullo
On 1/3/2011 11:23 PM, rickman wrote:
> On Dec 30 2010, 7:56 am, Giuseppe Marullo
> <giuseppe.marullonos...@iname.com> wrote:
>> Hi,
>> I am designing a very simple cw keyer, and I am wondering why some
>> timings in reset signal is triggering timing violations.
>>
>> My problem is that apparently symmetrical FSMs get warnings on one
>> instance while the other not.
>>
>> I got timing violations when reset duration is, for example 60ns or
>> 100ns in the testbench:
>>
>> ...
>> // Initialize Inputs
>> fx2_clk = 0;
>> paddledot<= 1'b1;
>> paddledash = 1'b1;
>> resetpin = 1;
>>
>> // Wait 100 ns for global reset to finish
>> #60;
>> resetpin = 0;
>>
>> 60 or 100ns are exactly on the raising edge of the feeded fx2_clk (40ns
>> period).
>>
>> I got these warnings:
>>
>> WARNING:Simulator:29 - at 63.358 ns: Warning: Timing violation in
>> /test002/uut/dashstate_FSM_FFd1/ $recrem<recovery>( RST:62.893 ns,
>> CLK:63.358 ns,991.000 ps)
>>
>> WARNING:Simulator:29 - at 63.370 ns: Warning: Timing violation in
>> /test002/uut/morsestate_FSM_FFd1/ $recrem<recovery>( RST:62.958 ns,
>> CLK:63.370 ns,991.000 ps)
>>
>> My question is: why I got the warning on dashstate and not on dotstate?
>> They are debouncers for the dot and dash paddle inputs and they are
>> identical.
>
> ...snip...
>
> I assume you are running a post-layout simulation which uses special
> models for the actual components in the FPGA and checks setup and hold
> times on FFs. This is a poor way to verify logic and an even poorer
> way to verify timing. As KJ said, you should be checking timing using
> static timing analysis.
>
> Your error is coming from the fact that your reset is going away on
> the active edge of the clock. There are two ways this will mess up
> your design. One is that the prop delays to various FFs is different
> so that the reset will be released on different FFs on different clock
> cycles possibly putting your FSMs and other logic into invalid
> states. The other is that a FF can go metastable and disrupt other
> logic following it also putting things into invalid states.
>
> I try to design my logic so it will not be disturbed by a poorly timed
> async reset.
>
> Rick
Article: 150254On Jan 5, 4:21 pm, Giuseppe Marullo <giuseppe.marullonos...@iname.com> wrote: > Rick and Kevin, > thanks for your answers. > > Kevin explained very well why I may get warnings on one implementation > and not the other. Naive error. > > Rick, you are right my signal goes down exactly on the rising edge of > the clock (being async, it just happened in my simulation). > > I have changed how the design not to react to posedge of the reset > signal, not sure if this will solve the metastability side. > So from: The way to handle async inputs is to synchronize them by running the signals through at least one FF, or if your delays are a significant portion of your clock cycle, through two FFs serially. The major issue is actually just that you are feeding more than one FF with an async input. If the input changes near the clock edge, some FFs will see it high and others low. Running the signal through a FF first means it will not be changing on the active edge of the clock and all subsequent FFs will see the same value on each clock. Metastability is a more insidious problem and actually can never be eliminated, only minimized. But running the signal through two FFs serially will most likely reduce the probability such that you won't see it happen in your lifetime... Is that clear? > ... > always @(posedge fx2_clk or posedge resetpin) > if (resetpin) > begin > //dashout <= 1'b0; > //cntdash <= 4'b0; > dashstate <= 4'b0000; > end > else > case (dashstate) > 4'b0000: begin > ... > > To: > > ... > always @(posedge fx2_clk) > if (resetpin) > begin > //dashout <= 1'b0; > //cntdash <= 4'b0; > dashstate <= 4'b0000; > end > else > case (dashstate) > 4'b0000: begin > ... > > This "solved" the warnings. About metastability and such, I didn't find > much examples on how to handle the external async reset signal to > initialize FSM. You lucked into the warnings. It is not normal to see them in simulations, but I believe you are running a post layout simulation where the logic element models have setup and hold time checks. This makes your simulation run a LOT slower than a standard simulation done before layout. There is not much reason to run simulation after layout. This is not likely to find all or even most timing errors while static timing analysis does a much better job. There is a lot of debate on how to best handle an async reset release. In your case, I assume that once the circuit is reset, it does nothing until some external input changes state, no? If that is true, you don't need to worry about the async reset. Go back to the first approach you used and you will be fine. The tool will use the global set/reset signal which will save resources. I am not so familiar with Verilog, rather VHDL. In VHDL a register would be described by resetting it when the reset is asserted, but the clock is active only on an edge. What you have written above may be just fine for Verilog, you can check other examples to be sure. > I am trying to design a simple keyer and corresponding selfchecking > testbench. > > I wanted to set conditions based on the WPM speed (words per minute) and > check high level keyer behavior. > > For example I would like to be sure it will always generate dots and > dashes of the set length with the desired space between them. > > I need to check that pressing the dot or dashes while already operating, > will generate the corresponding dot or dash after the current operation, > acting like a sort of small buffer. > > I would like to check that the sidetone (700Hz) is correctly generated > only when the output is set. > > My idea is to loop from the lowest WPM to the highest WPM and check > several conditions while I implement more complex features. > > I currently having big troubles learning testbenches, and 10.1 webise > complains as soon I implement concurrent tasks, so I am using also 12.4 > on windows 7 64 bit and there at least the workbench operates without > errors (so far). > > Don't know much about stating timing analisys, I look at waveforms and > try to automate checks, I only have webise. All FPGA design toolsets include static timing analysis. You just have to set up the timing constraints. The simplest one is to tell the tool your clock speed with a period constraint. That does tons. You may also need to have constraints for input pin setup time and output pin delay time. > I see there is a "Static Timing Report" there but there is nothing wrong > there (0 errors). Because either there are no timing constraints to check or some default constraint was applied and was met. > On the other side, I didn't set any constraints, I don't know what I > could ask for at them moment, is a very simple project. I don't know that you should expect any timing problems. If your clock is under 10 MHz it is unlikely that you have any timing errors. If it is faster than 50 MHz, you need to be very careful to setup the timing constraints fully. But I don't think timing is your problem. I think you need to be much more concerned with your code and logic. The number one rule of using HDLs is to remember that HDL stands for Hardware Description Language. It should be used to describe hardware. That works better, in my opinion, if you know what hardware you want and write the code to get that. I plan my design by thinking or even drawing block diagrams based on the registers. You don't need to specify the logic in detail, but knowing where you want registers is important. Then you can write the code to describe those registers. The logic between registers can be written as combinatorial code or added to the register always blocks. It can be important to keep the clocking simple to reduce the work required to deal with crossing clock domains. So if possible, use one clock with enables rather than to generate slower clocks. This helps tons with the timing analysis too. Does that make sense? In essence, I try to keep it all simple by thinking simply in the HDL. There may be complexity in the logic I use to solve the problem. But describing that logic is actually pretty simple. RickArticle: 150255
On Jan 4, 3:08=A0am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > At least I can do addition of std_logic_vectors with no special settings = in > Quartus 10. It's not 'special settings'. In order to 'add' std_logic_vectors you need to include the ieee.std_logic_arith package. This package however is not standard, it is also not from IEEE. The proper package to use when you want to do math with vectors is either ieee.numeric_std or the more recently released fixed point package 'fixed_pkg'. > But for integers, you need the numeric library. Not true. For integers, you need no package at all. Math with integers is supported by the language definition. > The code below is some tested and implemented code I found on my drive. Not shown in your code is the statement "use ieee.std_logic_arith.all" which, as mentioned above, is not standard...but is required in order to use your code 'as-is'. <snip> The following process code also has an unneeded signal in the sensitivity list...left as an exercise to the reader to spot. > =A0process(clk,rst) begin > =A0 if(rising_edge(clk)) then > =A0 =A0test<=3D'0'; > =A0 =A0testcnt<=3Dtestcnt+"1"; > =A0 =A0if(rst=3D'1' or testcnt>testval) then > =A0 =A0 testcnt<=3D(others=3D>'0'); > =A0 =A0 test<=3D'1'; > =A0 =A0end if; > =A0 end if; > =A0end process; > end rtl; > KJArticle: 150256
On 5 Jan., 12:24, "Pragathi" <pragathikethireddi@n_o_s_p_a_m.gmail.com> wrote: > what exactly is dual port ram... how it is different from single port > ram...?Is data pin a bidirectional pin? > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Hi, inside an FPGA there are no bidirectional connections (anymore). An external memory device can have bidirectional pins. See the datasheet for details. Have a nice synthesis EilertArticle: 150257
I'm looking for a cheap Altera dev board with DDR RAM and an LVDS compatible connector. However, it seems like the cheapest one is the $1000 "Cyclone III FPGA Development Kit". I initially thought that the $200 "Cyclone III FPGA Starter Kit" would work since it has HSMC, but the manual states that it is only intended for CMOS signals and has no provisions for differential pairs. So does there exist a board that meets my requirements that is less than $500? I know Xilinx does (the Digilent Atlys, which has great specs), but I'd like to develop for the Cyclone 3/4 because they support DDR DIMM's while the Spartans do not. If there doesn't exist such a dev board, it seems to me like there's a huge gap in their line- up. What I want to do is make a daughtercard board for an 11-bit ADC, at 200MHz DDR. I need twelve LVDS pairs. Perhaps I could just try using the starter kit board and see if the non-differential pair routing will still work, but I don't want to just toss $200 away either.Article: 150258
"KJ" <kkjennings@sbcglobal.net> wrote in message news:8b3f8888-75d7-4af1-906d-0e992949fad8@g26g2000vbi.googlegroups.com... >On Jan 4, 3:08 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: >> At least I can do addition of std_logic_vectors with no special settings >> in >> Quartus 10. >It's not 'special settings'. In order to 'add' std_logic_vectors you >need to include the ieee.std_logic_arith package. This package >however is not standard, it is also not from IEEE. The proper package >to use when you want to do math with vectors is either >ieee.numeric_std or the more recently released fixed point package >'fixed_pkg'. When I say "special settings" I meant there was no application references to packages (if possible at all). I use the default Quartus settings. >> The code below is some tested and implemented code I found on my drive. >Not shown in your code is the statement "use ieee.std_logic_arith.all" >which, as mentioned above, is not standard...but is required in order >to use your code 'as-is'. NO, ieee.std_logic_arith.all was not in my code. Did you try it? >The following process code also has an unneeded signal in the >sensitivity list...left as an exercise to the reader to spot. True, I just add 'rst' there as my own standard, in case I need to use async reset. When not using it, I forget to remove it, and it doesn't cause any damage, so I don't care.Article: 150259
Hello. I have a design targeting the (ancient, perhaps) Actel A54SX32A. During testing I exposed several of the input pins to signals with extremly low slewrate, using a power-supply to supply the input. This was most likely way outside the minimum slewrate requrements for the device. The FPGA seems to be working and it passes all functional tests, but the current to the core is way to large at about 70mA. Sadly, I did not measure the current beforehand and the cost of a new (ceramic) FPGA prohibits me from just burning a new one to test that. A freshly burned plastic FPGA works fine and consumes the expected current. Does anyone have any experience with destroying FPGAs due to low slewrates? Is this even probable? Also, Hello everyone. This is my first post here, Ive been "lurking" so to speak, and there seems to be a lot of talanted people here. Regards! Kalle --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150260
Hello, I'm working on a project involving an actel flash FPGA (A3P250) and I need to discriminate cold resets (reset at power up) from warm resets. As the power up level of my registers is unknown, I can't find any good way of doing this. The best solution I came up with so far is the following: - Use an n-Bit wide register - When the FPGA is reset compare the register with a "magic value" A, if it is equal to A then it is a warm reset - When the FPGA is reset load the register with A This will work most of the time but has one chance over 2^n to detect a warm reset at power up (if the register powers-up containing A). Is there any best way of detecting a cold boot? Thanks is advance. JB DuboisArticle: 150261
"JB" <jb.dubois.jbd@gmail.com> wrote in message news:32d6bdbb-8616-4a6f-946a-22cc2aa09d96@m11g2000vbs.googlegroups.com... > Hello, > > I'm working on a project involving an actel flash FPGA (A3P250) and I > need to discriminate cold resets (reset at power up) from warm resets. > Is there any best way of detecting a cold boot? I would assume you could just put an attribute to a FF telling it should be high or low at init, and write code to change its state when read.Article: 150262
"Morten Leikvoll" <mleikvol@yahoo.nospam> wrote in message
news:DPednbEEsKCGvbrQnZ2dnUVZ8sidnZ2d@lyse.net...
> "JB" <jb.dubois.jbd@gmail.com> wrote in message
> news:32d6bdbb-8616-4a6f-946a-22cc2aa09d96@m11g2000vbs.googlegroups.com...
>> Hello,
>>
>> I'm working on a project involving an actel flash FPGA (A3P250) and I
>> need to discriminate cold resets (reset at power up) from warm resets.
>
>> Is there any best way of detecting a cold boot?
>
> I would assume you could just put an attribute to a FF telling it should
> be high or low at init, and write code to change its state when read.
You could TRY this, but I guess its a bit dependant on the synth tool if it
actually uses the init value of the signal.
signal hotboot:STD_LOGIC:='1';
..
if(rising_edge(clk)) then
if(warmreset='1') then -- for syncronous warm reset
hotboot<='0';
end if;
end if;
.
.
Article: 150263On Jan 7, 4:07=A0am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > "KJ" <kkjenni...@sbcglobal.net> wrote in message > > >The following process code also has an unneeded signal in the > >sensitivity list...left as an exercise to the reader to spot. > > True, I just add 'rst' there as my own standard, in case I need to use as= ync > reset. When not using it, I forget to remove it, and it doesn't cause any > damage, so I don't care. That's not strictly true. In simulation this will cause additional, unnecessary executions of the process when RST toggles, but then I guess that's not very often. I wouldn't leave those in just to keep the code clean. If nothing else, I am sure it generates warnings which help to clutter up the compile output and hide other, more meaningful warnings. RickArticle: 150264
On 7 jan, 15:22, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > "Morten Leikvoll" <mleik...@yahoo.nospam> wrote in message > > You could TRY this, but I guess its a bit dependant on the synth tool if = it > actually uses the init value of the signal. > > signal hotboot:STD_LOGIC:=3D'1'; > .. > if(rising_edge(clk)) then > =A0 =A0 if(warmreset=3D'1') then -- for syncronous warm reset > =A0 =A0 =A0 =A0 hotboot<=3D'0'; > =A0 =A0 end if; > end if; > . It will work on SRAM FPGA but as far as I know flash FPGA can't use initial values for their FF. At least it is not specified by Actel, and as the project targets a secure aeronautical function, I can't justify the design just by saying "I tried it a few times, it seems to be working..." Do one of you know anything about FF power up level on flash (or antifuse) FPGA which may not be specified by actel but still true?Article: 150265
"Allan Wang" <allanvv@gmail.com> wrote in message
news:b69383b3-ad53-4e2c-a9b8-03580cbf6d60@g25g2000yqn.googlegroups.com...
>
> So does there exist a board that meets my requirements that is less
> than $500? I know Xilinx does (the Digilent Atlys, which has great
> specs), but I'd like to develop for the Cyclone 3/4 because they
> support DDR DIMM's while the Spartans do not. If there doesn't exist
> such a dev board, it seems to me like there's a huge gap in their line-
> up.
>
I could have sworn ("£$%^) that the Spartan series have DDR support?
BICBW??
Article: 150266Sorry for not thinking flash. I guess you need some external powerup signal (poweron reset) to set a FF then. And the warm reset needs to be separate from this. "JB" <jb.dubois.jbd@gmail.com> wrote in message news:86367b28-3d01-48f0-beb0-33e53bf49dd9@l22g2000vbp.googlegroups.com... On 7 jan, 15:22, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > "Morten Leikvoll" <mleik...@yahoo.nospam> wrote in message > > You could TRY this, but I guess its a bit dependant on the synth tool if > it > actually uses the init value of the signal. > > signal hotboot:STD_LOGIC:='1'; > .. > if(rising_edge(clk)) then > if(warmreset='1') then -- for syncronous warm reset > hotboot<='0'; > end if; > end if; > . It will work on SRAM FPGA but as far as I know flash FPGA can't use initial values for their FF. At least it is not specified by Actel, and as the project targets a secure aeronautical function, I can't justify the design just by saying "I tried it a few times, it seems to be working..." Do one of you know anything about FF power up level on flash (or antifuse) FPGA which may not be specified by actel but still true?Article: 150267
Hi, I am facing a problem, i stuffed a new FPGA spartan 3 xc3s1000 on a custom board and it is not getting programmed. It gets detected correctly, all the JTAG pins are in the correct state i.e. Pulled up to 2.5v. When i program the FPGA, xilinx ISE 12.1 says program succeeded but i do not see any functionality of the FPGA.I am only running a counter in the code on the incoming clock and viewing it on chipscope. Chipscope detects the core but does not trigger and gives a message "waiting for core to be armed" or something like that. So i changed the clock pin of FPGA assuming that the pin may have been left dry sold but still the same problem.And yes the clock is coming as i saw it on oscilloscope. So, i started probing all the signals i.e. DONE, Prog_B and INIT_B to view their proper behaviour. DONE was going high when xilinx said program succeeded, INIT_B always goes low at the start of programming sequence. But Prog_B never goes low :s It should go low to clear the configuration memory but it doesn't. So, does it have anything to do with the dysfunctional FPGA ? And i also checked the power rails, before and after programming and they were stable. so what can be the problem here?Is is possible that some bank is not getting proper voltages and while mapping the logic in FPGA, xilinx maps it to that area, is that possible ? kindly give me pointers to debug the issue. regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150268
On Fri, 07 Jan 2011 07:24:21 -0600, "karl.bengtsson" <karl.bengtsson@n_o_s_p_a_m.norspace.no> wrote: >Hello. > >I have a design targeting the (ancient, perhaps) Actel A54SX32A. During >testing I exposed several of the input pins to signals with extremly low >slewrate, using a power-supply to supply the input. This was most likely >way outside the minimum slewrate requrements for the device. > >The FPGA seems to be working and it passes all functional tests, but the >current to the core is way to large at about 70mA. Sadly, I did not measure >the current beforehand and the cost of a new (ceramic) FPGA prohibits me >from just burning a new one to test that. A freshly burned plastic FPGA >works fine and consumes the expected current. > >Does anyone have any experience with destroying FPGAs due to low slewrates? >Is this even probable? CMOS structures are push-pull ie they have two switches which "simultanenously" turn-on/off to change state; alas the switching is never instantenous so there is overlap so dynamic current flows during the switch. The worst case current is near the middle voltage level, the longer you stay around that point the higher the average current. It's possible to destroy individual IOs by leaving unconnected inputs and letting them float. Your case is not as extreme but would affect lifetime of the IO. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 150269
On Fri, 07 Jan 2011 10:19:43 -0600, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >Hi, >I am facing a problem, i stuffed a new FPGA spartan 3 xc3s1000 on a custom >board and it is not getting programmed. It gets detected correctly, all the >JTAG pins are in the correct state i.e. Pulled up to 2.5v. When i program >the FPGA, xilinx ISE 12.1 says program succeeded but i do not see any >functionality of the FPGA.I am only running a counter in the code on the >incoming clock and viewing it on chipscope. >Chipscope detects the core but does not trigger and gives a message >"waiting for core to be armed" or something like that. >So i changed the clock pin of FPGA assuming that the pin may have been left >dry sold but still the same problem.And yes the clock is coming as i saw it >on oscilloscope. > >So, i started probing all the signals i.e. DONE, Prog_B and INIT_B to view >their proper behaviour. DONE was going high when xilinx said program >succeeded, INIT_B always goes low at the start of programming sequence. But >Prog_B never goes low :s It should go low to clear the configuration memory >but it doesn't. So, does it have anything to do with the dysfunctional FPGA >? > >And i also checked the power rails, before and after programming and they >were stable. > > >so what can be the problem here?Is is possible that some bank is not >getting proper voltages and while mapping the logic in FPGA, xilinx maps it >to that area, is that possible ? > >kindly give me pointers to debug the issue. Route the incoming clock to an output and observe with the scope. Depending on what you see you need to take different routes to further debug. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 150270
On 1/7/2011 7:07 AM, Morten Leikvoll wrote: > Sorry for not thinking flash. I guess you need some external powerup signal > (poweron reset) to set a FF then. And the warm reset needs to be separate > from this. > > "JB"<jb.dubois.jbd@gmail.com> wrote in message > news:86367b28-3d01-48f0-beb0-33e53bf49dd9@l22g2000vbp.googlegroups.com... > On 7 jan, 15:22, "Morten Leikvoll"<mleik...@yahoo.nospam> wrote: >> "Morten Leikvoll"<mleik...@yahoo.nospam> wrote in message >> >> You could TRY this, but I guess its a bit dependant on the synth tool if >> it >> actually uses the init value of the signal. >> >> signal hotboot:STD_LOGIC:='1'; >> .. >> if(rising_edge(clk)) then >> if(warmreset='1') then -- for syncronous warm reset >> hotboot<='0'; >> end if; >> end if; >> . > > It will work on SRAM FPGA but as far as I know flash FPGA can't use > initial values for their FF. > > At least it is not specified by Actel, and as the project targets a > secure aeronautical function, I can't justify the design just by > saying "I tried it a few times, it seems to be working..." > > Do one of you know anything about FF power up level on flash (or > antifuse) FPGA which may not be specified by actel but still true? > > Hang a ceramic cap off an IO pin. Use it as a 1 bit memory. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 150271
A coworker and I were debating what do the likes of Intel, IBM and AMD do d= ifferently that allows them to design circuits at 3GHz+. In contrast with F= PGAs which for the most part run on a similar process node (i.e. 65 or 40nm= ), but where even the major static blocks (i.e. DSP blocks) are only capabl= e of around 500Mhz performance. Also compare to the fastest ARM chips, grap= hics chips, most ASICs and other chips which may get up to 1.5GHz, but rare= ly faster (yes, faster chips do exist, but they are the exception rather th= an the rule). So we had some theories about the cause of the difference: - Intel/IBM are way ahead in their technology development over the likes of= TSMC and UMC. Doesn't AMD use UMC? - The 3.5GHz logic (i.e. the execution unit pipeline) in an Intel CPU doesn= 't actually run at 3.5GHz. There is a 3.5G clock, but it turns into a mess = clock enables and logic effectively running at a much slower rate. Though e= ffective 3GHz performance is still achieved through parallelism. - The difference is dynamic logic/domino logic/etc. Most common logic desig= ns (ASICs, FPGAs, ARM processors) use static logic - a mess of conventional= CMOS gates separated by flops. High performance chips use dynamic logic, l= ots of latches and similar tricks to avoid the overhead of static logic. Th= is idea may not stand up to scrutiny as I understand that the latest Intel = architectures (Nehalem) are fully static. - The designers of ASICs/GPUs/FPGAs knowingly make the tradeoff to lower sp= eeds to reduce power consumption. That is you could get a 3.5GHz ARM proces= sor, but it'd be 100W. Anyone have any ideas or knowledge to clarify the issue? Why can Intel, AMD= , and IBM create 3-4GHz chips, when most other chips seem to be limited to = somewhere between 500MHz-1.5GHz. ChrisArticle: 150272
On Fri, 7 Jan 2011 14:53:51 -0000, "Fredxx" <fredxx@spam.com> wrote:
>
>"Allan Wang" <allanvv@gmail.com> wrote in message
>news:b69383b3-ad53-4e2c-a9b8-03580cbf6d60@g25g2000yqn.googlegroups.com...
>
>>
>> So does there exist a board that meets my requirements that is less
>> than $500? I know Xilinx does (the Digilent Atlys, which has great
>> specs), but I'd like to develop for the Cyclone 3/4 because they
>> support DDR DIMM's while the Spartans do not. If there doesn't exist
>> such a dev board, it seems to me like there's a huge gap in their line-
>> up.
>>
>
>I could have sworn ("£$%^) that the Spartan series have DDR support?
>
>BICBW??
Spartan-3 can be made to drive a DIMM, up to a certain speed.
Spartan-6 on the other hands, has a dedicated DDR interface core which connects
to several individual DDR2 (3) DRAM chips, but won't support a DIMM. I believe
the issue is that timings are calibrated assuming individual address/ctrl lines
for each chip, but they are commoned in a DIMM.
It might be possible to implement the old style DDR controller in S6 and just
ignore the dedicated core. I recall a hint here several months ago to "contact
your friendly FAE" if you wanted to learn more about it, but there were no
posted follow-ups.
I can't help feeling Xilinx dropped the ball with the S6 and DDR memory.
- Brian
Article: 150273> Hang a ceramic cap off an IO pin. =A0Use it as a 1 bit memory. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order How will you be sure that the capacitor will not be loaded by the FPGA on cold reset? By not putting any FF in the path (assuming that is it logically valid)?Article: 150274
Chris Maryan <kmaryan@gmail.com> wrote: >A coworker and I were debating what do the likes of Intel, IBM and AMD do d= >ifferently that allows them to design circuits at 3GHz+. In contrast with F= >PGAs which for the most part run on a similar process node (i.e. 65 or 40nm= >), but where even the major static blocks (i.e. DSP blocks) are only capabl= >e of around 500Mhz performance. Also compare to the fastest ARM chips, grap= >hics chips, most ASICs and other chips which may get up to 1.5GHz, but rare= >ly faster (yes, faster chips do exist, but they are the exception rather th= >an the rule). > >So we had some theories about the cause of the difference: >- Intel/IBM are way ahead in their technology development over the likes of= > TSMC and UMC. Doesn't AMD use UMC? Just compare the power consumption and there is your answer. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------
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