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On Thu, 15 Feb 2007 08:55:05 +0100, "Geronimo Stempovski" <geronimo.stempovski@arcor.de> wrote: >Again, I'm looking for a diagram like frequency (some MHz to 10 GHz for >example) versus loss tangent and / or epsilon R for FR4 or other usual PCB >material. I only found a poor black-and-white copy from 1991 in a paper >which I searched with Google. I wouldn't have thought it to be so hard to >find a graph but as noone replied to my previous question so far it does >seem to be hard! :-) > >Does anybody know where I can find that? > >Regards Gero > Google gives lots of hits on stuff like "loss tangent fr4 frequency" But FR-4 varies a lot, so there's no definitive data. What are you trying to do? JohnArticle: 115626
On Wed, 14 Feb 2007 17:10:34 +0100, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > > FR4 can be used at 20 GHz, depending on what you're trying to do. Hello, well, if the transmission line is very, very short..... byeArticle: 115627
On Thu, 15 Feb 2007 08:55:05 +0100, Geronimo Stempovski = <geronimo.stempovski@arcor.de> wrote: > Again, I'm looking for a diagram like frequency (some MHz to 10 GHz fo= r > example) versus loss tangent and / or epsilon R for FR4 or other usual= = > PCB > material. I only found a poor black-and-white copy from 1991 in a pape= r > which I searched with Google. I wouldn't have thought it to be so hard= to > find a graph but as noone replied to my previous question so far it do= es > seem to be hard! :-) Hello, look here for FR408 http://www.isola.de/d/ecomaXL/index.php?site=3DISOLA_DE_product_addition= al_information&sid=3D235&p=3D10 byeArticle: 115628
On Thu, 15 Feb 2007 16:15:49 +0100, "Uwe Hercksen" <hercksen@mew.uni-erlangen.de> wrote: >On Wed, 14 Feb 2007 17:10:34 +0100, John Larkin ><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >> >> FR4 can be used at 20 GHz, depending on what you're trying to do. > >Hello, > >well, if the transmission line is very, very short..... > > Exactly. JohnArticle: 115629
Hello, Do you know what is the format of the FFT IP 2.2.1 Altera Output ? It's not compliant with IEEE 754 floating point format I think that it have the exponent in 2's complement The mantissa in 2's complement with the MSB the bit sign Thanks for helpArticle: 115630
On Feb 14, 9:59 am, "jetq88" <jetq5...@gmail.com> wrote: > goto Xilinx > and check MIG tool, nowhere to download MIG tool for ISE9.1. guess I > have to use old tool, then import to ISE9.1 and tweak it by myself. In late February Xilinx will release the newest MIG1.7 that works with ISE9.1i . Peter AlfkeArticle: 115631
If you just want to include a netlist generated by CoreGen in your XPS project, you will need to create a BBD (black box definition?) file in the data/ directory of the pcore you want to use the core in. You will also need to create a netlist/ directory to put your EDNs and NGCs in. MattArticle: 115632
John, Thanks for the reply. I agree that it would appear that the banks are somehow not being powered. We have two boards based on this design, and they both suffer from the same problem. It seems strange that both boards would suffer from the same soldering anamoly. The folks who did the layout and routing have gone back and checked the connections to VCCO, and everything seems to check out. > It all makes solid sense for non-powered I/O banks. Do you have more than > one board? Do you have access to the layout? If there are direct plane > connects for power but not for signals, there could be differences in the > soldering for the different pin types. Good luck. Can you elaborate a little more on this? How might the soldering be different? I believe the power pins do have direct plane connects. Thanks, -BenArticle: 115633
"bengineerd" <bengineerd@gmail.com> wrote in message news:1171563163.989270.307350@j27g2000cwj.googlegroups.com... > John, > > Thanks for the reply. I agree that it would appear that the banks are > somehow not being powered. We have two boards based on this design, > and they both suffer from the same problem. It seems strange that > both boards would suffer from the same soldering anamoly. The folks > who did the layout and routing have gone back and checked the > connections to VCCO, and everything seems to check out. > >> It all makes solid sense for non-powered I/O banks. Do you have more >> than >> one board? Do you have access to the layout? If there are direct plane >> connects for power but not for signals, there could be differences in the >> soldering for the different pin types. Good luck. > > Can you elaborate a little more on this? How might the soldering be > different? I believe the power pins do have direct plane connects. > > Thanks, > -Ben Our process guys were very uncomfortable with any inconsistent thermal footprints for any FPGA balls in our reflow setup to the extent that they wanted all balls connected to via escapes, necessary or not; that certainly didn't work for me for the outside rows but I understood their point. Depending on how the part is assembled onto the board, the balls connected to vias that feed traces have a low thermal load - when heat is applied, heat is transferred efficiently. The balls connected to vias that connect to planes through thermal releiefs have reasonable thermal transfer efficiency because heat transfers to the balls with little dependence on the plane temperature, but some. The balls connected to direct-plane vias have most of their heat transferred directly to the plane leading to very poor thermal efficiency. Preheating the board can bring the internal plane temperature high enough that the impact on thermal transfer efficiency is minor. A hot-air BGA rework station will typically have the hot-air head on top responsible for most of the soldering but a hot-air head on the bottom as well that's used to preheat the board before the top is brought to a temperature that will melt the solder. Without the preheat, there will be failures. Lots. Epoxy-glass is a thermal insulator. Planes need to heat up through the exposed copper connections and the epoxy-glass. It takes time to get to temperature. Different reflow methods have different requirements to get good process yield. In a well-tweaked process it shouldn't matter if there are direct-connects to the planes or not. If the process is even a little sloppy, the direct-connections can sincerely degrade process yield. There are shops that offer reasonably-prices xray inspection that should expose any soldering faults. You can even find a shop on eBay (based in AZ?) that offers a $50 service - search on "xilinx xray inspection" and you'll find the eBay store listing. One test that might produce results: use a diode checker on your unpowered board's I/O pins. If the protection diodes are engaged when the device is off and unconfigured, you should see the diodes for the I/O pins to the VCCO of the associated banks. My S3E starter board shows about 0.4V on the I/Os I probed with the doide-checker (standard DMM function) COM/black on the VCCO pin (there's a jumper for 3.3V/2.5V so I know it was unconnected) and the V/ohm/red lead on the I/O pads. If your VCCO is unconnected you should see no-connects or simply much larger values (typically 1.2 V on my board) from other circuits. COM on floating VCCO plane - 0.4V, COM on 3.3V plane - 1.2V, COM on 2.5V plane - 1.2V. Connect the plane to the VCCO and the 0.4V is seen from the voltage plane to the I/O. Happy hunting!Article: 115634
Thanks for the in-depth description. I went back and checked, and all balls are connected to escaped vias. There are no direct plane connections. When we got the board back from the surface mount shop, I was told that they had X-ray'd the boards and they had both checked out. I will preform the test that you describe to see what that reveals. Thank you again for your help. -BenArticle: 115635
"bengineerd" <bengineerd@gmail.com> wrote in message news:1171571929.744945.217470@q2g2000cwa.googlegroups.com... > > Thanks for the in-depth description. I went back and checked, and all > balls are connected to escaped vias. There are no direct plane > connections. When we got the board back from the surface mount shop, > I was told that they had X-ray'd the boards and they had both checked > out. I will preform the test that you describe to see what that > reveals. > > Thank you again for your help. > -Ben A quick caution: I/Os that are connected to other chips with the same supply rail as the VCCO may give a false "connected" reading if their protection diodes kick in but the FPGA's I/Os are left floating. The quick test I did on the starter board was with unconnected I/O pins (signals brought out to headers).Article: 115636
Hi, I have a small microblaze system with my own ipif peripheral. In this peripheral I want to use a vhdl block which is also used in another part of my project. Is this possible? Because when building the system, the edk looks in the pcores/<peripheral name>/hdl/vhdl directory for sources (where it doesn't find the shared vhdl part and I don't want to place the shared vhdl code in this directory!). TIA, FrankArticle: 115637
On Feb 15, 1:03 pm, David Brown <d...@westcontrol.removethisbit.com> wrote: > Nico Coesel wrote: > > "llandre" <llan...@libero.it> wrote: > > >> In this message > >>http://groups.google.it/group/comp.arch.fpga/browse_thread/thread/4b6... > >> Josh Rosen provided detailed information about comparative performance > >> tests he made (see alsohttp://www.polybus.com/linux_hardware/ > >> index.htm). > >> When he posted that message AMD processors were definitively the best > >> choiche. Did something changed since then? Have Intel processors > >> released in the meanwhile filled the gap? > > > Based on 10 years of experience I recommend to stay away from AMD > > based system for any serious computing. AMD based systems are low > > budget systems based on crappy chipsets and crappy components and > > because of that they lack a very important feature: stability. I've > > never seen an AMD based system survive a day in the office without > > crashing. Most people will tell you their AMD system _at home_ works > > perfectly. But tell me, is a PC at home used extensively for 10 hours > > straight? I don't think so. > > That may have had some merit as an argument 10 years ago, but it is > totally at odds with most people's experiences since then. AMD has been > the manufacturer of choice for serious computing since the Opteron's > first came out - again and again, they have given more powerful and > scalable than Intel's solutions, and the processors left stability > problems behind with the K6 generation. There have been issues with > heat - many of AMD's chips in the last five years have run particularly > hot, and if you buy a cheap system then it's cooling system might not be > good enough. And if you want to talk about motherboard and chipset > issues, then Intel has far outweight AMD for problems in recent years - > mostly because, until the Core 2, it has been rushing out everything it > can in hopes of competing with AMD. > > In my own experience, I have picked AMD on almost every occasion in the > last fifteen years - first purely for value for money, and later for > reliability as well. Were I buying a new machine today, I would > probably go for a Dual Core 2, simply because of better value for money > at the moment, although for a server I might pick AMD for stability (and > for a four-core or more machine, AMD is the only realistic choice). > > If your machines crash after a day at the office, you are doing > something terribly wrong, and the processor is the least of your > worries. Most of the machines I use and administer, at home and at the > office, are AMD's, and most of them are never turned off. I have a > server here at the office with a 300 MHz AMD K6 that has been running > for around 8 years, and has only been off a half-dozen times for power > cuts and a replacement power supply (this is probably a world record for > NT 4.0). > > And in the world of gaming, people run their machines for much longer > than 10 hours at a time, and often with more demanding loads than any > professional use - they generally choose AMD. > > There is a reason why AMD captured a large proportion of the server > market, especially for multi-core systems, despite Intel's entrenchment > (and illegal and/or unethical behaviour, for which they are currently on > trial). > > > If you want a computer get an Intel cpu based professional workstation > > from the business section from Dell or HP. You'll probably notice the > > price difference between the computer shop around the corner, but > > believe me, the price difference is worth having a PC that just works > > fine every day. Large companies buy PCs like these by the thousands > > for a good reason: a PC which doesn't work/crashes costs a lot of > > money. > > This is a totally different issue. If you want a reliable machine, be > prepared to spend money on it and get it from a reliable supplier. No > one will argue with that. Don't buy AMD processors because they are > cheap - buy the appropriate chip for the job. There is a major risk for me missing the point here, but I'll give it ago anyway! The original question takled about the ISE and Dual Cores.... why would you need Dual Core for ISE? It does never use more than one of them anyway! OK it'll give your windows/Linux better response for other things while running ISE but it will NOT speed up the actual Synthesis+P&R action. Have any of you guys had ANY luck with using the "second" one within ISE? Maybe someone from Xilinx care to answer. If my memory serves me Xilinx made a statement that the ISE 8.1 would add support for Dual-Cores when running the tools. OK i gogled for that too.. http://www.eeproductcenter.com/pld-fpga/ showArticle.jhtml?articleID=174918452 I did NOT notice any improvement between 7.1 and 8.1 using my AMD 3800+ X2 when building a bigger project (a big project for me is a project that fills my S3 StarterKit 200K). It actually got slower! And now in ISE 9.1 (webpack) I did not see any signs of the normal ISE toolchain having any support at all for Dual Cores? I did a more through post here: http://www.journalforums.com/cgi-bin/ikonboard.cgi? act=ST;f=1;t=57 that you can read and comment on here in this newsgroup.Article: 115638
Well, it seems I need the latest NCSim. I found out my company has licenses and access to ModelSimSE. So I am moving to that. They seem to be partnered with Xilinx pretty well.Article: 115639
>> > > If you do, every clock, > > out = out + (in-out)/k > > that approximates a single-pole RC lowpass filter. The divide by K can > just be a right-shift by R bits. Ideally you should lose no bits, so > if the input is digitized to N bits, do the math to N+R bits width. > > (in-out) is of course signed. > > If the clock period is T, then for a unit step input, the first output > step has amplitude 1/k, so the effective tau is T*k, so the corner > frequency is 1/(2*pi*T*K). > > I think. > > John > Perfect, thanks very much. When I've implemented it will be on the website. Cheers, Mike.Article: 115640
jetq88 wrote: > Our design department basically split in the middle with half products > were designed with Altera parts and half products were designed with > Xilinx parts, when talking about choosing one main FPGA source, > everyone voiced different opinions. I'm about to have a new design to > process digital video signal which requires large external memory, > either DIMM DDR/DDR2 SDRAM or component DDR/DDR2 SDRAM. > First i go for Xilinx ISE9.1 webpack, quite large program, go to > CoreGen, can't find place to generate memory controller, goto Xilinx > and check MIG tool, nowhere to download MIG tool for ISE9.1. guess I > have to use old tool, then import to ISE9.1 and tweak it by myself. > downloaded Altera quartus6.1 webpack, go to megawizard, choose memory > controller, then DDR SDRAM, right there, only thing I need is to > customize it, looks like it's simpler so far, since I just get > started, no sure the road ahead yet, but from the beginning, look like > xilinx road is bumpy. > I know if I get reference design of either one, It should get the job > done, I want to listen to others out there, specially those who have > experience on both, what are your thoughts about both companies in > term of chip performance, development tool and supports, I'd like > choose a company with overall better preformance, stick with it and > forget the other one Seems a strange rationale - in fact, you've just given an example that counters your desire to go 'one vendor shop'. If you had chosen one, could you have so easily compared the flows ? In this case, Quartus gets the tick, but Peter says Xilinx have a fix coming. Altera has nothing quite like the Coolrunner devices, and Xilinx has no answer to MAX II - so do you really want to restrict your design choices that much ? Plus there is the real benefit of sales leverage others have mentioned. Do you have Lattice tools there ? -jgArticle: 115641
Do you like Virtex-5 ? Then please vote for it... The editors of Electronic Design News think Virtex-5 is an innovative product; they have nominated for their 17th Annual EDN Innovation Awards: the Xilinx Virtex-5 Design Team for "Innovator of the Year," and the Virtex-5 LXT platform for "Innovation of the Year" (in the Digital ICs category) EDN is asking their readers to select the winner. =B7 Learn more ( http://www.xilinx.com/prs_rls/2007/silicon_vir/ 0727_ednawards.htm ) =B7 Vote now! ( www.edn.com/innovationballot.asp ) And confirm your vote as soon as you receive an automated email from EDN. Peter Alfke, Xilinx Applications, and proud of it !Article: 115642
In article <1171576522.086383.317010@h3g2000cwc.googlegroups.com>, spartan3wiz <magnus.wedmark@gmail.com> wrote: >There is a major risk for me missing the point here, but I'll give it >ago anyway! The original question takled about the ISE and Dual >Cores.... why would you need Dual Core for ISE? It does never use more >than one of them anyway! Because the fast (2.4GHz and above) Core 2 Duo chips get you 4MB of level-2 cache which, if you're using ISE on only one core and not doing anything very intensive in the background, is all available to the ISE process. Given how much of a boost people saw with 1MB-cache versus 512k-cache AMD chips, and how memory-intensive FPGA compilation is, I would expect 4MB to be distinctly useful. TomArticle: 115643
Peter Alfke wrote: > Do you like Virtex-5 ? Then please vote for it... > > The editors of Electronic Design News think Virtex-5 is an innovative > product; > they have nominated for their 17th Annual EDN Innovation Awards: > > the Xilinx Virtex-5 Design Team for "Innovator of the Year," and > > the Virtex-5 LXT platform for "Innovation of the Year" (in the > Digital ICs category) > > EDN is asking their readers to select the winner. > > · Learn more ( http://www.xilinx.com/prs_rls/2007/silicon_vir/ > 0727_ednawards.htm ) > > · Vote now! ( www.edn.com/innovationballot.asp ) > And confirm your vote as soon as you receive an automated email from > EDN. > > Peter Alfke, Xilinx Applications, and proud of it ! I see a pretty small category : ( where do these guys get their candidates ? - could it be advertiser revenue ? ) They also miss a [none of the above] vote, so readers cannot indicate if they agree with the shortlists. Digital ICs, programmable logic, and memory: PEX 8548 PCI Express switch (PLX Technology) MR2A16A MRAM (Freescale) Virtex-5 LXT FPGAs (Xilinx) and since the award is for innovation : Adj. 1. innovative - ahead of the times; 2. innovative - being or producing something like nothing done or experienced or created before; then the clear winner (by a large margin) is the MRAM. That's far closer to innovative than "another iteration in FPGAs" ? -jgArticle: 115644
Peter Alfke wrote: > Do you like Virtex-5 ? Then please vote for it... What do I do if I think Virtex-5 is really cool but no normal user can take delivery of one? Most awards (e.g. the Oscars) are for products which are in meaningful production. Which doesn't seem to be the case for Virtex-5, and for Virtex-4, if distributor stockholdings are anything to go by.Article: 115645
On Feb 15, 5:06 pm, Tim <t...@nooospam.roockyloogic.com> wrote: > Peter Alfke wrote: > > Do you like Virtex-5 ? Then please vote for it... > > What do I do if I think Virtex-5 is really cool but no normal user can > take delivery of one? > > Most awards (e.g. the Oscars) are for products which are in meaningful > production. Which doesn't seem to be the case for Virtex-5, and for > Virtex-4, if distributor stockholdings are anything to go by. Put in an order for 1000 pieces of any Virtex-5 LX or LXT (except perhaps for the biggest -330 parts) with the ES suffix (early silicon =with errata sheet), and watch us ship from inventory. The trouble with distributors is that they do not want or like to stock "ES" parts. It's s sad story, for these ES parts are what seeds the important innovative user designs. But the distributor will (must!) take your order for shipment from Xilinx. There is no scarcity of Virtex-5 LX and LXT devices ! Our two foundries know how to make them in quantity... Complain to me if you encounter a delivery problem of ES devices. (peter@xilinx.com) Peter Alfke, not in Sales or Marketing, but with close ties to it.Article: 115646
Tim, Well, that is odd, because we have ES material in stock (for V5). In the V5 program, we have met, or met early every public date we gave. After the V4 issues with FX MGT, we promised ourselves to never do that, ever. Never. Ever. So, if you are with-holding your vote because of your V4FX experience, we apologise, and promise to do much better (and are doing much better). Peter and I have personally helped a few folks get their hands on their V5 ES parts, when it seemed that the distributors had failed them. If your distributor has failed you, we want to know. As to who you want to vote for, you can always vote (in another beauty contest) for the "most innovative product in 2006 -- the Stratix III." (Note, quotes are from a press release!). That is a good one: the product will sample in September, 2007.... Of course, it is a free Internet, and the chip you should vote for is the one that best fit the criteria as you decide. AustinArticle: 115647
morpheus wrote: > Hi There! > I am designing a digital AM/FM receiver in a Vertex-4 FPGA. I have > designed the system blocks but have one question regarding digital > filtering. >>From a systemic point of view, we are using the DDC approach to > convert IF 45MHz down to baseband. After this we are using a 40MSPS A/ > D to sample and output parallel 12-bit I, Q data to the FPGA. > The FPGA front end has to have a LPF with a cut-off frequency of 5kHz. > After the LPF, AM and FM need to be demodulated. I intend to do > demodulation as follows > FM -> (Q(n)I(n-1) - I(n)Q(n-1))/(I-Sq + Q-Sq) > AM -> (I-Sq + Q-Sq) > My question is: > I need to do some decimation (to make my life easier when it comes to > 5kHz LPF design)...what is the best way of doing this? I have read > some material and it seems to point towards cascaded CIC filters. > Please comment and also let me know if you notice any flaw in my > design methodology. Moreover, due to my inexperience in this field, I > wanted to know if decimation upstream would affect (adversely) my AM/ > FM demodulation process. > > cheers > Morpheus > If you are externally downconverting to baseband, there is no need to be sampling at 40 MS/sec, the DDC should have a low pass filter in it. If on the other-hand, all you have is a mixer, then the filtering makes sense. In that case, you probably want a CIC followed by one or more decimating FIR filters. In the receivers I've done, I sample the IF directly and do the downconversion in the FPGA rather than doing it outside. The CIC itself is a somewhat crude low pass filter (it has a sinx/x frequency characteristic) that makes it well suited for decimating, especially by large ratios. The shortwave receiver shown on the home page of my website actually samples the RF directly and the FPGA (a Spartan2-100) does the tuning, down conversion and demodulation for AM and AM SSB. An FM demodulator can be added with little extra real-estate by using bit serial arithmetic. In that case, the RF is sampled at 40 MHz, and downconverted to complex base-band. The 40 MHz was dictated by the ADC's max sample rate. Considering the lack of an RF front end (the ADC input was connected to a long wire antenna through an antenna preamp) on this receiver it actually worked surprisingly well. I've done other designs that sample the RF or IF as high as 500MS/sec. At a 5KHz cutoff, you are sampling at a very low (for FPGAs) rate, so the demodulation can be done bit serial. A CORDIC rotator is one way of deriving both AM and FM, as it produces amplitude and phase. Differencing the phase will get you the FM (you'll probably also want to put a DC blocker or add a frequency lock loop before the CORDIC to remove any residual carrier), and you may find you need an automatic gain control for the AM. The decimation upstream is actually preferable since it lets you work at a lower sample rate, which in turn lightens the processing load.Article: 115648
Peter Alfke wrote: > On Feb 15, 5:06 pm, Tim <t...@nooospam......com> wrote: >> Peter Alfke wrote: >>> Do you like Virtex-5 ? Then please vote for it... >> What do I do if I think Virtex-5 is really cool but no normal user can >> take delivery of one? >> >> Most awards (e.g. the Oscars) are for products which are in meaningful >> production. Which doesn't seem to be the case for Virtex-5, and for >> Virtex-4, if distributor stockholdings are anything to go by. > > Put in an order for 1000 pieces of any Virtex-5 LX or LXT (except > perhaps for the biggest -330 parts) with the ES suffix (early silicon > =with errata sheet), and watch us ship from inventory. Not practical. There is no published pricing for these parts and distribution refuses to give pricing without an order. To be blunt, Peter, you know that I have the highest regard for Xilinx, but the way you conduct your sales business these days is very disheartening. An unblinking concentration on the major accounts is just fine, but for the great majority of users: - you cannot buy the Virtex-5 - you cannot buy most of the Virtex-4 range - you cannot buy the Spartan-3E - you cannot buy the Spartan-3A - the Xilinx online store gives a new meaning to "store" If you think I'm exaggerating, try the Avnet site: Virtex-5 parts: all out of stock, no pricing Virtex-4 parts: out of 243 parts (mostly priced!) just 59 are available Spartan-3A parts: "Part is not found as a stocked item" Spartan-3E parts: prototype parts only and no higher volume pricing NuHo show pretty much the same results. If you, or anyone else in Xilinx, would like to improve matters, could you please publish a comprehensive price and availability list for the various families. Then the poor old working engineer can make a cost/benefit/risk analysis - after all, that's what you want your customers to do before setting forth on designs.Article: 115649
Tim wrote: > > If you think I'm exaggerating, try the Avnet site: As an equal-opportunity economist, I tried the Stratix numbers at the Arrow site. As far as I can tell the StratixIII (EP3S) doesn't have an entry, like the Virtex-5. The StratixII (EP2S) picture appears to be about the same as the Virtex-4. I didn't check their equivalents to Spartan3. But I'm not at all familiar with Altera and someone more in that culture may care to check or comment.
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