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In article <1137904787.597157.249800@z14g2000cwz.googlegroups.com>, <bill.sloman@ieee.org> wrote: > > I see a lot of fat kids, but precious few skinny ones. > > http://www.childinfo.org/areas/malnutrition/wasting.php > > 0.6 moderately wasted kids per 100,000 isn't all that many, and such > kids aren't all that active, so I'm not surprised that you haven't seen > them. You are misreading the table. It is in percent, not in per 1e5. So 6 per thousand, according to the table. But then you read the footnote, and see that 'moderately wasted' means: * Below minus two standard deviations from median weight for height of reference population If you had a 'normal distribution' (Gaussian) of weights, then you would expect 2.2% (22 per thousand) to be below the median (which would also be the mean) by more than two standard deviations. It doesn't mean that those 0.6% are or are not malnourished. Elsewhere in this thread > <bill.sloman@ieee.org> wrote in message > > And you seen happy to neglect the malnutrition problem that you do have > > in raising kids in the U.S. In Europe, former Yugoslavia, The Czech > > Republic, Hungary and Romania do worse, but everybody else does > > appreciably better. But the table you cite in trying to bolster your argument has the US as having the SMALLEST reported percentage of wasting. (European countries tend to have no data listed.) Which is support for calling Americans lard-asses (which everyone does) but not for your contention that malnutrition is worse in the US than in most Euro countries. -- David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com)Article: 95301
Antti Lukats <antti@openchip.org> wrote in message dqtefv$pkp$1@online.de... > > ASFAIK it is only available upon request from FAE, not freely > downloadable But what exactly is it for?!? Is it something to cope with the lack of T-bufs in most recent devices, or is it a tool that only helps with the modular design flow? A.D.Article: 95302
Bryan Hackney wrote: > Ray Andraka wrote: [...] > > The worst engineer I knew was an EE - PE. Never designed a damn thing. > Knew how to dress, though. > > But then, he "was" an EE in a field where PE mattered - building systems, > plant stuff, etc. Certainly not eletronic design. What can I add to what > Paul Carpenter wrote? Certain companies needs PEs as window dressing, > the same way some rich heiresses need poodles. > P.S. I've seen you use PE in your title. I did not mean to insult. Your assertions seem to be contrary to many engineers' experiences.Article: 95303
"David M. Palmer" wrote: > In article <1137904787.597157.249800@z14g2000cwz.googlegroups.com>, > <bill.sloman@ieee.org> wrote: > > > > I see a lot of fat kids, but precious few skinny ones. > > > > http://www.childinfo.org/areas/malnutrition/wasting.php > > > > 0.6 moderately wasted kids per 100,000 isn't all that many, and such > > kids aren't all that active, so I'm not surprised that you haven't seen > > them. > > You are misreading the table. It is in percent, not in per 1e5. So 6 > per thousand, according to the table. > > But then you read the footnote, and see that 'moderately wasted' means: > * Below minus two standard deviations from median weight for height of > reference population > > If you had a 'normal distribution' (Gaussian) of weights, then you > would expect 2.2% (22 per thousand) to be below the median (which would > also be the mean) by more than two standard deviations. > > It doesn't mean that those 0.6% are or are not malnourished. > > Elsewhere in this thread > > <bill.sloman@ieee.org> wrote in message > > > And you seen happy to neglect the malnutrition problem that you do have > > > in raising kids in the U.S. In Europe, former Yugoslavia, The Czech > > > Republic, Hungary and Romania do worse, but everybody else does > > > appreciably better. > > But the table you cite in trying to bolster your argument has the US as > having the SMALLEST reported percentage of wasting. (European > countries tend to have no data listed.) Which is support for calling > Americans lard-asses (which everyone does) but not for your contention > that malnutrition is worse in the US than in most Euro countries. Malnourishment can simply mean having a poor *quality* diet missing important nutrients. There isn't necessarily any correlation with 'wasting' i.e. low weight. Interestingly, the poor quality diet may result in the person feeling underfed and this can then lead to overeating and obesity. So you can end up with overweight malnourished ppl. GrahamArticle: 95304
Ray Andraka wrote: > Joerg wrote: > [...] > > A few points here: > 1) You can obtain a PE license in any state that adheres to the NSPE > guidelines without a degree if you have 20 years experience in the > field. That invalidates your concern about ABET certification, since > most engineering schools in the US have had the certification for the > past 20 years. > > 2) Passing the test is only one of the wickets you need to pass through. > At least as important as the test, is your references who ascribe to > know your work and attest that it is worthy of a professional. > > 3) Finding the PE references is a little harder as an EE, but is not > impossible. There's a good chance, for example, that a mechanical > engineer in your firm has his PE and can truthfully sign off as being Most MEs know a little about high speed digital circuit design. NOT! My degree is ME, and I can attest that our academic electrical exposure was little and bad. > familiar with your work. If you have outside consultants doing work > (not contractors, consultants) for your company, one or more of them > will likely have a P.E. As a last resort, there is nothing stopping you > from joining the local chapter of NSPE and getting friendly with the > members. Many would be very interested in hearing about your work. They > really are a likeable lot. :-) > > 4) Most states in the US DO REQUIRE someone on staff with a PE license > if you are offering engineering services in any form to the public. If, > as you signature suggests, you are a consultant offering design His signature does not indicate he offers engineering services. Consultant could mean financial consultant. That's where the term consultant is most often used. > services, you DO NEED to have someone with a PE license on your staff in > most of the 50 states. Some states prosecute that more aggressively > than others. My state took all of about 6 months to find me after I From what I remember, using the unqualifed term "engineer" in business may get one in trouble. Using the term "software engineer" is harmless as well as meaningless. > hung my shingle out. In most cases, the state has the authority to issue > a cease and desist order against you if you cannot prove you have a PE > on staff. > > 5) Having a PE license doesn't give you carte blanche to go out and do > stuff outside of your area of expertise. In fact, the code of ethics > specifically states that you won't sign off on stuff that is not in your > area of expertise. > > 6) Some of the medical firms I've dealt with specifically do require a > PE on a project involving medical equipment that could potentially > endanger a patient. I'm not sure if it is a regulatory requirement or > not, but it was a requirement from somewhere. If you are working for a > medical firm, ask around. I'll bet there is a PE involved somewhere in > the project. Every medical project I've been involved with has had a PE > directly involved with the project. > A rarified world. I vaguely remember a 3.95 GPA requirement for getting into "medical engineering", a program I'm not sure even exists anymore. > 7) PE licensing is intended to protect the public by certifying that you > have demonstrated competency as an engineer in your field. You needn't > have the PE to do engineering work, but if the engineering services are > offered to the public, someone with a PE has to be accountable for the > work.Article: 95305
Hello,
with the following code snipped I have Problems on synthese/fit
process on xst Web/ISE 8.1 (the behavioral simulation works fine) for
a CPLD XC95000:
---8<---
library ieee;
use ieee.std_logic_1164.all;
entity synchronized_gate is
generic (
RESET_ACTIVE : std_logic := '1');
port (
reset : in std_logic;
clk : in std_logic;
start : in std_logic; -- start synchronizing
stop : in std_logic; -- stop synchronizing
en : out std_logic);
end entity synchronized_gate;
architecture behavioral of synchronized_gate is
signal arm : std_logic;
begin
-- arming RS-FF (asynchronous, latch inference)
arming_ff : process (reset, start, stop) is
begin
if (reset = RESET_ACTIVE) then
arm <= '0';
-- stop has precedence before start!
elsif (stop = '1') then
arm <= '0';
elsif (start = '1') then
arm <= '1';
end if;
end process arming_ff;
-- edge triggered gate control FF
clk_gate : process (clk, reset) is
begin
if (reset = RESET_ACTIVE) then
en <= '0';
elsif rising_edge(clk) then
en <= arm;
end if;
end process clk_gate;
end architecture behavioral;
--->8---
The synthese say:
WARNING:Xst:737 - Found 1-bit latch for signal <arm>.
which is OK. The fitter message is:
WARNING:Cpld:1007 - Removing unused input(s) 'stop'. The input(s) are
unused
WARNING:Cpld:828 - Signal 'arm.RSTF' has been minimized to 'GND'.
Well, looking at RTL and Technology Schematics all is as expected. If
I have a look into the generated post fit vhdl file, the signal stop
is really missing.
What are xst doing here, why?
Using Fitter's "preserve unused input" preserves the signal self, but
the signal stop doesn't have any functionality any more.
Therefore all post-fit simulation fails. Any help here?
Regards,
Olaf
Article: 95306maybe, the fitter report may help: >>>>> file removed from archiveArticle: 95307
David M. Palmer wrote: > In article <1137904787.597157.249800@z14g2000cwz.googlegroups.com>, > <bill.sloman@ieee.org> wrote: > > > > I see a lot of fat kids, but precious few skinny ones. > > > > http://www.childinfo.org/areas/malnutrition/wasting.php > > > > 0.6 moderately wasted kids per 100,000 isn't all that many, and such > > kids aren't all that active, so I'm not surprised that you haven't seen > > them. > > You are misreading the table. It is in percent, not in per 1e5. So 6 > per thousand, according to the table. Shit. You seem to be right. My apologies to the group, and my thanks to David M. Palmer. I've been reading too many medical statistics where they do quote per 100,000. > But then you read the footnote, and see that 'moderately wasted' means: > * Below minus two standard deviations from median weight for height of > reference population > > If you had a 'normal distribution' (Gaussian) of weights, then you > would expect 2.2% (22 per thousand) to be below the median (which would > also be the mean) by more than two standard deviations. The distribution is the big if. Children's weights will obviously not lie on a Gaussian distribution - there will be a lot more very fat children than very skinny children, because gross obesity takes a long time to kill you, while starvation can do for a kid in a few weeks. As John Larkin has point out, most of the variability in the U.S. population is going to be concentrated in the fat kids. > It doesn't mean that those 0.6% are or are not malnourished. Seems very likely that they are. Children starve a lot fasster than adults. > Elsewhere in this thread > > <bill.sloman@ieee.org> wrote in message > > > And you seen happy to neglect the malnutrition problem that you do have > > > in raising kids in the U.S. In Europe, former Yugoslavia, The Czech > > > Republic, Hungary and Romania do worse, but everybody else does > > > appreciably better. > > But the table you cite in trying to bolster your argument has the US as > having the SMALLEST reported percentage of wasting. (European > countries tend to have no data listed.) Which is support for calling > Americans lard-asses (which everyone does) but not for your contention > that malnutrition is worse in the US than in most Euro countries. There is other evidence that suggests that juvenile malnutrition is vanishingly rare in most Western European countries, and appreciably less common than in the U.S.A. http://unstats.un.org/unsd/databases.htm > -- Bill Sloman, NijmegenArticle: 95308
"Olaf Petzold" <olaf@mdcc-fun.net> schrieb im Newsbeitrag news:dqvdse$jnd$1@viper.mdlink.de... > Hello, > > with the following code snipped I have Problems on synthese/fit process on > xst Web/ISE 8.1 (the behavioral simulation works fine) for a CPLD XC95000: > [snip] Hi Olaf, this is what 8.1 does from your code (I copy pasted your code with NO mods!!), XC9500 as target -------- arm <= ((start AND NOT reset AND NOT stop) OR (NOT reset AND NOT stop AND arm.LFBK)); FDCPE_en: FDCPE port map (en,arm.LFBK,clk,reset,'0'); -------- as you see the stop input is present and not optimized away !! AnttiArticle: 95309
Thanks Antti,
> this is what 8.1 does from your code (I copy pasted your code with NO
using the same (with sp1)
> mods!!), XC9500 as target
>
> --------
>
> arm <= ((start AND NOT reset AND NOT stop) OR (NOT reset AND NOT stop AND
> arm.LFBK));
> FDCPE_en: FDCPE port map (en,arm.LFBK,clk,reset,'0');
>
> --------
>
> as you see the stop input is present and not optimized away !!
interesting, from what file is it? Attached my fitted file with entity.
I've got from Fitter report:
********* Errors and Warnings ***************************
WARNING:Cpld:1007 - Removing unused input(s) 'stop'. The input(s) are
unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:828 - Signal 'arm.RSTF' has been minimized to 'GND'.
The signal is removed.
^^ There is my problem!
********** Mapped Logic **********
FDCPE_arm: FDCPE port map (arm,'0','0','0',start);
FDCPE_en: FDCPE port map (en,arm.LFBK,clk,reset,'0');
Register Legend:
FDCPE (Q,D,C,CLR,PRE);
FTCPE (Q,D,C,CLR,PRE);
LDCP (Q,D,G,CLR,PRE);
Maybe a question of right compiler switches (got from fitter report)?:
Device(s) Specified : xc95144-7-PQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : ON
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 50
Thanks and regards,
Olaf
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: I.25
-- \ \ Application: netgen
-- / / Filename: synchronized_gate_timesim.vhd
-- /___/ /\ Timestamp: Sun Jan 22 10:23:01 2006
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -rpw 100 -ar Structure -tm synchronized_gate -w -dir netgen/fit -ofmt vhdl -sim synchronized_gate.nga synchronized_gate_timesim.vhd
-- Device : XC95144-7-PQ100 (Speed File: Version 3.0)
-- Input file : synchronized_gate.nga
-- Output file : D:\electronic\projects\mfgc\xst\netgen\fit\synchronized_gate_timesim.vhd
-- # of Entities : 1
-- Design Name : synchronized_gate.nga
-- Xilinx : C:\Programme\Xilinx\xst
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity synchronized_gate is
port (
reset : in STD_LOGIC := 'X';
clk : in STD_LOGIC := 'X';
start : in STD_LOGIC := 'X';
en : out STD_LOGIC
);
end synchronized_gate;
architecture Structure of synchronized_gate is
signal FSRIO_1_1 : STD_LOGIC;
signal FCLKIO_0_2 : STD_LOGIC;
signal start_IBUF_3 : STD_LOGIC;
signal en_OBUF_4 : STD_LOGIC;
signal en_OBUF_Q : STD_LOGIC;
signal Gnd_5 : STD_LOGIC;
signal en_OBUF_tsimcreated_prld_Q_6 : STD_LOGIC;
signal en_OBUF_D_7 : STD_LOGIC;
signal Vcc_8 : STD_LOGIC;
signal en_OBUF_D1_9 : STD_LOGIC;
signal en_OBUF_D2_10 : STD_LOGIC;
signal arm_FBK_11 : STD_LOGIC;
signal arm_Q : STD_LOGIC;
signal arm_D_12 : STD_LOGIC;
signal arm_CLKF_13 : STD_LOGIC;
signal arm_SETF_14 : STD_LOGIC;
signal arm_D1_15 : STD_LOGIC;
signal arm_D2_16 : STD_LOGIC;
begin
FSRIO_1 : X_BUF
port map (
I => reset,
O => FSRIO_1_1
);
FCLKIO_0 : X_BUF
port map (
I => clk,
O => FCLKIO_0_2
);
start_IBUF : X_BUF
port map (
I => start,
O => start_IBUF_3
);
en_0 : X_BUF
port map (
I => en_OBUF_4,
O => en
);
en_OBUF : X_BUF
port map (
I => en_OBUF_Q,
O => en_OBUF_4
);
en_OBUF_tsimcreated_prld_Q : X_OR2
port map (
I0 => FSRIO_1_1,
I1 => Gnd_5,
O => en_OBUF_tsimcreated_prld_Q_6
);
Gnd : X_ZERO
port map (
O => Gnd_5
);
en_OBUF_REG : X_FF
generic map(
INIT => '0'
)
port map (
I => en_OBUF_D_7,
CE => Vcc_8,
CLK => FCLKIO_0_2,
SET => Gnd_5,
RST => en_OBUF_tsimcreated_prld_Q_6,
O => en_OBUF_Q
);
Vcc : X_ONE
port map (
O => Vcc_8
);
en_OBUF_D : X_XOR2
port map (
I0 => en_OBUF_D1_9,
I1 => en_OBUF_D2_10,
O => en_OBUF_D_7
);
en_OBUF_D1 : X_ZERO
port map (
O => en_OBUF_D1_9
);
en_OBUF_D2 : X_AND2
port map (
I0 => arm_FBK_11,
I1 => arm_FBK_11,
O => en_OBUF_D2_10
);
arm_FBK : X_BUF
port map (
I => arm_Q,
O => arm_FBK_11
);
arm_REG : X_FF
generic map(
INIT => '0'
)
port map (
I => arm_D_12,
CE => Vcc_8,
CLK => arm_CLKF_13,
SET => arm_SETF_14,
RST => Gnd_5,
O => arm_Q
);
arm_D : X_XOR2
port map (
I0 => arm_D1_15,
I1 => arm_D2_16,
O => arm_D_12
);
arm_D1 : X_ZERO
port map (
O => arm_D1_15
);
arm_D2 : X_ZERO
port map (
O => arm_D2_16
);
arm_CLKF : X_ZERO
port map (
O => arm_CLKF_13
);
arm_SETF : X_AND2
port map (
I0 => start_IBUF_3,
I1 => start_IBUF_3,
O => arm_SETF_14
);
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => PRLD);
end Structure;
Article: 95310
Frank,
See:
http://www.deepchip.com/posts/0184.html
HTH
Ajeetha
www.noveldv.com
Article: 95311PicoLA is a very simple logic anlazer created by dulse electronics available as free download there http://www.dulseelectronics.com/download/download_index.html the original design incluses some Excel spreadsheat as "GUI" ther are explanations how to use it, but well I never understood the excle thing and it did not seem to work so here is a very simple GUI http://xilant.com/component/option,com_remository/Itemid,53/func,fileinfo/id,10/ it support the original command set of the PicoLA logic analyzer Antti PS the original FPGA project has one small bug in te statemachine that gets stalled so that should be fixed before the original FPGA code can be usedArticle: 95312
"Olaf Petzold" <olaf@mdcc-fun.net> schrieb im Newsbeitrag news:dqvj42$kfi$1@viper.mdlink.de... > Thanks Antti, > >> this is what 8.1 does from your code (I copy pasted your code with NO > > using the same (with sp1) > >> mods!!), XC9500 as target >> >> -------- >> >> arm <= ((start AND NOT reset AND NOT stop) OR (NOT reset AND NOT stop AND >> arm.LFBK)); >> FDCPE_en: FDCPE port map (en,arm.LFBK,clk,reset,'0'); >> >> -------- >> >> as you see the stop input is present and not optimized away !! > > interesting, from what file is it? Attached my fitted file with entity. > > I've got from Fitter report: Dear Olaf, 1) do not try to oversmart the tools, it doesnt work. I do not know what you are doing, but when I tested your code in new project all default setting all worked properly. 2) it looks like the code you have trouble is part of logic analyzer - so call me killjoy, but XC95xx is not a part you would use for logic analyzer, so select suitable device and the problem you are having would not be there at all. doing a logic analyzer (a simple one) is really piece of cake. doing a good one just means doing the specifications the implementation is not an issue at all. I just feel that you have spend a lot of your time in your logic analyzer project without having anything useable to demonstrate so far. I just dont have enough fingers (only 37 on last count) to implement some logic analyzer properly, I would do it targettable to any Xilinx FPGA using configuration readback (capture storage reading ) and partial reconfiguration (for trigger settings). AnttiArticle: 95313
Hi, Olaf:
Please complete all the state in your if-else statement.
"Olaf Petzold" <olaf@mdcc-fun.net> ??????:dqvdse$jnd$1@viper.mdlink.de...
> Hello,
>
> with the following code snipped I have Problems on synthese/fit process on
> xst Web/ISE 8.1 (the behavioral simulation works fine) for a CPLD XC95000:
>
> ---8<---
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity synchronized_gate is
> generic (
> RESET_ACTIVE : std_logic := '1');
> port (
> reset : in std_logic;
> clk : in std_logic;
> start : in std_logic; -- start synchronizing
> stop : in std_logic; -- stop synchronizing
> en : out std_logic);
> end entity synchronized_gate;
>
> architecture behavioral of synchronized_gate is
> signal arm : std_logic;
> begin
> -- arming RS-FF (asynchronous, latch inference)
> arming_ff : process (reset, start, stop) is
> begin
> if (reset = RESET_ACTIVE) then
> arm <= '0';
> -- stop has precedence before start!
> elsif (stop = '1') then
> arm <= '0';
> elsif (start = '1') then
> arm <= '1';
> end if;
> end process arming_ff;
>
> -- edge triggered gate control FF
> clk_gate : process (clk, reset) is
> begin
> if (reset = RESET_ACTIVE) then
> en <= '0';
> elsif rising_edge(clk) then
> en <= arm;
> end if;
> end process clk_gate;
> end architecture behavioral;
> --->8---
>
> The synthese say:
> WARNING:Xst:737 - Found 1-bit latch for signal <arm>.
> which is OK. The fitter message is:
> WARNING:Cpld:1007 - Removing unused input(s) 'stop'. The input(s) are
> unused
> WARNING:Cpld:828 - Signal 'arm.RSTF' has been minimized to 'GND'.
>
> Well, looking at RTL and Technology Schematics all is as expected. If I
> have a look into the generated post fit vhdl file, the signal stop is
> really missing.
>
> What are xst doing here, why?
>
> Using Fitter's "preserve unused input" preserves the signal self, but the
> signal stop doesn't have any functionality any more.
>
> Therefore all post-fit simulation fails. Any help here?
>
> Regards,
> Olaf
Article: 95314<bill.sloman@ieee.org> wrote in message news:1137903985.757432.131050@g49g2000cwa.googlegroups.com... > Don't argue with me - argue with > http://www.childinfo.org/areas/malnutrition/wasting.php There's nothing to argue about, slovenia is not listed and neither is most of EU?!?! > Former Yugoslavia is cleaning up after a nasty series of civil wars, so > it isn't surprising that your welfare system is in worse shape than the > U.S.A., but we can hope that you will be back up to the European norm - > no juvenile malnutrition (bar a few vicitims of lunatic parents) - in a > few more years. Romania is stll recovering from Ceausescu and we can > hope that they will do as well. The Czech Republic and Hungary are a > bit more puzzling. I'm worndering how much of their malnutrition is > confined to the Gypsy minority. I always thought you checked your sources very well, but apparently not so. I find that very dissapointing since you're always fiercely defending your views. Slovenia is the only country from the Ex-Yugoslavia inside EU at the moment and as such the only one you can use in your comparisons, we were talking about EU. The only war that took place here lasted 10 days, yet you can hardly call that a war. I assure you, no malnutrition of children resulted from this 10-day incident which took place 15 years ago. Our BDP, if this has any bearing at all for malnutrition, is comparable to the other, admittedly among the less wealthy EU members I listed, such as Portugal. Besides, the culture of eating is very high here. There are far less McDonalds style chains here than in the NetherLands since they're not popular with people, for example Dairy Queen went belly up years ago. Here is the full "War" story: http://www.uvi.si/10years/path/war/ -- Siol ------------------------------------------------ Rather than a heartless beep Or a rude error message, See these simple words: "File not found."Article: 95315
Alex Gibson wrote: > > You do not need an fpga for this but > > > > With PWM , simple closed loop control and a LC filter can solve your > > problem. > > A FPGA adds 7 segment display, a few buttons to adjust voltage manually > > or > > even RS-232 control is very feasable. > > ok you have a fpga then you can make it multiple output power supply. > > > > Just for fun add sinusoidal outputs to make it universal.(Again PWM) > > > > yusuf > > Could do the same with a pic or even a cpld Well, Sunday, and was just thinking about this a bit, In ANY case, when using FLASH based ROm or a FLASH based FPGA (and you will likely want a AD converter and these new Actel FPGAs have one build in... then do the PWM..... * B U T * We all know FLASH does not hold for ever, I have some PSU that are 20 years old and still work fine. So that begs the question WHAT will happen when a bit goes wrong in the EEPROM or FLASH FPGA? It *could* kick your programable FPGA output to max volts no curent limit ! So I think that in case of a FLASH based micro controller, or FPGA (so not an analog solution, or ROM based ) one MUST provide a second circuit 'crowbar' and in this case 'programmable crowbar'. Then from that POV one should actually do the PWM and compare in analog, and only use the FPGA output to perhaps set some switches to select voltage range. You *can* specify 20 years max usage in your documentation, but if the thing blows up 1M$ lab equipment one day later I wonder if they could sue you. As for the OP .. his question implies zero knowledge of FPGA and likely electronics. So I referred to monkeys to explain it. Sunday .... it is going to be very cold here too this week......Article: 95316
"Michael A. Terrell" <mike.terrell@earthlink.net> wrote in message news:43D2F4B3.7888F481@earthlink.net... > No problem. I am starting to lose my close-up eyesight to diabetes, > and have to depend on the spell checker. I have severe carpal tunnel > (The VA and Shands hospital doctors tell me the surgery won't help me) > so I have to type with just a couple fingers. That causes me a lot of > spelling errors. I get so busy trying to make sure the spelling is > correct that I sometimes forget to check the syntax. Sorry to hear it. Good luck. Steve http://www.fivetrees.comArticle: 95317
In article <SeFAf.29814$SD1.13573@tornado.texas.rr.com>, Bryan Hackney <no@body.home> writes >Ray Andraka wrote: >> Joerg wrote: >> >> 5) Having a PE license doesn't give you carte blanche to go out and do >> stuff outside of your area of expertise. In fact, the code of ethics >> specifically states that you won't sign off on stuff that is not in your >> area of expertise. >> 7) PE licensing is intended to protect the public by certifying that you >> have demonstrated competency as an engineer in your field. You needn't >> have the PE to do engineering work, but if the engineering services are >> offered to the public, someone with a PE has to be accountable for the >> work. > >The worst engineer I knew was an EE - PE. Never designed a damn thing. >Knew how to dress, though. > >But then, he "was" an EE in a field where PE mattered - building systems, >plant stuff, etc. Certainly not eletronic design. What can I add to what >Paul Carpenter wrote? Certain companies needs PEs as window dressing, >the same way some rich heiresses need poodles. It is not window dressing. As Ray said you opperate in your area of expertise. If his area was building systems and plant systems designing the low level HW or Sw may not be his area. Know how to design a safe system, the interlocks and legal/safety requirements etc. Therefor he could design a system and give the requirements spec to some one else to actually implement. On the other hand some EE PE's could design the HW but not the system or the software. PE or C.Eng etc does not mean qualified to do it al but it means qualified in certain areas and professional enough not to try and do other stuff. SO a HW PE will not attempt any critical Sw BTW Bryan could you design those systems and be sure the were safe and up to al the legal requirements? -- \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ \/\/\/\/\ Chris Hills Staffs England /\/\/\/\/ /\/\/ chris@phaedsys.org www.phaedsys.org \/\/\ \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/Article: 95318
from xilinx data2mem report file
START_RSR_TOP (Enables BRAM Redundancy Self-Repair for top half of chip)
= off.
START_RSR_BOT (Enables BRAM Redundancy Self-Repair for bottom half of
chip) = off.
so the BRAMs may have self repair enabled?
I wonder how many undocu features are there more ?
Antti
Article: 95319On 21 Jan 2006 20:10:16 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: >In article <6gh4t1d9bsi0sfs3s0ltrvfd8nuur8pfd9@4ax.com>, >Brian Drummond <brian@shapes.demon.co.uk> wrote: >>On 21 Jan 2006 09:21:06 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: >> >>>In article <3fjAf.9305$bF.2150@dukeread07>, >>>Ray Andraka <ray@andraka.com> wrote: >>>>Phil Tomson wrote: >>>> >>>>> Though, I do wonder: once we have an XDL parser, what's the next step? >>One option would be help with floorplanning or placement. >> >>My ideas on this are ill-defined, but here are a couple of >>suggestions... >>(2) take a post-PAR design which fails timings and a possibly hand >>generated (*) list of "problem" components and try to improve placement >>for those specific locations. Again, let Xilinx router take over... >> >Can XDL go back into PAR? No, but it can translate back to a new .ncd file. Which WILL go back into PAR - look at "re-entrant routing" and/or "guided design" in the documentation. >>A tool which took a failed PAR and its TWR and had, say, 80% chance of >>fixing the failing paths quite quickly (i.e. not overnight!) might win a >>few friends... > >But again, how would we get back into PAR from XDL, can you offer more >details? I suppose if PAR doesn't accept XDL, that it must accept a list of >critical nets and we would generate that based on the knowledge extracted from >the XDL and timing report. I don't think you need more than the above - and I haven't tried it since Foundation 3.1. It seemed to work but I don't recall actually modifying the XDL. >>For bonus points, let it replicate that FF (or LUT in a carry chain) >>that REALLY needs to be in two opposite corners of the chip at once! The more I think about it, the more this one appeals. It's simple, pragmatic, and fairly testable. >>>...and here's a concern I have: >>>If an open source ecosystem were to grow up around >>>XDL might Xilinx decide that they are uncomfortable with that >>If XDL helps sell Brand X chips ... >> >>Another valid concern would be - if the open source tools actually DID >>embarrass the in-house ones (say, achieve 10% better fmax 50% of the >>time), what do Xilinx do? >Offer us jobs (telecommuting jobs where we don't have to move to the Bay Area, >please ;-)? Maybe just a cash reward would suffice ;-) Well, who knows? ;-) Look at the record so far ... what happened to Neocad, whoever wrote PlanAhead, and now AccelChip. Even the late lamented XC6200 originally came from a Scottish startup, http://algotronix.com/people/tom/album.html and I honestly believe Xilinx tried to make it fly for a few years. >>And if they don't embarrass the in-house tools, where's the problem? > >I suppose you're right. It's just that in my experience corporations like >control (that's mainly why bitstreams are closed, right?).... what was it I >read recently (I think it was in Businessweek) something about >how most corporate organizations look a lot like the Soviet Politburo and that >while democracy has made huge inroads all over the world, it hasn't made much >progress in corporate America. Seemed apt. Well, IMO we can give them that control by not fighting them on Bitgen (the uninteresting "translation") AND get most of what we want (openness on the interesting bits, i.e. where you can win/lose performance) using XDL. - BrianArticle: 95320
John, I have some questions : In the user manual it's stated that there is two sites for platform flash. If we solder the second flash, is it usable ? how we can select between the first and the second ? Can we fit two xcf04 and a bigger fpga ? X.Article: 95321
On Fri, 20 Jan 2006 23:41:47 -0800, "Jeremy" <jeremy.lees@hotmail.com> wrote: >Greetings, >I've used the Altera/Quartus II tool set for a previous project, and my next >project will likely use the Xilinx/ISE toolset. In Quartus II there is the >ability to define I/O in the top module as virtual pins. This prevented >logic from being synthesized away and having the I/O assigned to a real pin >on the device. Does anybody now how to do this in the Xilinx/ISE tool set? There are options to allow or prohibit automatic allocation of pins; if you prohibit allocation, only the pins you allocate (usually via the .ucf = user constraints file) will be allocated. A "keep" attribute(*) on each non-pin signal should prevent it being optimised away. (*) I say attribute, assuming you are using VHDL. I don't know the Verilog equivalent, but there must be one. Searching for "keep attribute" and "ucf" or "pin constraints" should bring more info and examples. - BrianArticle: 95322
Chris Hills wrote: > In article <SeFAf.29814$SD1.13573@tornado.texas.rr.com>, Bryan Hackney > <no@body.home> writes > >>Ray Andraka wrote: >> >>>Joerg wrote: > > >>>5) Having a PE license doesn't give you carte blanche to go out and do >>>stuff outside of your area of expertise. In fact, the code of ethics >>>specifically states that you won't sign off on stuff that is not in your >>>area of expertise. > > >>>7) PE licensing is intended to protect the public by certifying that you >>>have demonstrated competency as an engineer in your field. You needn't >>>have the PE to do engineering work, but if the engineering services are >>>offered to the public, someone with a PE has to be accountable for the >>>work. >> >>The worst engineer I knew was an EE - PE. Never designed a damn thing. >>Knew how to dress, though. >> >>But then, he "was" an EE in a field where PE mattered - building systems, >>plant stuff, etc. Certainly not eletronic design. What can I add to what >>Paul Carpenter wrote? Certain companies needs PEs as window dressing, >>the same way some rich heiresses need poodles. > > > It is not window dressing. As Ray said you opperate in your area of > expertise. If his area was building systems and plant systems designing > the low level HW or Sw may not be his area. Know how to design a safe > system, the interlocks and legal/safety requirements etc. Therefor he > could design a system and give the requirements spec to some one else to > actually implement. > > On the other hand some EE PE's could design the HW but not the system or > the software. > > PE or C.Eng etc does not mean qualified to do it al but it means > qualified in certain areas and professional enough not to try and do > other stuff. SO a HW PE will not attempt any critical Sw I'm unaware of digital design and software being areas of expertise where a PE can be registered in Texas. Maybe that's changed, but I doubt it. So that point is probably moot. > > BTW Bryan could you design those systems and be sure the were safe and > up to al the legal requirements? > Maybe. I've never worked in those areas, but I'm more familiar with processes where designs and implementaions are verified, not those processes where the designer is certified and the product is not. Sometimes this makes sense. It's hard to non-destructively test a bridge's strength - it must be right the first time. A complicatated system is never right the first time.Article: 95323
SioL wrote: > Slovenia is the only country from the Ex-Yugoslavia inside EU at the moment > and as such the only one you can use in your comparisons, we were talking about EU. > The only war that took place here lasted 10 days, yet you can hardly call that a war. Easy for you to say since you weren't in it... > > Here is the full "War" story: http://www.uvi.si/10years/path/war/ Heheh- typical revision by a Slovenian military historian. The few pictures suggest that the terrain was absolutely *perfect* to stop any and all YPA tank and armored vehicle advances and kill the occupants, but I guess the TD was shy on explosives so barricades and indirect 82mm mortar fire had to be it. I am not all that familiar with the geography and situation there. Were the YPA already stationed in barracks throughout the country? The RS strategy does seem to have been a brilliantly conceived and executed design, that always helps to make the a war short and sweet.Article: 95324
"Fred Bloggs" <nospam@nospam.com> wrote in message > SioL wrote: >> Slovenia is the only country from the Ex-Yugoslavia inside EU at the moment >> and as such the only one you can use in your comparisons, we were talking about EU. >> The only war that took place here lasted 10 days, yet you can hardly call that a war. > > Easy for you to say since you weren't in it... I haven't been fighting, that much is true. 19 died on slovenian side. That many die in road accidents in a similar period of time. Traffic was mostly suspended during these 10-days. >> Here is the full "War" story: http://www.uvi.si/10years/path/war/ > Heheh- typical revision by a Slovenian military historian. The few pictures suggest that the terrain was absolutely *perfect* to > stop any and all YPA tank and armored vehicle advances and kill the occupants, but I guess the TD was shy on explosives so > barricades and indirect 82mm mortar fire had to be it. I am not all that familiar with the geography and situation there. Were the > YPA already stationed in barracks throughout the country? The RS strategy does seem to have been a brilliantly conceived and > executed design, that always helps to make the a war short and sweet. Ah, yeah, it was written by a military man, it sounds a bit overly dramatized. The reality was the YPA had no idea what to do. Most of YPA forces were scared young boys from obligatory 1-year service, from different parts of the country, including Slovenia. Most had no idea what the hell was going on and many fled the first chance they got. They were stationed in barracks around the country. We got out easy. SioL
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