Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hello, I have simple question - is there possibility of managing power consumed by FPGA design by turning off some parts of design ? Due to the fact that Z state is not synthazable ( I'm right ? ) I was planning that I will set Z state where I want to turn off for example not used registers but it don't work in real FPGA hardware I think... Clock gating is not really good idea for me - I heard that is not good solution Will I observe lower power consumption if I don't let DFFs to switching state ? Or it does not matter at all... Thank you very much for help Best regards, Mac --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144551
On Dec 14, 9:32=A0am, "de4" <d...@poczta.onet.pl> wrote: > Hello, > > I have simple question - is there possibility of managing power consumed = by > FPGA design by turning off some parts of design ? Due to the fact that Z > state is not synthazable ( I'm right ? ) Internal to a device 'Z' is generally not synthesizable because devices typically don't have internal tri-state buffers. I/O pins do have this so 'Z' is synthesizable there. The short answer is that 'Z' is synthesizable if the targetted part has tri-state drivers where your particular design intends to use them. > I was planning that I will set Z > state where I want to turn off for example not used registers but it don'= t > work in real FPGA hardware I think... > That wouldn't do much of anything. > Clock gating is not really good idea for me - I heard that is not good > solution > Depends on how you're gating. If your design is clocked by something coming out of a PLL/DLL, then gating the clock by holding the PLL/DLL in a reset state will shut off the clock and reduce the dynamic power to as low as you're likely going to get. The drawback is the startup time, whether that time is acceptable or not depends on your particular application. > Will I observe lower power consumption if I don't let DFFs to switching > state ? Yes...but the clock circuit itself can be a major power consumer so shutting that off will also take care of not switching > Or it does not matter at all... > Dynamic power is consumed when you need to change states on *any* signal, it takes power to switch a voltage from one level to another. To the extent that you can minimize this, you'll be minimizing your dynamic power consumption. This is just the general rule that would apply to basically any technology implementation. That's why shutting the clock off saves a significant chunk of power...the clock is *always* switching even if the receiver of the clock does not change its output as a result. Specific parts may also have other power minimization features to investigate as well. Kevin JenningsArticle: 144552
On 13 Dez., 22:18, "dlopez" <d...@designgame.ca> wrote: > I would have to disagree with you here. There are two modes of operation > for this chip: > a) Synchronous: One channel at ~25MB/s. > b) Asynchronous: Two channels of max ~10MB/s. Assuming that the 25MB/s limit is not from the FIFO but from the USB source as another poster hinted and the FIFO has 60MB/s bandwidth: c) 25MB/s when writing 16 bit words to the fifo where the first byte of the word indicates which stream it belongs to and the 2nd byte is the stream data. This is extremely simple to decode on the FPGA side, uses the simpler synchronous interfaces and allows up to 256 streams. Kolja SulimmaArticle: 144553
Thank you for expert answer. Now I have everything clear. It is great to have support from people who really knows the thing. You helped me a lot thank you. --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144554
On Dec 14, 7:41=A0am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > On 13 Dez., 22:18, "dlopez" <d...@designgame.ca> wrote: > > > I would have to disagree with you here. There are two modes of operatio= n > > for this chip: > > a) Synchronous: One channel at ~25MB/s. > > b) Asynchronous: Two channels of max ~10MB/s. > > Assuming that the 25MB/s limit is not from the FIFO but from the USB > source as another poster hinted and the FIFO has 60MB/s bandwidth: > c) 25MB/s when writing 16 bit words to the fifo where the first byte > of the word indicates which stream it belongs to and the 2nd byte is > the stream data. > This is extremely simple to decode on the FPGA side, uses the simpler > synchronous =A0interfaces and allows up to 256 streams. > > Kolja Sulimma One thing to consider for the performance is ... can the software stack really push/pull data from the USB at these rates. My company has achieved sustained 30MB/sec over USB using a Cypress FX2, but the s/w driver and application s/w was non-trivial. In addition, not all USB host chips are created equal. We saw quite a disparity in performance caused by the host USB controller. So, if the OP is really concerned about 20MB/sec throughput, I hope he checks that the s/w drivers won't be his bottleneck. John ProvidenzaArticle: 144555
On Dec 14, 2:32=A0pm, "de4" <d...@poczta.onet.pl> wrote:
> Clock gating is not really good idea for me - I heard that is not good
> solution
Clock gating in the crude sense of using random logic to turn clocks
on and off is not usually a good idea. But in many devices (certainly
in the latest Spartan and Virtex parts from Xilinx) the dedicated
clock buffers have clock-enable inputs, which allow the clocks to be
turned on and off cleanly. You can also dynamically program the clock
generator blocks, multiplex between a fast clock and a slower clock,
and so on, provided that you take due care. (Of course, something has
to be controlling all this, which probably requires at least *one*
clock to be active...)
Global clocks do typically consume a lot of power, and (as Kevin
already pointed out) they continue to do so even when the rest of the
logic is idle. So they are a good target for power optimization.
> Will I observe lower power consumption if I don't let DFFs to switching
> state ?
Yes, in general if you can prevent FFs from toggling, you will reduce
the power consumption of your design. But it is sometimes hard to
quantify the benefits of such optimizations without investing a fair
bit of effort. Tools such as the XPower Analyser can give you a
breakdown of how much power each element of a design is using... but
that assumes that you've already implemented it. See
http://www.xilinx.com/products/design_resources/power_central for
information on that, and other related solutions.
Cheers,
-Ben-
Article: 144556Hello. I am using a global buffer input as clock input, the signal then goes through a DCM, and I need to output the inverted clock through a pin into another chip. Can I use any pin for this clock output or are there specific pins that better serve this purpose? Thanks.Article: 144557
Ben Jones wrote:
> I agree that it's a Very Good Idea to have a reset, but I don't see
> why it has to be an asynchronous one. By default I try to make
> everything synchronous, including resets, unless there is a strong
> case to do otherwise. I have found that this leads to fewer problems
> throughout implementation.
This is certainly a matter of style, but I like to
reserve the asynch reset for simulating power up.
I describe all other initialization, sequentially.
Like Andy said, the reset pulse has to be synchronized
in any case.
-- Mike Treseler
Article: 144558a, Any pin will function. "Better" is a relative term: there are pins with less delay from the pad on the die to the pin on the package, would you call this better? If this is what you want (the shortest delay), you need to look at the delay from the pad to the pin in the package. This delay is commonly called "flight-time." AustinArticle: 144559
The VHDL code below was used to start up some
video interface chips that have a quite a few
control registers.
It's probably more code than you want to look at.
And it's VHDL. I'm not sure how Verilog supports
constructs like the enum but I believe you could
use another numbering system in Verilog and code
the ACK and STOP with separate if statements.
One thing that helped me set up my state machine
was to make the I2C clock always change on the
same clock phase edges. Then the START and STOP
conditions were set up by changing the data signal
on the other edges.
On the top level I used a Xilink IO tristate buffer
with the Input connected to ground, and the tristate
connected to the outgoing data. This allows the output
pin to be pulled up by an external resistor on your
board as specified by the I2C standard.
Good luck and tell us how it's going.
Brad Smallridge
AiVision
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity i2c8 is
port(
clk : in std_logic;
en : in std_logic;
reset : in std_logic;
sda_master : out std_logic;
scl_master : out std_logic;
sda_slave : in std_logic;
scl_slave : in std_logic;
ack_error : out std_logic;
hold_error : out std_logic );
end i2c8;
architecture Behavioral of i2c8 is
signal i2c_clk_phase0 : unsigned(1 downto 0);
signal i2c_clk_phase1 : unsigned(1 downto 0);
signal i2c_clk_phase2 : unsigned(1 downto 0);
signal i2c_bit_index0 : unsigned(2 downto 0);
signal i2c_bit_index1 : unsigned(2 downto 0);
signal i2c_bit_index2 : unsigned(2 downto 0);
type i2c_enum is (
h00,h01,h02,h03,h04,h05,h06,h07,h08,h09,h0A,h0B,h0C,h0D,h0E,h0F,
h10,h11,h12,h13,h14,h15,h16,h17,h18,h19,h1A,h1B,h1C,h1D,h1E,h1F,
h20,h21,h22,h23,h24,h25,h26,h27,h28,h29,h2A,h2B,h2C,h2D,h2E,h2F,
h30,h31,h32,h33,h34,h35,h36,h37,h38,h39,h3A,h3B,h3C,h3D,h3E,h3F,
h40,h41,h42,h43,h44,h45,h46,h47,h48,h49,h4A,h4B,h4C,h4D,h4E,h4F,
h50,h51,h52,h53,h54,h55,h56,h57,h58,h59,h5A,h5B,h5C,h5D,h5E,h5F,
h60,h61,h62,h63,h64,h65,h66,h67,h68,h69,h6A,h6B,h6C,h6D,h6E,h6F,
h70,h71,h72,h73,h74,h75,h76,h77,h78,h79,h7A,h7B,h7C,h7D,h7E,h7F,
h80,h81,h82,h83,h84,h85,h86,h87,h88,h89,h8A,h8B,h8C,h8D,h8E,h8F,
h90,h91,h92,h93,h94,h95,h96,h97,h98,h99,h9A,h9B,h9C,h9D,h9E,h9F,
hA0,hA1,hA2,hA3,hA4,hA5,hA6,hA7,hA8,hA9,hAA,hAB,hAC,hAD,hAE,hAF,
hB0,hB1,hB2,hB3,hB4,hB5,hB6,hB7,hB8,hB9,hBA,hBB,hBC,hBD,hBE,hBF,
hC0,hC1,hC2,hC3,hC4,hC5,hC6,hC7,hC8,hC9,hCA,hCB,hCC,hCD,hCE,hCF,
hD0,hD1,hD2,hD3,hD4,hD5,hD6,hD7,hD8,hD9,hDA,hDB,hDC,hDD,hDE,hDF,
hE0,hE1,hE2,hE3,hE4,hE5,hE6,hE7,hE8,hE9,hEA,hEB,hEC,hED,hEE,hEF,
hF0,hF1,hF2,hF3,hF4,hF5,hF6,hF7,hF8,hF9,hFA,hFB,hFC,hFD,hFE,hFF,
START,STOP,ACK,HALT,REPEAT ) ;
signal i2c_data1 : i2c_enum ;
signal i2c_data2 : i2c_enum ;
signal i2c_data_vector : unsigned( 8 downto 0) ;
type i2c_array_type is array(natural range <>) of i2c_enum;
constant i2c_data_array : i2c_array_type :=(
-- START,h88,ACK,h00,ACK,h00,ACK,STOP, -- Status 0 VER2-0 CCRDO CCRDE 0 FSEQ
O_E
-- START,h88,ACK,h00,ACK,h00,ACK,STOP, -- Null 01H to 25H
START,h88,ACK,h26,ACK,h00,ACK,STOP, -- Wide screen WSS7-0
START,h88,ACK,h27,ACK,h00,ACK,STOP, -- Wide screen WSSON 0 WSS13-8
START,h88,ACK,h28,ACK,h19,ACK,STOP, -- DECCOL DECFIS BS[5:0]=19H NTSC
START,h88,ACK,h29,ACK,h1D,ACK,STOP, -- 0 0 BE[5:0]=1DH
START,h88,ACK,h2A,ACK,h00,ACK,STOP, -- Copy generation CG07-0
START,h88,ACK,h2B,ACK,h00,ACK,STOP, -- CG15-08
START,h88,ACK,h2C,ACK,h00,ACK,STOP, -- CGEN 0 0 0 CG19-16
START,h88,ACK,h2D,ACK,hFF,ACK,STOP, -- CVBSEN1 CVBSEN0 CVBSTRI YTRI
-- CTRI RTRI GTRI BTRI
-- h2E to h37 -- Null
START,h88,ACK,h38,ACK,h1A,ACK,STOP, -- Gain luminance for RGB 0 0 0 GY4-0
START,h88,ACK,h39,ACK,h1A,ACK,STOP, -- Gain colour diff for RGB 0 0 0
GCD4-0
-- Turning this off created hsync and color issues, need SYMP
START,h88,ACK,h3A,ACK,h13,ACK,STOP, -- 0 CBENB Colour Bar Enable
-- 0
-- 0
-- SYMP Synchs from 656 Header
-- DEMOFF Dematrix OFF
-- CSYNC Advanced Composite Sync
-- MP2C MPEG straight binary (default
ON)
-- VP2C Fader is straight binary
(default ON)
START,h88,ACK,h42,ACK,h00,ACK,STOP, -- KEY1LU 7-0
START,h88,ACK,h43,ACK,h00,ACK,STOP, -- KEY1LV 7-0
START,h88,ACK,h44,ACK,h00,ACK,STOP, -- KEY1LY 7-0
START,h88,ACK,h45,ACK,h00,ACK,STOP, -- KEY2LU 7-0
START,h88,ACK,h46,ACK,h00,ACK,STOP, -- KEY2LV 7-0
START,h88,ACK,h47,ACK,h00,ACK,STOP, -- KEY2LY 7-0
START,h88,ACK,h48,ACK,h00,ACK,STOP, -- KEY1UU 7-0
START,h88,ACK,h49,ACK,h00,ACK,STOP, -- KEY1UV 7-0
START,h88,ACK,h4A,ACK,h00,ACK,STOP, -- KEY1UY 7-0
START,h88,ACK,h4B,ACK,h00,ACK,STOP, -- KEY2UU 7-0
START,h88,ACK,h4C,ACK,h00,ACK,STOP, -- KEY2UV 7-0
START,h88,ACK,h4D,ACK,h00,ACK,STOP, -- KEY2UY 7-0
START,h88,ACK,h4E,ACK,h00,ACK,STOP, -- 0 0 FADE1 5-0
START,h88,ACK,h4F,ACK,h00,ACK,STOP, -- CFADEM CFADEV FADE2 5-0
START,h88,ACK,h50,ACK,h00,ACK,STOP, -- 0 0 FADE3 5-0
START,h88,ACK,h51,ACK,h40,ACK,STOP, -- LUTU 7-0
START,h88,ACK,h52,ACK,h80,ACK,STOP, -- LUTV 7-0
START,h88,ACK,h53,ACK,hA0,ACK,STOP, -- LUTY 7-0
START,h88,ACK,h54,ACK,h0C,ACK,STOP, -- VPSEN 0 ENCIN RGBIN
-- DELIN VPSEL EDGE2 EDGE1
START,h88,ACK,h55,ACK,h00,ACK,STOP, -- VPS byte 5 VPS5 7-0
START,h88,ACK,h56,ACK,h00,ACK,STOP, -- VPS byte 11 VPS11 7-0
START,h88,ACK,h57,ACK,h00,ACK,STOP, -- VPS byte 12 VPS12 7-0
START,h88,ACK,h58,ACK,h00,ACK,STOP, -- VPS byte 13 VPS13 7-0
START,h88,ACK,h59,ACK,h00,ACK,STOP, -- VPS byte 14 VPS14 7-0
START,h88,ACK,h5A,ACK,h35,ACK,STOP, -- Chrominance phase
START,h88,ACK,h5B,ACK,h76,ACK,STOP, -- Gain U=076 with the 0 in 5D.7
START,h88,ACK,h5C,ACK,h65,ACK,STOP, -- Gain V=165 with the 1 in 5E.7
START,h88,ACK,h5D,ACK,h7A,ACK,STOP, -- GAINU8 DECOE BLCKL=3A
START,h88,ACK,h5E,ACK,hAE,ACK,STOP, -- GAINV8 DECPH BLNNL=3A
START,h88,ACK,h5F,ACK,h2E,ACK,STOP, -- CCRS1-0 BLNVB=3A
-- h60 -- Null
START,h88,ACK,h61,ACK,h15,ACK,STOP, -- DOWNB DOWNA INPI YGS
-- SECAM SCBW PAL FISE
-- 7 DOWNB 0 = DACs for R, G and B in normal operational mode
-- 1 = DACs for R, G and B forced to lowest output voltage;
-- default state after reset.
-- 6 DOWNA 0 = DACs for CVBS, Y and C in normal operational mode;
-- default state after reset.
-- 1 = DACs for CVBS, Y and C forced to lowest output voltage
-- 5 INPI 0 = PAL switch phase is nominal; default state after reset
-- 1 = PAL switch phase is inverted compared to nominal
-- if RTC is enabled; see Table 43
-- 4 YGS 0 = luminance gain for white - black 100 IRE;
-- default state after reset
-- 1 = luminance gain for white - black 92.5
-- IRE including 7.5 IRE set-up of black
-- 3 SECAM 0 = no SECAM encoding; default state after reset
-- 1 = SECAM encoding activated; bit PAL has to be set to logic 0
-- 2 SCBW 0 = enlarged bandwidth for chrominance encoding
-- 1 = standard bandwidth for chrominance encoding
-- default state after reset
-- 1 PAL 0 = NTSC encoding (non-alternating V component)
-- 1 = PAL encoding (alternating V component); default
-- 0 FISE 0 = 864 total pixel clocks per line; PAL default
-- 1 = 858 total pixel clocks per line NTSC
START,h88,ACK,h62,ACK,h3F,ACK,STOP, -- RTCE, BurST Amplitude=3FH
-- NTSC-M: fsc = 227.5, fllc = 1716 FSC = d569408543 h21F07C1F
START,h88,ACK,h63,ACK,h1F,ACK,STOP, -- Subcarrier 0 FSC 07-00
START,h88,ACK,h64,ACK,h7C,ACK,STOP, -- Subcarrier 1 FSC 15-08
START,h88,ACK,h65,ACK,hF0,ACK,STOP, -- Subcarrier 2 FSC 23-16
START,h88,ACK,h66,ACK,h21,ACK,STOP, -- Subcarrier 3 FSC 31-24
START,h88,ACK,h67,ACK,h00,ACK,STOP, -- Line 21 odd 0 L21O0 7-0
START,h88,ACK,h68,ACK,h00,ACK,STOP, -- Line 21 odd 1 L21O1 7-0
START,h88,ACK,h69,ACK,h00,ACK,STOP, -- Line 21 even 0 L21E0 7-0
START,h88,ACK,h6A,ACK,h00,ACK,STOP, -- Line 21 even 1 L21E1 7-0
START,h88,ACK,h6B,ACK,h00,ACK,STOP, -- SRCV11-10 TRCV2 ORCV1
-- PRCV1 CBLF ORCV2 PRCV2
START,h88,ACK,h6C,ACK,hF0,ACK,STOP, -- HTRIG7-0
START,h88,ACK,h6D,ACK,h00,ACK,STOP, -- HTRIG10-8 VTRIG4-0
START,h88,ACK,h6E,ACK,h80,ACK,STOP, -- SBLBN BLCKON PHRES1-0 LDEL1-0 FLC1-0
START,h88,ACK,h6F,ACK,h00,ACK,STOP, -- CCEN1 CCEN0 TTXEN SCCLN4-0
START,h88,ACK,h70,ACK,h00,ACK,STOP, -- RCV2 output start RCV2S7-0
START,h88,ACK,h71,ACK,h00,ACK,STOP, -- RCV2 output end RCV2E7-E0
START,h88,ACK,h72,ACK,h00,ACK,STOP, -- 0 RCV2E10-8 0 RCV2S10-8
START,h88,ACK,h73,ACK,h54,ACK,STOP, -- TTX request H start TTXHS 7-0
START,h88,ACK,h74,ACK,h02,ACK,STOP, -- TTX request H delay TTXHD 7-0
START,h88,ACK,h75,ACK,h83,ACK,STOP, -- CSYNCA4-0 VS_S2-0
START,h88,ACK,h76,ACK,h06,ACK,STOP, -- TTXOVS 7-0
START,h88,ACK,h77,ACK,h10,ACK,STOP, -- TTXOVE 7-0
START,h88,ACK,h78,ACK,h05,ACK,STOP, -- TTXEVS 7-0
START,h88,ACK,h79,ACK,h10,ACK,STOP, -- TTXEVE 7-0
START,h88,ACK,h7A,ACK,h25,ACK,STOP, -- First active line FAL 7-0
START,h88,ACK,h7B,ACK,hFE,ACK,STOP, -- Last active line LAL 7-0
START,h88,ACK,h7C,ACK,h00,ACK,STOP, -- TTX mode
-- MSB vertical
-- TTX60
-- LAL8
-- TTXO
-- FAL8
-- TTXEVE8 TTXOVE8 TTXEVS8 TTXOVS8
-- h7D -- Null
START,h88,ACK,h7E,ACK,h00,ACK,STOP, -- Disable TTX line LINE 12-5
START,h88,ACK,h7F,ACK,h00,ACK,STOP, -- Disable TTX line LINE 20-13
HALT );
subtype i2c_dat_index_type is natural;
signal i2c_dat_index0 : i2c_dat_index_type;
signal i2c_dat_index1 : i2c_dat_index_type;
begin
i2c_clock_phase_index_proc : process(clk)
begin
if( clk'event and clk='1') then
if( reset='1' ) then
i2c_clk_phase0 <= (others=>'0');
i2c_bit_index0 <= (others=>'0');
i2c_dat_index0 <= 0;
elsif(en='1') then
if( i2c_clk_phase0="11" ) then
i2c_clk_phase0 <= (others=>'0');
if( i2c_data1=HALT ) then
null;
elsif( i2c_data1=REPEAT ) then
i2c_clk_phase0 <= (others=>'0');
i2c_bit_index0 <= (others=>'0');
i2c_dat_index0 <= 0;
elsif( i2c_data1=START
or i2c_data1=STOP
or i2c_data1=ACK
or i2c_bit_index0="111" ) then
i2c_bit_index0 <= (others=>'0');
i2c_dat_index0 <= i2c_dat_index0 + 1 ;
else
i2c_bit_index0 <= i2c_bit_index0+1;
end if;
else
i2c_clk_phase0 <= i2c_clk_phase0+1;
end if;
i2c_clk_phase1 <= i2c_clk_phase0;
i2c_clk_phase2 <= i2c_clk_phase1;
i2c_bit_index1 <= i2c_bit_index0;
i2c_bit_index2 <= i2c_bit_index1;
i2c_dat_index1 <= i2c_dat_index0;
end if;
end if;
end process;
i2c_bram_proc : process(clk)
begin
if( clk'event and clk='1') then
if(en='1')then
-- i2c_data1 <= i2c_data_array(to_integer(i2c_dat_index0));
i2c_data1 <= i2c_data_array(i2c_dat_index0);
i2c_data2 <= i2c_data1;
end if;
end if;
end process;
i2c_vector_proc: process(i2c_data1)
begin
i2c_data_vector <= to_unsigned(i2c_enum'pos(i2c_data1),9);
end process;
i2c_proc:process(clk)
begin
if( clk'event and clk='1') then
if(reset='1') then
scl_master <= '1';
sda_master <= '1';
ack_error <= '0';
hold_error <= '0';
elsif(en='1') then
if( i2c_clk_phase1="00" ) then
scl_master <= '0';
elsif( i2c_clk_phase1="01" ) then
if( i2c_data1=STOP ) then
sda_master <= '0';
elsif( i2c_data1=ACK
or i2c_data1=START
or i2c_data1=HALT
or i2c_data1=REPEAT ) then
sda_master <= '1';
else
-- for all the h enumerated numerics
case i2c_bit_index1 is
when "000" => sda_master <= i2c_data_vector(7) ;
when "001" => sda_master <= i2c_data_vector(6) ;
when "010" => sda_master <= i2c_data_vector(5) ;
when "011" => sda_master <= i2c_data_vector(4) ;
when "100" => sda_master <= i2c_data_vector(3) ;
when "101" => sda_master <= i2c_data_vector(2) ;
when "110" => sda_master <= i2c_data_vector(1) ;
when "111" => sda_master <= i2c_data_vector(0) ;
when others => null ;
end case;
end if;
elsif( i2c_clk_phase1="10" ) then
scl_master <= '1';
-- Check for ACKnowledge from slave device
-- The slave device should pull the sda line low
if( i2c_data1=ACK and sda_slave='1') then
ack_error <= '1';
end if;
elsif( i2c_clk_phase1="11" ) then
if( i2c_data1=START ) then
sda_master <= '0';
elsif( i2c_data1=STOP ) then
sda_master <= '1';
end if;
if( scl_slave='0' ) then
hold_error <= '1';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
Article: 144560Thank you for a replay. It is solution for my problems and thank you again. Best regards, mac --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144561
>Assuming that the 25MB/s limit is not from the FIFO but from the USB >source as another poster hinted and the FIFO has 60MB/s bandwidth: >c) 25MB/s when writing 16 bit words to the fifo where the first byte >of the word indicates which stream it belongs to and the 2nd byte is >the stream data. >This is extremely simple to decode on the FPGA side, uses the simpler >synchronous interfaces and allows up to 256 streams. > >Kolja Sulimma > This was my first idea: use the Synchronous interface because it's simpler, and divide it in 2 streams, one for control, one for data. The data goes in a small FIFO and is getting read out at about 1-2MB/s. The FPGA is a 'slave' here. Now I only saw problems and corner cases with this approach. The PC, which is sending the data and commands, does not have easy visibility on the FPGA FIFO, so it doesn't really know the right mix of data/command to send. Then I though, just design some packets for 'worst case'...small command packets, followed by larger data packets. That might work, but the commands are subject to latency because of the data. Then what if the data sink just stops reading from the FPGA? Then one command, somewhere between my C# code and the FPGA, might get stuck in the pipeline since the FPGA won't grab more data from the USB chip. Then I though: ah this means I need a time-out in the FPGA...flush the buffer if you haven't received a command in x cycles...and probably some feedback about the FIFO status...then how quick will this feedback make it to the PC etc etc etc...sounds like a can of worms. I'm sure someone very clever can make it all work, but if I don't need the 25MB/s, it just seems like a better engineering decision to use the Async Fifo. I would just like to run it as fast as possible, so that of ALL the places where I can lose performance in such a system (PC, OS, Windows, Other USB device), my interface with the Async Fifo is not eating another 2MB/s for no good reason. I want to be able to read this data FAST, when it finally made it to the FTDI chip. Diego --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144562
>One thing to consider for the performance is ... can the software >stack really push/pull >data from the USB at these rates. My company has achieved sustained >30MB/sec over >USB using a Cypress FX2, but the s/w driver and application s/w was >non-trivial. In addition, >not all USB host chips are created equal. We saw quite a disparity in >performance caused >by the host USB controller. > >So, if the OP is really concerned about 20MB/sec throughput, I hope he >checks that the s/w >drivers won't be his bottleneck. > >John Providenza I have good news here. Using the plain D2XX driver that they give, I was able to stream at about 25MB/s out of the PC with no errors (!). To be fair, the PC was 'only' doing this, but it didn't seem to be that bad of a load. I got 5MB/s streaming out and 8MB/s streaming in using the Async interface. The 5MB/s output is what I'm trying to optimize - hence my original post! I just can't find a good way to do this, although Kevin Jennings gave some pretty good clues a few posts above but I haven't had time to try it yet. Thanks! Diego --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144563
On Dec 13, 3:20=A0pm, laserbeak43 <laserbea...@gmail.com> wrote:
> I can't even get this simple code to work in the inserter
>
> module two_input_xor (
> =A0 =A0 =A0 =A0 input wire in1,
> =A0 =A0 =A0 =A0 input wire in2,
> =A0 =A0 =A0 =A0 output wire out
> =A0 =A0 =A0 =A0 );
> =A0 =A0 =A0 =A0 assign out =3D in1 ^ in2;
> endmodule
>
> On Dec 9, 6:48=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
>
>
>
> > Andy Peters <goo...@latke.net> writes:
> > > On Dec 7, 6:26=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrot=
e:
> > >> laserbeak43 <laserbea...@gmail.com> writes:
> > >> > Hello,
> > >> > =A0 =A0 I've just been shown Signaltap, A feature in Quartus Webpa=
ck
> > >> > Edition. Does the Webpack Edition of ISE have this feature? WOW th=
is
> > >> > alone can convince me to use Altera products.
>
> > >> Chipscope is the Xilinx equivalent - it's not in webpack (personally=
, I
> > >> think that's a mistake on Xilinx's part)
>
> > >> But comparing it to Signaltap may (IMHO) leave you underwhelmed... i=
t's
> > >> very disjointed and unintegrated in comparison. =A0I'm still using F=
PGA
> > >> editor to change which signals to monitor, then having to update the
> > >> viewer by hand! V. tedious.
>
> > > Really? What version of ChipScope are you using?
>
> > 10.1.3
>
> > > Use the ChipScope Core Inserter.
>
> > Indeed, I could (and have in the past), but
>
> > a) I'm using the EDK variety of core inserter, as it manages the JTAG
> > linkages with the microblaze debug module for me
>
> > b) I then have to run MAP, PAR, bitgen again.
>
> > > All of the signals and elements of
> > > the design are shown in it, and you simply choose the signals to
> > > monitor. After you close the Inserter, go back to ISE, and re-fit.
>
> > Re-fit - 10s of minutes.
>
> > > From the ChipScope viewer, you can reconfigure the FPGA, then do an
> > > "Import" which lets you bring in the names of all of the signals you
> > > selected from the ChipScope Core Inserter project file.
>
> > > No need to go into the FPGA editor at all!
>
> > FPGAeditor, regenerate bitstream, 10s of seconds... =A0Then click "writ=
e
> > CDC" button, import the result into the analyser. =A0Still tedious :)
>
> > As I recall my experience with SignalTap (which was a while ago
> > admittedly) I could select a signal from a dropdown list *in the
> > Analyser* and it would do the tedious hacking that I currently do in
> > FPGAed, regen the bitstream and upload it for me.
>
> > Under some circumstances, it would redo a fit at that point, which was
> > irritating, but at least I was able to do it all from the analyzer GUI,
> > which was then always in sync with the FPGA.
>
> > [Followups set to comp.arch.fpga, as it's not very Veriloggy]
>
> > Cheers,
> > Martin
>
> > Crosspost & Followup-To: comp.arch.fpga
> > --
> > martin.j.thomp...@trw.com
> > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp:/=
/www.conekt.net/electronics.html- Hide quoted text -
>
> - Show quoted text -
You didn't say what failed, but let me guess what they were.
1) Your simple code above doesn't have a clock so either nothing was
captured or it failed to insert because you didn't define a clock.
2) You tried to use the nets in1, in2 and out as the TRIGGER and DATA
sources and this failed. These net names become the PADs in the
design and can not be probed. You need to use the net attached to the
IBUF output for "in1" and "in2" and the net attached to the OBUF input
for "out".
This code would be a better simple design, using clock, in1_reg,
in2_reg and xor_reg.
odule two_input_xor (
input wire in1,
input wire in2,
input wire clock,
output reg out
);
reg in1_reg, in2_reg, xor_reg;
// Input Registers
always @ (posedge clock) begin
in1_reg <=3D in1;
in2_reg <=3D in2;
end
// Internal Registers
always @ (posedge clock) begin
xor_reg <=3D in1_reg ^ in2_reg;
end
// Output Registers
always @ (posedge clock) begin
out <=3D xor_reg;
end
endmodule
Article: 144564Hello, all! I'm interested in exploring digital design with FPGAs for both learning purposes and to help with a senior design project I'll be working on. To start, I spent my entire 1st day of winter break (yay!) looking at different starter boards, and I'm pretty much lost. I was wondering if someone could explain the practical differences between the various FPGA boards currently on Digilent's website: http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,400&Cat=10 It would be awesome if someone could give me a recommendation on what board would be best for me based on the info in this post. I'm typically looking for something ≤$200, but I'm willing to pay $300 for the XUP Virtex-II Pro (if necessary), since it seems like a killer deal for students. I guess a lot of this depends on what type of applications you will use the boards for, so I guess I'll explain a bit about my project: This past fall semester of school, I took an image processing course and also my first DSP course. I want to start my senior design project early (due May 2011) so I came up with an idea that would emphasize what I learned in those two courses. Anyway, my project's goal is to tap the 18-bit RGB lines on a Nintendo DS and produce a 640x480p/i YPbPr/Analog-RGB video output. Though that would probably be something complicated on its own, my main focus would be various selectable screen output modes. For example: Mode A) Top Screen only, 256 x 192 centered with black borders all around Mode B) Bottom Screen only, 256 x 192 centered with black borders all around Mode C) Top Screen only, 256 x 192 resized (bilinear interpolation) to 640 x 480 Mode D) Top screen directly above Bottom screen, no gap between screens Mode E) Top screen above Bottom screen, 64-line gap filled with interpolated data from both screens and/or motion predicted pixels ..and quite a few more modes. I found a thread on here where someone was trying to accomplish something very similar: http://www.fpgarelated.com/usenet/fpga/show/77345-1.php The recommended board for that type of project is the Spartan-3. But my project will probably require more/better "stuff" to be able to implement the various video processing functions, right? Plus, that's an old thread and there are a lot of newer boards out there now, so I don't know what to think. I'm totally lost. Oh, and here's some more specific info on what I plan to do: I would like to be taking FFTs to help with the video scaling, so I would prefer something capable of that. But, I can avoid the frequency domain altogether if the price difference for that capability is too large. Also, I would probably need to buffer more than one frame of video for the gap interpolation, and I'm assuming the Spartan-3's 1MB of RAM won't cut it. Though, it seems that people like the RAM on the Spartan-3 because it is SRAM. To anyone who actually read the mess of words I posted above, I thank you. Feel free to respond and help out in any way. I'll take any info that can be given to me and as always, it would be greatly appreciated. -Stephan --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144565
Hi .. 'm having ADC chip "ADS 8364" wit 25m Hz input Clock . ADC output Signal Going to FPGA and its out signal going to processor fr further process. my problem is before writing vhdl Code i want generate timings ADC to FPGA but (1) i don no what is this timing generation ? (2) why this necessary before Code ? (3)Can any one give example timing code generation for ADC's Waiting for all yur Inputs JoshiArticle: 144566
On Dec 14, 11:40=A0am, "ines_fr" <benhlima_i...@yahoo.fr> wrote: > hello, > > I am using spartan 3 starter board (with MB7.1) to work with 2 processors > cores using EDK10.1 (my reference is the Xilinx tutorial XAPP996). I want > to add, between the two processors, a shared memory BRAM_block_v1_00_a wi= th > the controler xps_bram_if_cntlr_v1_00_a. > > the problem is: when I want to share the bus of the bram controller =A0SP= LB, > changing the parameter C_SPLB_P2P to 0, nothing happens and the SPLB bus > does not connect the two buses mb_plb_0 and mb_plb_1 respectively of the > fist CPu and the the second. > if someone has an idea please help me because I'm stuck. :( > Thanks in advance > > INES =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com Hi, Not really clear on what you trying to do. One xps_bram_if_cntlr_v1_00_a connects to one PLB. So if the two MB is sharing that PLB bus, don't change anything and just connect the shared PLB bus to the PLB interface on the xps_bram_if_cntlr_v1_00_a. Then just connect the BRAM port on the xps_bram_if_cntlr_v1_00_a to one of the BRAM ports on the BRAM_block_v1_00_a If you don't want the two MB to share the PLB bus, you will need two xps_bram_if_cntlr_v1_00_a where each one is connected to it respectively MB PLB bus. You then connect the BRAM port on the xps_bram_if_cntlr_v1_00_a to the BRAM ports on the BRAM_block_v1_00_a, this will create a shared memory between two seperate PLB busses. G=F6ran BilskiArticle: 144567
On Dec 15, 1:24=A0am, "Joshi & Joshi" <joship...@gmail.com> wrote: > Hi .. > > 'm having ADC chip "ADS 8364" =A0wit 25m Hz input Clock . ADC output > Signal Going to FPGA and its out signal going to processor fr further > process. > > my problem is before writing vhdl Code i want generate timings ADC to > FPGA but > > (1) i don no what is this timing generation ? > A timing diagram. Refer to the data sheet for the part. > (2) why this necessary before Code ? > It isn't. > (3)Can any one give example timing code generation for ADC's > http://focus.ti.com/lit/ds/symlink/ads8364.pdf (Page 26) KJArticle: 144568
On Dec 15, 7:09=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > > http://focus.ti.com/lit/ds/symlink/ads8364.pdf(Page 26) > Make that page 6, not 26 KJArticle: 144569
Hi 'm having ADC chip "ADS 8364" wit 25m Hz input Clock . ADC output Signal Going to FPGA and its out signal going to processor fr further process. my problem is before writing vhdl Code i want generate timings ADC to FPGA but (1) i don no what is this timing generation ? (2) why this necessary before Code ? (3)Can any one give example timing code generation for ADC's Waiting for all yur Inputs JoshiArticle: 144570
>On Dec 15, 7:09=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > >> >> http://focus.ti.com/lit/ds/symlink/ads8364.pdf(Page 26) >> >Make that page 6, not 26 > >KJ > thanks fr Input ya i had this Data sheet .. But i want Know how to make use use of Giving timing diagrams in VHDL Code .. Can any one Give Give Xmple Code fr Timing Generating Code .. for what purpose we want generate this Code? Joshi --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144571
On 4 dic, 15:15, "kendor" <jonas.re...@bfh.ch> wrote: > hello there > > for a measuring utility (running @ 100MHZ) I need a counter of 42-bit wid= th > whose value is used by several sub blocks of my design. As a first, someh= ow > dirty solution I have implemented this like follows. Since this approach > needs quite a huge amount of FFs and leads to long delaytimes (bit 0 to 4= 2) > I am looking for an alternative. I was thinking about usingBlockRAM > (Spartan3) to reduce routing effort and delaytimes. (see alsohttp://cours= es.ece.illinois.edu/ece412/References/datasheets/xapp463.pdf) > > Has anyone ever done such a thing or do you have any suggestions on solvi= ng > my task? > > current code: > ------------------------------------- > # i have to use std_logic_unsigned since numeric_std has as integer width > the normal 4 bytes width (32bit - which for 42 bits is not enough ... > overflow,..) > > # ... > GENERIC ( > =A0 t : NATURAL :=3D 42; =A0--! counter width > =A0 wd: NATURAL :=3D 5 =A0 =A0--! divider (clk/(2*wd)) > ); > > # ... > ARCHITECTURE rtl OF worldtimeCtr IS > =A0 =A0 =A0 =A0 SIGNAL cnt: std_logic_vector(t-1 downto 0); > BEGIN > =A0 =A0 =A0 =A0 PROCESS(clk,rst) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 VARIABLE temp : NATURAL RANGE 0 to wd; > =A0 =A0 =A0 =A0 BEGIN > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 IF(rst=3D'0')THEN > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt <=3D (others =3D>'0')= ; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 temp :=3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF(clk'event and clk=3D'1')THEN > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 IF(en=3D'1' and temp =3D = wd)THEN > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0temp :=3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cnt <=3D STD_LOGIC= _VECTOR(cnt + 1); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 END IF; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 temp :=3D temp+1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 END if; > > =A0 =A0 =A0 =A0 END process; > =A0 =A0 =A0 =A0 o_worldtime <=3D cnt; > END rtl; > > # ... > ------------------------------------- > > thank you in advance > > kendor Cant you use a DCM to generate a sub-clock?Article: 144572
Stephan, The V2Pro board is not supported in the latest ISE release, version 11, so you would be "stuck" using the last ISE version (10), forever. Which is not bad, per se, it is just that we can't continue supporting these old parts forever, so something has to get dropped in the software as we move forward. There are a lot of these V2P boards out there, so there is quite a community of users, and existing designs. It also does not need a programming cable (uses the on card USB and Digilent software). The latest and greatest Spartan part, is now Spartan 6, and Digilent does not have an S6 board (yet), but the Spartan 3A (and older 3E) series, and 3AD (for DSP) are still fully supported by Xilinx (no versions of these boards either at Digilent) and development boards from other suppliers would have more features and be more useful for what you want to do. The difference with Spartan from Virtex, is Virtex has larger parts, more of everything, and run faster. The 3A D series has more DSP blocks, so you can make more filters than in the same fabric size 3A part, for example. http://www.xilinx.com/products/boards_kits/spartan.htm The XUP (Xilinx University Program) offers the Virtex 5 board for students (through their professors), and it has plenty of SRAM, DDR DRAM, etc. plus video interfaces for monitors. It has a very large part, the xc5vlx110t (includes transceivers). I do most of my work on such a board, and I haven't run out of room yet. One has to obtain this board, and the software to support it through the XUP. Digilent also sells this board directly (but if not part of the XUP, you have to buy a version of the software, too, as this board's part, the xc5vlx110t is not in the "free" version of the tools). Sorry for the confusion.... Back to Digilent, Inc: the lowest cost board that probably can do what you desire is the Nexsys2 Spartan 3E board. One advantage is that all you need is the USB cable from board to pc to program it, as opposed to the other solutions which require the Xilinx Programming Programming Cable (more expensive as it has a pod on the end of it for JTAG, and the other programming modes of the part). Next, I would choose the 3A DSP 1800 kit from the xilinx.com website. But a hidden cost is that you need the Xilinx programming cable for this, as opposed to the built in programming solution from Digilent. The next choice is the V5 XUP board (in my opinion). Also need a Xilinx programming cable for this (like the 3A DSP above). AustinArticle: 144573
On Mon, 14 Dec 2009 22:24:40 -0800 (PST) "Joshi & Joshi" <joshiplns@gmail.com> wrote: > Hi .. > > 'm having ADC chip "ADS 8364" wit 25m Hz input Clock . ADC output > Signal Going to FPGA and its out signal going to processor fr further > process. > > my problem is before writing vhdl Code i want generate timings ADC to > FPGA but > > (1) i don no what is this timing generation ? > > (2) why this necessary before Code ? > > (3)Can any one give example timing code generation for ADC's > > Waiting for all yur Inputs > > Joshi > > You generate timed sequences of events by writing a finite state machine clocked by a system clock of known frequency. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 144574
The V2pro board from Digilent is good value but do take note of the software issues Austin talks about. For what you are describing I'd suggest a board with either SDRAM/DDR and/or a FPGA that has lots of blockrams. The Spartan-3A DSP does fit the bill well but there are not many cheap boards with these chips on. From our products I would suggest Darnaw1, Drigmorn2, Drigmorn3 for the lower end of what you need. A better fit may be the next board we launch next month which is Raggedstone2. It has DDR3 and because it has Spartan-6 XC6SLX45T a reasonable blockram count. This board with student discount will be at the top of your range but will have a USB Cable to ship with it. John Adair Enterpoint Ltd. On 15 Dec, 03:56, "Ste" <lords...@hotmail.com> wrote: > Hello, all! > > I'm interested in exploring digital design with FPGAs for both learning > purposes and to help with a senior design project I'll be working on. =C2= =A0To > start, I spent my entire 1st day of winter break (yay!) looking at > different starter boards, and I'm pretty much lost. =C2=A0I was wondering= if > someone could explain the practical differences between the various FPGA > boards currently on Digilent's website:http://www.digilentinc.com/Product= s/Catalog.cfm?NavPath=3D2,400&Cat=3D10 > It would be awesome if someone could give me a recommendation on what boa= rd > would be best for me based on the info in this post. I'm typically lookin= g > for something =E2=89=A4$200, but I'm willing to pay $300 for the XUP Virt= ex-II > Pro (if necessary), since it seems like a killer deal for students. > > I guess a lot of this depends on what type of applications you will use t= he > boards for, so I guess I'll explain a bit about my project: > This past fall semester of school, I took an image processing course and > also my first DSP course. =C2=A0I want to start my senior design project = early > (due May 2011) so I came up with an idea that would emphasize what I > learned in those two courses. =C2=A0Anyway, my project's goal is to tap t= he > 18-bit RGB lines on a Nintendo DS and produce a 640x480p/i YPbPr/Analog-R= GB > video output. =C2=A0Though that would probably be something complicated o= n its > own, my main focus would be various selectable screen output modes. =C2= =A0For > example: > Mode A) Top Screen only, 256 x 192 centered with black borders all around > Mode B) Bottom Screen only, 256 x 192 centered with black borders all > around > Mode C) Top Screen only, 256 x 192 resized (bilinear interpolation) to 64= 0 > x 480 > Mode D) Top screen directly above Bottom screen, no gap between screens > Mode E) Top screen above Bottom screen, 64-line gap filled with > interpolated data from both screens and/or motion predicted pixels > > ..and quite a few more modes. > > I found a thread on here where someone was trying to accomplish something > very similar:http://www.fpgarelated.com/usenet/fpga/show/77345-1.php > The recommended board for that type of project is the Spartan-3. =C2=A0Bu= t my > project will probably require more/better "stuff" to be able to implement > the various video processing functions, right? =C2=A0Plus, that's an old = thread > and there are a lot of newer boards out there now, so I don't know what t= o > think. =C2=A0I'm totally lost. > > Oh, and here's some more specific info on what I plan to do: > I would like to be taking FFTs to help with the video scaling, so I would > prefer something capable of that. =C2=A0But, I can avoid the frequency do= main > altogether if the price difference for that capability is too large. =C2= =A0Also, > I would probably need to buffer more than one frame of video for the gap > interpolation, and I'm assuming the Spartan-3's 1MB of RAM won't cut it. > Though, it seems that people like the RAM on the Spartan-3 because it is > SRAM. > > To anyone who actually read the mess of words I posted above, I thank you= . > Feel free to respond and help out in any way. =C2=A0I'll take any info th= at can > be given to me and as always, it would be greatly appreciated. > > -Stephan > > --------------------------------------- =C2=A0 =C2=A0 =C2=A0 =C2=A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z