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Messages from 105100

Article: 105100
Subject: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
From: nospam <nospam@please.invalid>
Date: Thu, 13 Jul 2006 20:06:16 +0100
Links: << >>  << T >>  << A >>
"Brannon" <brannonking@yahoo.com> wrote:

>> How many I/O pins does that take?
>
>I'm not sure that question makes a whole lot of sense. 

When you claim your FPGA solution will process 4096 bits of data per clock
cycle questioning how your solution gets 4096 bits of data per clock cycle
in and out of the FPGA makes a lot of sense. 

-- 

Article: 105101
Subject: EDK - Debugging software applications located in ISOCM
From: "MM" <mbmsv@yahoo.com>
Date: Thu, 13 Jul 2006 15:46:19 -0400
Links: << >>  << T >>  << A >>
According to Xilinx AR #22942 ISOCM should be readable from XMD in V4.
However, this doesn't seem to be the case... Has anyone succeeded in
debugging any code located in ISOCM?

Thanks,
/Mikhail



Article: 105102
Subject: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
From: Joseph Samson <user@example.net>
Date: Thu, 13 Jul 2006 20:03:48 GMT
Links: << >>  << T >>  << A >>
Eli Hughes wrote:
> 
> I don't like the limited availability (and the big warning message 
>  to not use verilog) of verilog examples.  It seems that they might 
> dump verilog support....
> 
> -Eli

They just added verilog support in 7.1i, so I doubt that the would drop 
it now. It would be nice to have verilog examples. I've generated VHDL 
versions just to see the example code.

---
Joe Samson

Article: 105103
Subject: Re: Micorblaze post place and route simulation...
From: "Xesium" <amirhossein.gholamipour@gmail.com>
Date: 13 Jul 2006 14:25:01 -0700
Links: << >>  << T >>  << A >>
hmm,
Thanks for the information but after all do you have any idea why this
happens? Am I on the right way of verification at all? Because I want
to measure the power but I have to make sure that the generated vcd
file has correct information.

mk wrote:
> On 13 Jul 2006 03:18:17 -0700, antti.tyrvainen@luukku.com wrote:
>
> >
> >mk kirjoitti:
> >
> >> >
> >> >By the way, why do you perform post P&R simulation for power analysis?
> >> >Isn't functional simulation activity output enough?
> >> >Do you know if post P&R simulation really gives a benefit over
> >> >functional simulation for power analysis?
> >> >
> >> >Antti
> >>
> >> With current FPGAs where routing delay can be more than half of the
> >> total delay, p&r results can be quite important in power. How long a
> >> route is and how many buffers it goes through certainly impacts the
> >> power consumption.
> >
> >Yes, but does the power tool really need post P&R simulation .vcd for
> >that?
> >Isn't P&R netlist enough?
> >
> >Can't you use functional .vcd together with post P&R netlist?
> >
> >Antti
>
> I am not sure what you mean by functional simulation here. If you mean
> rtl simulation, the answer is no; the nets and the gates (including
> replicated flops etc) have to match to get an accurate number. If you
> mean p&r netlist without the associated SDF back-annotation, that
> would be ok, you don't need timing annotated simulations. VCD gets the
> changes in the design so you have to simulate what ever is happening
> in the chip, not necessarily with timing.


Article: 105104
Subject: Re: Development Boards -Your chance to suggest features
From: "Brannon" <brannonking@yahoo.com>
Date: 13 Jul 2006 15:25:30 -0700
Links: << >>  << T >>  << A >>
I would like a board designed from the ground up to do general software
acceleration for consumers. That means a fast interface between the
FPGA and the host computer. It will have to be an external PCIe and DMA
controller with sufficient PCIe channels (like 4 or 8) and DMA channels
(like 4 or 8) that I can stream data in and out with. The board would
have standard ports for connections to other boards of the same type,
DDR2 memory, and SRAM (all unpopulated on the low-end sales). It could
have one or several FPGAs on it. It would be even better if it could be
populated with a range of cheap FPGAs to expensive ones.

John Adair wrote:
> Following our recent Swinyard1 (Virtex-4) release we are now looking at the
> Swinyard2 module concept which will be based on a middle end Virtex-5
> (initial XC5VLX50 and others) that will be supported by our Broaddown series
> of main development boards. Bearing in mind this a small module what
> features would you like us to put on this module?


Article: 105105
Subject: Re: Spartan 3E starter kit DDR SDRAM code
From: "Scott Schlachter" <scott.schlachter@xilinx.com>
Date: Thu, 13 Jul 2006 15:41:56 -0700
Links: << >>  << T >>  << A >>
Hi Frank, and others interested,

Don't worry about the speedgrade part of the device selection - the width
and depth are important though, so for rev D board, you'd normally want to
select the MT46V32M16P (either -5 or -75 like you did).  MIG 1.5 won't allow
you to select putting all of the data, address and control pins into any
single bank (like bank 3).  The .ucf file required to use the board's pinout
had to be very carefully crafted, and there were a few slight mods required
in the HDL for the single-ended system clock (we use the SMA connector), and
the high-going reset (we use the Button WEST pushbutton which is active high
and requires an internal pull-down).  There was also some special design
tweaks that we had to do for the loop-back signal, which isn't present on
this board like how the MIG core typically requires it.

We're getting ready to include a set of pre-canned S3E Starter Kit board
files for a Verilog version of the core in the next release of the MIG tool.
I don't have a release date for it though.   In the MIG 1.5 tool's main
window, after selecting a Spartan-3E part, you'll see a button towards the
lower right that reads "No Board Files".  In the next MIG version, that will
say something like "Spartan-3E Starter Kit files", and when you press it, it
will create a zip file.   If you are interested, and can handle 5MB sized
attachments, I can send you a beta-copy of this Verilog design.  Although I
can not support you with it, I'm happy to provide it to folks who are
interested.   Send me an email direct to scott.schlachter@xilinx.com .
We're working on a VHDL version, but it's still in progress, and I can't
provide an ETA yet at this time.

-Scott Schlachter
Xilinx


"Frank Buss" <fb@frank-buss.de> wrote in message
news:y0zsbkmbzp7g$.1rp86jojhcwji$.dlg@40tude.net...
> Frank Buss wrote:
>
> > Has anyone VHDL code for accessing the DDR SDRAM on this Spartan 3E
starter
> > kit?
>
> I've tried the Xilinx CORE Generator with MiG 1.5 but when I try to click
> on "Generate" for the MT46V32M16P-75 (I can't select the part
> "MT46V32M16-6T F", which is soldered on my board, so I selected the
slowest
> part I found), the log says multiple times:
>
> | Verifying proximity rules for local clock distribution...
> | Rule violated...trying different locations due to rule violation...
>
> and later:
>
> | Could not find the pins for all the data(2.5V) and data strobe(2.5V) .
> | Pin allocation  ...failed.
>
> And on the button where I can click for boards for other Xlinx FPGAs,
there
> is the text "No board files".
>
> The CORE Generator looks nice, but I would be happy with just one working
> CORE or VHDL code for the DDR SDRAM on the Spartan 3E starter kit.
>
> -- 
> Frank Buss, fb@frank-buss.de
> http://www.frank-buss.de, http://www.it4-systems.de



Article: 105106
Subject: Re: Universal Scan with Xilinx's ML403
From: George.Y.Ma@gmail.com
Date: 13 Jul 2006 15:53:44 -0700
Links: << >>  << T >>  << A >>
I am thinking about using the JTAG port on the CPLD (XC9500XL) to
program the flash. I am not very familiar with boundary scan
applications. Where can I find more info on it?
Thanks

Antti wrote:
> George.Y.Ma@gmail.com schrieb:
>
> > Hi,
> >
> > Does anyone have experience using Universal Scan to program the flash
> > on Xilinx's ML403?
> > Universal Scan should use the JTAG port on the FPGA (Virtex4) to
> > program the flash. I'm having difficulties to get it to work. Any
> > suggestions?
> >
> > Thanks
> I tried universalscan with S3e sample pack board. never got it working.
>
> writing a custom application that does the nor flash programming
> (either over boundary scan or using BSCAN primitive) was way easier.
> 
> Antti


Article: 105107
Subject: issue on on using Xilinx PROMS in conjugation with System ACE;
From: "rao" <raonpc@gmail.com>
Date: 13 Jul 2006 17:13:09 -0700
Links: << >>  << T >>  << A >>
Hello,

I am currently working on a board design based on Virtex-4 FPGAs.
For configuration I am planning to use 4 XCF32P(parallel platform
flash) and
a system ACE chip so that I can have two options to program.

I have 2 virtex-4 fpga's (LX200), 4 platform flash and system ace
controller in jtag chain.

The JTAG chain is as follows:
PC4 CONN -> System ACE -> PROM3 -> PROM2 -> PROM1 -> PROM0 -> FPGA1 ->
FPGA2 -> PC4 CONN(back)

I am planning to use either jtag, master serial(proms) or system ace
modes of configuration.

The fpga Mode setting bits for configuration:
M2 M1 M0
1  0  1 - Jtag
0  0  0 - Master serial
1  1  1 - System ACE ?

In addition to this settings I need a extra switch to select
between platform proms and system ACE (as described in ML401
Board documentation and schematic) configuration modes.

This switch is two way in sense that it disables
system ace and enables platform proms and
in other action disables platform proms and enables
system ace.

--- use system ace and disable proms ---
Normally for cascade configuration of PROMS, the fpga_done
pin from fpga goes to 1st prom0 ce_bar, the ceo of prom0 goes
to ce_bar of prom1, the ceo of prom1 goes to ce_bar of prom2,
the ceo of prom2 goes to ce_bar of prom3 and the ceo of prom3
is left unconnected.

So if I want to disable these prom chain(when using system ace),
then I need to disconnect fpga_done from ce_bar of prom0 and connect to
VCC ?

Do I need to connect all ce_bar (PROM0, PROM1, PROM2, PROM3) to VCC  or
for PROM0 will do ?

--- use proms and disable system ace ---
connect CFGMODEPIN of system ACE to gnd ?

I appreciate if any one can respond.

Regards
Nannapaneni


Article: 105108
Subject: Cyclone II Power Measurement on DE2 Board
From: syzygy01@gmail.com
Date: 13 Jul 2006 17:25:31 -0700
Links: << >>  << T >>  << A >>
I have a DE2 board with Cyclone II FPGA EP2C35F672C6. I want to measure
the power consumed by my design in the FGPA device. For that I have to
measure the current drawn off the power supply VCCIO. Since everything
is hardwired on the board, I cannot connect an ammeter in series to
measure current. I tried measuring the current drawn off the board
power supply, which is at 9V. But this is not the true power of my
design in FPGA. That power also includes the power consumed by other
components on the board.
Is there a way I can measure the power of the FPGA that is in DE2
board?


Article: 105109
Subject: Re: Any *really old* Viewlogic / Xilinx users around here? :)
From: joseph2k <cooltechblue@yahoo.com>
Date: Fri, 14 Jul 2006 01:52:04 GMT
Links: << >>  << T >>  << A >>
Peter wrote:

> In the 1990s I used a Xilinx-only version of DOS Viewlogic, version 4
> I think.
> 
> Viewlogic was hacked so that schematic files created in the
> unrestricted version could not be opened in the restricted version(s).
> 
> However, somebody developed a program called sneaky.exe which patched
> the schematic file, to enable it to be opened.
> 
> I have been chucking out a large quantity of 5.25" disks with all
> sorts of stuff on them, and came across this. It is on a 360k disk
> which I can't read anymore (I can read 1.2MB ones) so if anybody wants
> this drop me an email with your mailing address. I recall it is a very
> small file, a few k.
> 
<snip>
> email petexrh337@yahooxz.co.uk but remove the two "x" chars and the
> one "z" char

I am pretty sure that my 5.25 can still read it.  Would you like the file
back (?) on a 5.25 (1.2 MB), 3.5 (720KB or 1.44MB), or CDR?

-- 
JosephKK
Gegen dummheit kampfen die Gotter Selbst, vergebens.  
--Schiller

Article: 105110
Subject: Separate enable on address for ram blocks
From: "rickman" <spamgoeshere4@yahoo.com>
Date: 13 Jul 2006 19:53:34 -0700
Links: << >>  << T >>  << A >>
I am reworking a design I did a couple of years ago to fit a newer
part.  The original design made use of async ram blocks since they fit
the application better.  Now I am forced to use registered synchronous
block rams.  This will create an extra clock delay on reads if I don't
think of a way around it.  But the clever guy I am, I have come up with
a couple of alternatives.

The source of the address is a register that will often be updated just
before the cycle that needs to do the memory access.  Call the old
memory access cycle 1 and the cycle that calculates the address cycle
0.  The write enable is not valid until this clock cycle 1, but during
the clock cycle 0, the address is on the input to the address register,
call it "next address".  If I run "next address" to the address inputs
on the memory, I can start the memory read on clock cycle 0 and the
timing works out.  I can't do the same trick with the read or write
enable since they depend on decoding that will not take place until
cycle 1 where the memory access was happening.  Since the enable signal
is not available early, the read will have to take place on every clock
cycle wasting some power whether I need to do a read or not.  So it
looks like I will have to do a read on every cycle using the "next
address" and a write only when I need it using the "current address".

I can use a dual port memory and connect one for the read and one for
the write. This can even be done on the same port if the address has a
separate enable.  Then I can use the address input to the block ram as
the address register.  The address is updated on every clock cycle and
a read performed, except when the logic signals a write, then the write
enable is asserted on cycle 1 and the address enable is removed so keep
the same address that was latched on cycle 0.  I see the Altera Cyclone
2 parts have an address enable that will let me hold the last address.
I don't see an address enable on the Xilinx Spartan 3 parts and I am
not sure about the Lattice ECP2 parts as I don't have the full data
sheet.

The only down side to this "trick" is that it adds a bit of time to the
logic path that updates the address register.  But the actual ram setup
time seems to be pretty small and I expect the routing can be kept
pretty minimal as well. So this timing impact may not make the address
setup the critical path.  But I expect the overall timing to change
significantly since the instruction fetch and other internal memory
access will be greatly improved using the sync block ram.  So the
address update may end up as the critical path.

Am I missing something about how to best use a block ram?  Any other
ideas on how to do the read without adding a clock cycle?


Article: 105111
Subject: PLB slaves
From: "Nitesh" <nitesh.guinde@gmail.com>
Date: 13 Jul 2006 20:19:03 -0700
Links: << >>  << T >>  << A >>
Can we have 2 separate plb slaves  in one IP ?
 I am trying to fit 2  slaves in one peripheral .  I am not using IPIF
. I have using different address spaces for the 2 slaves.The process
goes on fine but NGDbuild gives me a problem.
It gives me some errors saying that some signals like  SL_wrdack , has
multiple drivers. I  have changed the mpd file and added 2 slaves
separately

I added the following line in the mpd file and then separately  used
two  set of interface signals to connect them.
## Bus Interfaces
BUS_INTERFACE BUS = SPLB, BUS_STD = PLB, BUS_TYPE = SLAVE
BUS_INTERFACE BUS = MPLB, BUS_STD = PLB, BUS_TYPE = MASTER
BUS_INTERFACE BUS = SPLB, BUS_STD = PLB, BUS_TYPE = SLAVE
 Is it possible  to do that  ? Has anybody tried it  2 slaves in one
peripheral.?

Thanks,
Nitesh


Article: 105112
Subject: Re: Separate enable on address for ram blocks
From: John_H <johnhandwork@mail.com>
Date: Fri, 14 Jul 2006 03:55:09 GMT
Links: << >>  << T >>  << A >>
rickman wrote:
> I am reworking a design I did a couple of years ago to fit a newer
> part.  The original design made use of async ram blocks since they fit
> the application better.  Now I am forced to use registered synchronous
> block rams.  This will create an extra clock delay on reads if I don't
> think of a way around it.  But the clever guy I am, I have come up with
> a couple of alternatives.

<snip>
> Am I missing something about how to best use a block ram?  Any other
> ideas on how to do the read without adding a clock cycle?

Are you *using* the Altera parts?  Xilinx?  Lattice?  You remain 
politically neutral in your discussion but it doesn't help with 
architecture-specific implementations.

Look at the Xilinx WRITE_MODE attribute where NO_CHANGE or WRITE_FIRST 
*might* give you an extra trick up your sleeve for that architecture. 
If you don't need the size of those blocks, perhaps the Altera M512 
blocks have slightly different performance characteristics that could be 
leveraged.  I'm still a big fan of distributed memory as in Xilinx and 
Lattice devices giving that old async kind of feeling.

Do you ever want to read the address you just wrote?  Write during cycle 
1, read from the same registered address on cycle 2?  (More precisely, 
the same combinatorial address also on cycle 1)

Article: 105113
Subject: Re: Obtain old ver ISE Foundation?
From: Ron <News5@spamex.com>
Date: Thu, 13 Jul 2006 22:59:53 -0700
Links: << >>  << T >>  << A >>
Brandon Jasionowski wrote:
> I currently have a license for ISE Foundation 8.1. Is it possible to
> obtain old versions? 

I'll be happy to trade you my ISE Foundation 5.1 for your 8.1. ;-)

-- Ron

Article: 105114
Subject: Re: Where are you heading?
From: Ron <News5@spamex.com>
Date: Thu, 13 Jul 2006 23:52:00 -0700
Links: << >>  << T >>  << A >>
rickman wrote:
> I think if upper management saw all of the posts that Austin makes they
> would likely not be pleased by the way the company is presented.  Or
> maybe they wouldn't have a problem, I can't say.  I do know that the
> apperence is that Xilinx is a rather arrogant company, not unlike Intel
> in the early days.

I totally agree and already reported both Austin and Peter to Xilinx 
marketing as well as corporate management sometime ago via email. It 
seemed to do no good whatsoever, so maybe Xilinx doesn't care. ...Or 
maybe they just need more complaints, preferably via US postal mail on 
company letterhead rather than email. Austin sure spews a lot of 
marketing hype for an engineer who is ostensibly not in marketing.

-- Ron


Article: 105115
Subject: Re: Development Boards -Your chance to suggest features
From: "John Adair" <g1@enterpoint.co.uk>
Date: 13 Jul 2006 23:53:47 -0700
Links: << >>  << T >>  << A >>
A very delayed projected (Broaddown3) will come close to what you want.
This project is awaiting resource but those darned things called
customers keep giving the team more and more work to keep them busy.
Generally we aim to run our team here with on a 50% customer loading
but for many months that has been closer to 100%. However some more
heads are now allowing us some man time to do projects like Swinyard2
and Tarfessock1 and I expecting them to make an appearance in Q3 albeit
at the end of this quarter. Broaddown3 is contending for a slot in
early Q4 but that depends in some extent how well our current
recruitment drive works out. We also have a number of interesting
concepts floating around that could could take precidence. A refreshed
Broaddown1 might even be back on the list for those that know of it's
esoteric capabilities.

Swinyard3 has drawn the shortest straw in getting resources because we
are not as yet sure of the economics to make it succeed as a saleable
item. One of the current big barriers to PCI-E is the price and the
size of FPGA core. There is not a lot of choice out there in cheap
PCI-E cores unlike convertional PCI. We are considering the switch to
something like a PLX solution or even a preprogrammed essentially fixed
front end FPGA to resolve these cost issues so the concept may get
moved around a little.

As to standard board interconnections have you looked at how we do the
build option "OVERCOAT" available on our Raggedstone1, Broaddown2/4,
Holybush1 and just maybe MINI-CAN. We can built parallel/serial arrays
of boards as big as power supply will allow. It's a cheap and simple
way to do it and we can do it in situe in a PC motherboard (subject to
number of slots). We also have a dumb PCI backplane on our list of
things to do for array processing.

But as always if you have an interesting and viable project do talk to
us direct. We do announce things up front that we are doing but there
are projects we don't talk about and just occasionally a customer
requirement, and maybe some money, may tilt which project gets done
first.

John Adair
Enterpoint Ltd.

Brannon wrote:
> I would like a board designed from the ground up to do general software
> acceleration for consumers. That means a fast interface between the
> FPGA and the host computer. It will have to be an external PCIe and DMA
> controller with sufficient PCIe channels (like 4 or 8) and DMA channels
> (like 4 or 8) that I can stream data in and out with. The board would
> have standard ports for connections to other boards of the same type,
> DDR2 memory, and SRAM (all unpopulated on the low-end sales). It could
> have one or several FPGAs on it. It would be even better if it could be
> populated with a range of cheap FPGAs to expensive ones.
>
> John Adair wrote:
> > Following our recent Swinyard1 (Virtex-4) release we are now looking at the
> > Swinyard2 module concept which will be based on a middle end Virtex-5
> > (initial XC5VLX50 and others) that will be supported by our Broaddown series
> > of main development boards. Bearing in mind this a small module what
> > features would you like us to put on this module?


Article: 105116
Subject: Re: Development Boards -Your chance to suggest features
From: "John Adair" <g1@enterpoint.co.uk>
Date: 13 Jul 2006 23:57:29 -0700
Links: << >>  << T >>  << A >>
Project now underway. I will post seperately when I have expected dates
for something being really available for sale. It is Spartan-3E based
this time.

John Adair
Enterpoint Ltd.

radarman wrote:
> John Adair wrote:
> > Following our recent Swinyard1 (Virtex-4) release we are now looking at the
> > Swinyard2 module concept which will be based on a middle end Virtex-5
> > (initial XC5VLX50 and others) that will be supported by our Broaddown series
> > of main development boards. Bearing in mind this a small module what
> > features would you like us to put on this module?
> >
> > and what did you all think of the general Swinyard concept?
> >
> > This is you chance to influence what we deliver to the marketplace so do let
> > us know.
> >
> > John Adair
> > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
> > Board.
> > http://www.enterpoint.co.uk
>
> I would concur with some of the other posters. What would be really
> nice is a selection of decent size Spartan / Virtex parts on a PGA
> board that could be plugged into a socket 370 or socket 478 ZIF. These
> boards should have plenty of bypass caps on them - and it would be nice
> if these boards had a platform flash on them - making them, in essence,
> very nice CPLD's. If done properly, you could even strap a standard
> heatsink/fan unit on top!
>
> There are companies out there that have BGA -> PGA adapters, but then
> you have the little trick of getting the BGA on the board - a
> non-trivial task at best. I would definitely be interested in a
> pre-fitted, tested, PGA module with a Spartan 3/3E or Virtex II/II Pro
> BGA mounted on it.
>
> An ideal board would have:
>
> 1) Standard, commercially available socket pattern for the PGA.
> 2) Onboard 3.3 -> <core voltage> regulator
> 3) Bypass capacitors
> 4) Platform flash
> 5) Optional DDR SDRAM pads (or even devices). These could be on a
> "wing" that extends out past the socket like the Macintosh G3/G4
> processor modules.
> 6) Reasonably high capacity XIlinx or Altera FPGA.
>
> Actually, if you could just make a G3/G4 processor module with a Virtex
> II Pro, you might be able to use an old Macintosh AS a development
> board!


Article: 105117
Subject: EDK adding custom vhdl with multiple arch/entity
From: "Bram van de Kerkhof" <None>
Date: Fri, 14 Jul 2006 09:06:08 +0200
Links: << >>  << T >>  << A >>
Hello,

Im making a custom ip for edk. It generates x.vhd and user_logic.vhd.

You are supposed to design in the user_logic.vhd

But what I want is replace that with a TOP.vhd which contains the
user_logic.vhd and some other arch/entity.

For some reason it keeps looking for the user_logic.vhd.

Is it possible to replace the user_logic.vhd as mentioned above or am I
doing something that isn't possible?

Kind regards Bram



Article: 105118
Subject: Re: PLB slaves
From: "John McCaskill" <junkmail@fastertechnology.com>
Date: 14 Jul 2006 00:43:39 -0700
Links: << >>  << T >>  << A >>
Nitesh wrote:
> Can we have 2 separate plb slaves  in one IP ?
>  I am trying to fit 2  slaves in one peripheral .  I am not using IPIF
> . I have using different address spaces for the 2 slaves.The process
> goes on fine but NGDbuild gives me a problem.
> It gives me some errors saying that some signals like  SL_wrdack , has
> multiple drivers. I  have changed the mpd file and added 2 slaves
> separately
>
> I added the following line in the mpd file and then separately  used
> two  set of interface signals to connect them.
> ## Bus Interfaces
> BUS_INTERFACE BUS = SPLB, BUS_STD = PLB, BUS_TYPE = SLAVE
> BUS_INTERFACE BUS = MPLB, BUS_STD = PLB, BUS_TYPE = MASTER
> BUS_INTERFACE BUS = SPLB, BUS_STD = PLB, BUS_TYPE = SLAVE
>  Is it possible  to do that  ? Has anybody tried it  2 slaves in one
> peripheral.?
>
> Thanks,
> Nitesh


Yes you can have multiple bus interfaces in one peripheral, I have done
it.  The problem with the example above is that both slaves have the
same name because "BUS = SPLB" is used twice. Give them different names
both where the bus is defined, and every where the name is used.

Regards,

John McCaskill.


Article: 105119
Subject: OPB or FSL?
From: Christian Schleiffer <usenet_NOSPAM_@schleiffer.net>
Date: Fri, 14 Jul 2006 11:09:11 +0200
Links: << >>  << T >>  << A >>
Hi everybody,

at the moment, I'm facing the decision wether to connect to a MicroBlaze
through OPB or FSL.
The scenario is as following: I have a huge parallel computing device
with a 64 bit backplane (only moderate data throughput is required).
This backplane has to be interfaced to a MircoBlaze being the central
controller of the device.
Implementing an FSL interface seems a lot easier to me but I can't find
any comparisons of data rates, latency and so forth. Does anybody have
any suggestions on the topic?
Is it possible to trigger interrupts on arriving data with the FSL?

Best regards
/Chris

--
Christian Schleiffer
Communication Security (COSY)
Dept. of Electr. Eng. & Information Science
Ruhr-University Bochum
http://www.crypto.rub.de
cschleiffer@crypto.rub.de

Article: 105120
Subject: design partition across multiple FPGAs
From: shalza.mittal@gmail.com
Date: 14 Jul 2006 02:56:05 -0700
Links: << >>  << T >>  << A >>
Hi,
I am interested to learn more about techniques for design partition
across multiple FPGAs.
Can someone provide me with useful pointers about it

Thanks a lot
Shalza


Article: 105121
Subject: Re: Separate enable on address for ram blocks
From: "Symon" <symon_brewer@hotmail.com>
Date: 14 Jul 2006 12:08:20 +0200
Links: << >>  << T >>  << A >>
Hi Rick,

"rickman" <spamgoeshere4@yahoo.com> wrote in message 
news:1152845614.243674.222440@s13g2000cwa.googlegroups.com...
>
> Now I am forced to use registered synchronous block rams.
>
And about time too! :-)
>
> Am I missing something about how to best use a block ram?  Any other
> ideas on how to do the read without adding a clock cycle?
>
If you have the timing budget, (I guess you have if this is coming from an 
old design) use your idea of a dual port ram with one port for write and one 
for read, but clock the read half on the falling edge.
HTH, Syms.


p.s. DISCLAIMER. I hate using the opposite edge. It's usually bad, costing 
you in the long ruin. (Nice typo, I'll leave that in!) 



Article: 105122
Subject: Re: Separate enable on address for ram blocks
From: "rickman" <spamgoeshere4@yahoo.com>
Date: 14 Jul 2006 03:11:07 -0700
Links: << >>  << T >>  << A >>
John_H wrote:
> rickman wrote:
> > I am reworking a design I did a couple of years ago to fit a newer
> > part.  The original design made use of async ram blocks since they fit
> > the application better.  Now I am forced to use registered synchronous
> > block rams.  This will create an extra clock delay on reads if I don't
> > think of a way around it.  But the clever guy I am, I have come up with
> > a couple of alternatives.
>
> <snip>
> > Am I missing something about how to best use a block ram?  Any other
> > ideas on how to do the read without adding a clock cycle?
>
> Are you *using* the Altera parts?  Xilinx?  Lattice?  You remain
> politically neutral in your discussion but it doesn't help with
> architecture-specific implementations.

I'm looking for the best architecture to implement this design.  I want
to use a low cost device so the choices are Spartan 3, Cyclone 2 or
ECP2.  I would like to optimize for the best architecture and have the
option of porting to other choices.

> Look at the Xilinx WRITE_MODE attribute where NO_CHANGE or WRITE_FIRST
> *might* give you an extra trick up your sleeve for that architecture.
> If you don't need the size of those blocks, perhaps the Altera M512
> blocks have slightly different performance characteristics that could be
> leveraged.  I'm still a big fan of distributed memory as in Xilinx and
> Lattice devices giving that old async kind of feeling.

I am familiar with the write mode features.  I will be using the write
through mode or I think Xilinx calls it "WRITE_FIRST".  Distributed
memory is too small for this application.


> Do you ever want to read the address you just wrote?  Write during cycle
> 1, read from the same registered address on cycle 2?  (More precisely,
> the same combinatorial address also on cycle 1)

The reads and writes in this case will be separate.  I don't actually
need the WRITE_FIRST mode on this memory, but will use it on other
blocks where it implements a stack.  That works great with the sync
block ram.  The main memory works better async.  But I think this may
work out pretty well and it has the potential of speeding up things
overall.


Article: 105123
Subject: Re: EDK adding custom vhdl with multiple arch/entity
From: Andi <00andi@web.de>
Date: Fri, 14 Jul 2006 03:17:22 -0700
Links: << >>  << T >>  << A >>
Hi,

you can replace the user_logic. You need to edit the pao-file located in the data directory of you ip-core. That file contains all the files that edk shall synthesis. Remove user-logic here and add you vhd files.

Andi

Article: 105124
Subject: Re: EDK - Debugging software applications located in ISOCM
From: Andi <00andi@web.de>
Date: Fri, 14 Jul 2006 03:18:31 -0700
Links: << >>  << T >>  << A >>
Hi,

as far as i know you cannot debug c-code in isocm.



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