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Messages from 120075

Article: 120075
Subject: Re: weird PACE Error, not one google result
From: ashes.man@gmail.com
Date: Thu, 31 May 2007 19:54:22 -0700
Links: << >>  << T >>  << A >>
On May 22, 3:50 am, Ligeti <jlls...@gmail.com> wrote:
> Hello
> I get the same problem working with Spartan 3 and Virtex II Pro, it
> started when I was trying the ISE 9.1i Quick Start Tutorial (am new to
> ISE in general), when it comes to pin assigning the pins, PACE gives
> me this message:
> "PACE was unable to parse the HDL source file 'C:\...\counter.vhd' "
> and after that PACE shows this (whatever you call it):
>
> Loading device for application Rf_Device from file '3s200.nph' in
> environmentC:\Xilinx91i.
> ERROR:HDLParsers:3562 - pepExtractor.prj line 1  Expecting 'vhdl' or
> 'verilog'   keyword,  found 'work'.
>
> I searched and search, and the only result was this topic ... so I
> sent an Email to mludwig hoping that he knows by now an answer for
> this, but he didnt answer me :-(
> So I am trying to refresh the topic ... Thats all for the moment,
> thank you!
>
> note: sorry for my bad English.


The problem is in the pepExrtractor.prj file that ISE generates before
calling Pace.  I dont know what generates this file, but in a project
that is OK the file does not exist.  If you delete it, ISE just
regenerates it.  I am sure if you can fix the generation of this file
all problems will go away!  The contents of this file looks like:

work	C:/Repository Working Copies/Link_Peak_and_Hold/
top_level_schematic.vhd

Notice the 'work' keyword it is complaining about at the start...


Article: 120076
Subject: Re: LVDS termination scheme to nonstandard ribbon cable
From: Brian Davis <brimdavis@aol.com>
Date: Thu, 31 May 2007 19:55:28 -0700
Links: << >>  << T >>  << A >>
John_H wrote:
>
>Since the transmitters will tend to have high C as well
> in Xilinx transmitters, reflections should be expected.
>
 FPGA driving FPGA, or FPGA driving non-FPGA, are usually
much easier to deal with.

 My posts cautioning about Cin have always been in the context
of a fast, non-FPGA driver (LVDS, LVDS-ish, ECL, etc. ) into
a FPGA input with big Cin.

 When the thread discussion turned to external matching
networks for ECL drivers, I thought the T-coil Cin
matching scheme would be of interest.

>
> One thing you appear to rely on from previous posts is probing
> of the signal at a point external to the receiver silicon, the
> only place practical to probe.  This will always result in a
> signal that's worse than the actual received signal when high
> Cs (or other impedance mismatches) are involved.
> <snip>
>   The SI results will often provide much better response than your
> practical observations.
>
 I use lab measurements to verify my simple first or second
order SPICE simulation models at the points I CAN observe,
after which I can then experiment in simulation with some
comfort of reality being conserved at the receiver input.

 I 'forward' clock and test signals on/off chip using
LVDS DIFF_OUT buffers and OFDDR's, letting me measure
clock distribution without the need for a DCM.

 A mechanical trombone line allows an internal sample clock
to be offset without any need to worry about DCM jitter or
other on-chip delay techniques.

 Tek probes of 15-20 years ago in the form of an SD-14
or P6150 (with bias offset), on an 1180x or CSA803 sampler,
can easily measure 1 Gbps LVDS, with minimal loading impact,
and are practically free since the dot com telecom bust.

 Note that sometimes my use of the word "probe" is intended in
the context of "bus probe", in which case the external probe
is capturing and analyzing the bus traffic- this requires the
reflections be damped or otherwise equalized at the point
of probe attachment so that the sample clock is usable.

>
> It really is C/2 for those who are thinking 100 ohm impedance.
> It really is C for those who are thinking 50 ohm impedance.
> Where are peoples' minds normally on the impedance for LVDS?
> There are no lies here.
>
 When I say "10 pf Cin (single ended)", I am specifically
referencing Xilinx's only datasheet spec for capacitance,
called Cin, which is a single-ended specification.

 I have pointed this out to Austin numerous times, yet he
still insists on "correcting" ( his term ) any references
to Xilinx's published Cin values, even after I started
explicitly postfixing the '(single ended)' whenever I
reference Cin.

 My references to C_COMP and C_PKG are also, like their
IBIS values, single ended.

 I am loath to quote the calculation Cin/2 instead of the
actual specification values because :

  1) It's only valid if the input is perfectly differential

  2) A more realistic input model includes pin-pin capacitance
   separately as Cdiff, giving a calculated total differential
   capacitance Ccalc = Cdiff + Cin/2

 IIRC, one of the IBIS summit papers discussed LVDS modeling
using a C_DIFF, C_PKG, and C_IN, but I can't turn up the
paper just now.

>
> I love that a 600 Mbit link in the "cheap" S3E devices
> hampered not by one but by TWO DCMs can result in an eye
> that's still half open; I could blame just about all of
> that mess on the DCMs, not the LVDS transceivers.
>
 I also think the S3E's are great.

 C_PKG + C_COMP ~= 3 pf,  $$ < 10, at quantity 1 in VQ100

Brian


Article: 120077
Subject: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
From: Peter Alfke <alfke@sbcglobal.net>
Date: Thu, 31 May 2007 20:03:12 -0700
Links: << >>  << T >>  << A >>
So were microprocessors and PCs in an earlier era, and amateur (ham)
radio even earlier...
Peter Alfke,
Plus ca change, plus c'est la meme chose.
======================================
On May 31, 7:33 pm, Alan Nishioka <a...@nishioka.com> wrote:
> On May 30, 4:06 pm, Peter Alfke <p...@xilinx.com> wrote:
>
>
>
> > On May 30, 3:08 pm, "u_stad...@yahoo.de" <u_stad...@yahoo.de> wrote:
>
> > > hi
>
> > > just a quick question: i saw that there is one x-fest in vienna on
> > > june 21.
> > > i am a student. can i register and attend aswell? and is it really
> > > free?
>
> > > thanks
> > > Urban
>
> > The answer is: Yes, yes, and yes.
> > The earlier engineers/students become familiar with our parts, the
> > better.
> > Herzlich willkommen. Es ist nie zu frueh, mit FPGAs vertraut zu
> > werden.
> > Peter
>
> So, to tie in with another part of this thread, FPGA's really are like
> drugs. Get them while they're young and the first hit is free.
>
> Alan Nishioka
> a...@nishioka.com



Article: 120078
Subject: Re: Quartus-II 7.1 Systemverilog interface?
From: "Altera User" <altera_user@nospam.com>
Date: Thu, 31 May 2007 20:24:59 -0700
Links: << >>  << T >>  << A >>
Ok, I tried your suggestion, but Quartus-II doesn't seem to like
interface-modports as port-declarations

module my_module(
  cpu_if.vga if_vga
  );

// ^^^ produces some arcane error about 'port direction' must be specified.

The error goes away if I drop the modport (.vga) from the port-declaration,
but obviously, that just leads back to my original problem.

I'd be very grateful if you could post a known *working* example
with modports in module-port declarations!

"Edmond Coté" <edmond.cote@gmail.com> wrote in message 
news:1180393293.936039.203110@g4g2000hsf.googlegroups.com...
> What am I doing wrong?

You are doing tons wrong ;)

The interface specifies the collection of signals, and a modport
declaration inside the interface specifies the direction of those
signals, which is what I believe what you wanted to achieve.

The following snippet should help you get started, but you'll find a
wealth of information online that can describe how to use interfaces
much better than I ever could... in a short-time frame that is.

interface cpu_if;
  logic [15:0] cpu_addr;
  logic          cpu_write;
  logic          cpu_read;
  logic [15:0] cpu_wdata;
  logic [15:0] cpu_rdata;

modport vga (
  input  cpu_addr,
  input  cpu_write,
  input  cpu_read,
  input  cpu_wdata,
  output cpu_rdata
);

modport cpu (
output cpu_addr,
  output cpu_write,
  output cpu_read,
  output cpu_wdata,
  input  cpu_rdata
);

endinterface // cpu_if

-- Edmond Coté



Article: 120079
Subject: Re: FIR ON FPGA
From: "Bob" <nimby_NEEDSPAM@roadrunner.com>
Date: Thu, 31 May 2007 20:28:17 -0700
Links: << >>  << T >>  << A >>

"bngguy" <bngguy@gmail.com> wrote in message 
news:1180492021.200997.137630@i38g2000prf.googlegroups.com...
> Hi,
>    I'm working on implementing an FIR Filter on a FPGA (Spartan 3E),
> here's what i want to accomplish -->
>
> The FIR Filter coefficients are generated on a host system using
> LabView, these coefficients are written to a RAM / PROM on a DSP
> card , the number of taps is constant but other parameters like
> sampling frequency and cut off frequencies can change according to
> requirements.
>
> The FPGA reads these coefficients from the RAM / PROM and implements
> the FIR Filter.There should be a single bit file that is downloaded to
> configure the FPGA.
>
> Any pointers in the right direction would be appreciated.
>
> Thanks
> Tim
>

There's an echo in here.

Bob



Article: 120080
Subject: Re: Spartan-3E DIG-3E1600 Development Board Kit
From: Tommy Thorn <tommy.thorn@gmail.com>
Date: Thu, 31 May 2007 20:41:19 -0700
Links: << >>  << T >>  << A >>
On May 31, 6:14 pm, Eric Smith <e...@brouhaha.com> wrote:
> At some point Digilent will probably start selling that board directly,
> without the EDK.

Well, they used to (I got one), but stopped around the time Xilinx
started offering it for sale for much more. That suggests something to
me.

Too bad, it's a nice card (except for the lame 3-bit VGA). The
Spartan-3A kit fixes that, but the XC3S700A is way too small IMO.

Tommy


Article: 120081
Subject: Re: LVDS termination scheme to nonstandard ribbon cable
From: Brian Davis <brimdavis@aol.com>
Date: Thu, 31 May 2007 20:54:28 -0700
Links: << >>  << T >>  << A >>
Some additions to John's advice, assuming we are talking
of an original S3 family device ( not E,A,AN,... )

John_H wrote:
>
> The receiver should be the differential impedance of the cable and of
> the transmitter - they should all (roughly) match.  If you have an
> external termination at the receiver, change it to the 173 ohm value if
> that's the true differential impedance.  If the termination is internal
> at 100 ohms, add two 36 ohm resistors (or thereabouts) to get the
> impedance match, albeit at a reduced signal amplitude.
>

 If this is an original Spartan-3, the differential terminations
are not available, so external terminations will be needed.

 Put them as close to the package as you can, especially for any
clock or strobe signals.

>
> On the transmitter, you want a 100 ohm to 173 ohm impedance match so the
> transmitter sees 100 ohm but the transmission line sees 173 ohm.  You'll
> need a differential termination on the transmitter side of this network
> and two series resistors to the ribbon cable.  The signal amplitude will
> again be reduced.
>

 Here, I'd suggest a switch to the LDT output standard instead
of LVDS, which will give you higher minimum drive and will help
make up for the lower output amplitude caused by the series
matching resistors.

 I'd normally suggest using LVDS_EXT, another variant of LVDS
with extra drive, but in the original S3, the differential
output specs are a bit odd, with Vod(min) of only 100 mV for
both LVDS and LVDS_EXT, unless you have a certain mask revision.
( See table 37 of DS099 v2.2 )

 As you are going FPGA to FPGA, you can switch the I/O standards
on both ends, but watch the change in SSO limits for the various
differential standards ( See table 49 of DS099 v2.2 )

Brian



Article: 120082
Subject: Re: FIR ON FPGA
From: TonyTSE99 <TonyTSE99@gmail.com>
Date: Fri, 01 Jun 2007 03:56:10 -0000
Links: << >>  << T >>  << A >>
On May 31, 8:28 pm, "Bob" <nimby_NEEDS...@roadrunner.com> wrote:
> "bngguy" <bng...@gmail.com> wrote in message
>
> news:1180492021.200997.137630@i38g2000prf.googlegroups.com...
>
>
>
> > Hi,
> >    I'm working on implementing an FIR Filter on a FPGA (Spartan 3E),
> > here's what i want to accomplish -->
>
> > The FIR Filter coefficients are generated on a host system using
> > LabView, these coefficients are written to a RAM / PROM on a DSP
> > card , the number of taps is constant but other parameters like
> > sampling frequency and cut off frequencies can change according to
> > requirements.
>
> > The FPGA reads these coefficients from the RAM / PROM and implements
> > the FIR Filter.There should be a single bit file that is downloaded to
> > configure the FPGA.
>
> > Any pointers in the right direction would be appreciated.
>
> > Thanks
> > Tim
>
> There's an echo in here.
>
> Bob


Hi Tim,

Your post looks like a previous post, but perhaps you didn't get the
response you were looking for ...

So, here's a more detailed response.

Spartan 3E ranges from :
4-36 multipliers
2K-33K logic cells

Your choices for FIR implementation are :
Distributed Arithmetic FIR Filters
Multiplier Based FIR Filters

Distributed Arithmetic (DA) will tend to provide small size, high
speed operations, but are more difficult to change coefficients (you
have to calculate ROM LUT values from the coefficients).

Multiplier based FIR structures can take advantage of the built-in
multipliers, and are much easier to reload, but there's a limited
number of multipliers.  Multiplier

>From a flexibility standpoint, multiplier based FIR filters are a bit
more flexible than DA FIR structures.  Multiplier structures (MAC)
range (in area vs performance) from N multipliers - 1 clock cycle per
computation, to  N clocks and 1 multiplier (where N=the number of
coefficients).

DA fir structures range in computation rate from 1 clock (fully
parallel) to M clocks (where M = input bit width).  Usually, the input
bit width may be as high as 16 bits, so we're usually ranging up to 16
clocks.

Naturally, there's some wiggle room in both of the above paragraphs,
as it's possible to take advantage of symmetry to decrease the number
of multipliers in half for the MAC based FIR filters.  Symmetry can
also add another clock cycle to serial distributed arithmetic FIR
filters while decreasing the number of ROM LUT's by half.  There are
other tricks such as polyphase decomposition for interpolation and
decimation which can also reduce multiplier and ROM LUT usage.

Xilinx provides a distributed arithmetic FIR filter generator as part
of ISE, and it produces good results, but since it's basically a black
box, you'll be dependent on the vendor and may have to perform gate
level simulation.

You may be interested in looking at a new clear text human readable
Verilog based FIR filter generator from Optunis (
http://www.optunis.com/fir_hdl_writer/fir_hdl_writer_info.html ),
which also generates a testbench for impulse, step, and random
response.  It's new (still in Beta) and utilizes the hard multipliers
built into Spartan 3E.

Best of Luck,

Tony



Article: 120083
Subject: Re: accesing JTAG ports on GPIOs
From: maverick <sheikh.m.farhan@gmail.com>
Date: Thu, 31 May 2007 21:12:25 -0700
Links: << >>  << T >>  << A >>
On May 30, 6:54 pm, maverick <sheikh.m.far...@gmail.com> wrote:
> On May 30, 3:32 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
>
>
>
>
> > On 29 Mai, 15:33, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > maverick schrieb:> Hi there,
> > > > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> > > > > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> > > > > from using ChipScope pro on this board to debug my design. Is it
> > > > > possible somehow to tap the jtag ports internally and route them to
> > > > > GPIOs which are available on th board! In that case, I will insert the
> > > > > ChipScope Pro core in my design in the normal fashion and will put
> > > > > that part of the code in the design that will tap the JTAG ports
> > > > > internally and will map them to other GPIOs?
>
> > > > > Farhan
>
> > > > sure, get it here:
>
> > > >http://code.google.com/p/fpga-tools/downloads/list
>
> > > > Antti
>
> > > Hi Antti,
> > > Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd
> > > file. Unfortunately, I am a Verilog writer and do not have much
> > > exposure to VHDL code. What I have understood from the code is, I have
> > > to instantiate this primitive into my design and map the IO to FPGA
> > > IOs. It will make my life easy if you can demonstrate it by making
> > > required changes in the following simple counter code as it is not
> > > clear to me how would I make the chipscope logic communicate to this
> > > primitive. In the following code, assume that I have to monitor 8-bit
> > > counter reg in chipscope pro.
>
> > just use the VHDL in your verilog design should be no issue
> > all modern synthesis tools support mixed language designs.
>
> > Antti- Hide quoted text -
>
> > - Show quoted text -
>
> Thanks Antti for the reply,
> Yes, I am aware of the feature of mixed language synthesis. But here,
> I am more interested to know how to use these soft BSCAN primitives in
> the case where I need to use Chip SCope pro as well. Kindly modify the
> sample program I posted earlier to show the changes required to
> incorporate BSCAN primitive to use chip scope pro using GPIOs.
>
> Thanks- Hide quoted text -
>
> - Show quoted text -

Hi Antti,
I am anxiously waiting for your guidance on my problem. Kindly, do
reply....

Farhan


Article: 120084
Subject: Re: Spartan-3E DIG-3E1600 Development Board Kit
From: John_H <newsgroup@johnhandwork.com>
Date: Fri, 01 Jun 2007 04:45:17 GMT
Links: << >>  << T >>  << A >>
Eric Smith wrote:
> Sandro wrote:
>> I know the "Spartan-3E 1600E MicroBlaze Development Kit" use the same
>> board ...but I don't need EDK...
> 
> Buy it, and resell the EDK?
> 
> At some point Digilent will probably start selling that board directly,
> without the EDK.  Their deal with Xilinx might have an exclusivity
> period, or they might just not yet be able to build more than Xilinx is
> ordering.  But the other Digilent boards sold by Xilinx have eventually
> become available directly from Digilent.
<snip>

I got the board from them early on as well.  I figured the Xilinx 
exclusivity was the reason for "not currently for sale" but since XIlinx 
has the "buy from Digilent" link, if anyone wants this board...

Call Digilent, please!

Article: 120085
Subject: Re: Ise Flow with PowerPC
From: subint <subin.82@gmail.com>
Date: Thu, 31 May 2007 21:46:17 -0700
Links: << >>  << T >>  << A >>
On May 31, 9:42 pm, Pablo <pbantu...@gmail.com> wrote:
> On 31 mayo, 18:31, Joseph Samson <jsam...@the-company-name.com> wrote:
>
>
>
> > Pablo wrote:
> > > Hi, I am very interesting in how could I use ISE to create a PowerPC
> > > model.
>
> > <snip>
>
> > > But I cannot see the complete vhdl code. For example I cannot see the
> > > code from the dcm_module, the code from the util_vector_module, etc.
>
> > > I know that quite a lot designers use this ISE Flow, but how can they
> > > see the complete project in vhdl.
>
> > The VHDL for the EDK IP is not available. You can go to
> > $XILINX_EDK/hw/XilinxProcessorIPLib/pcores to see the IP that can be
> > instantiated from EDK. There are VHDL wrappers that instantiate black
> > boxes. In some cases (plb_ethernet) there is encrypted VHDL.
>
> > ---
> > Joe Samson
> > Pixel Velocity
>
> So the only thing I could edit is the system_stub.vhd and the
> system.vhd with inputs and outputs. Cores couldn't be edited. Correct
> me?

Yes you are right..


Article: 120086
Subject: After PAR simulation, should I assume that it will work on FPGA board?
From: Sandip <sandip.gaikwad@gmail.com>
Date: Fri, 01 Jun 2007 04:52:17 -0000
Links: << >>  << T >>  << A >>
Hi,
I am using ML403 board consisting of Virtex-4 device. I have simulated
my design on ISE 8.1i. I completed simulation after synthesis then,
Translate, Post-map and Post-PAR. I was getting desired results on
Simulation using 100Mhz as my clock frequency.
Next thing i did was put it on board and verify that design. Input
clock was now 8Mhz. But the output I was getting was not desirable.
Can any body help me in debugging this issue. Please let me know if I
am missing any steps to get it right.

Thanks and regards,
Sandip


Article: 120087
Subject: Re: After PAR simulation, should I assume that it will work on FPGA
From: Mark McDougall <markm@vl.com.au>
Date: Fri, 01 Jun 2007 15:08:31 +1000
Links: << >>  << T >>  << A >>
Sandip wrote:

> Next thing i did was put it on board and verify that design. Input
> clock was now 8Mhz. 

8MHz sounds too low for an FPGA clock, not that I'm overly familiar with
Xilinx devices. Check the fMin on the DCM...

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 120088
Subject: Re: After PAR simulation, should I assume that it will work on FPGA board?
From: Thomas Stanka <usenet_10@stanka-web.de>
Date: Thu, 31 May 2007 22:11:47 -0700
Links: << >>  << T >>  << A >>
On 1 Jun., 06:52, Sandip <sandip.gaik...@gmail.com> wrote:
> my design on ISE 8.1i. I completed simulation after synthesis then,
> Translate, Post-map and Post-PAR. I was getting desired results on
> Simulation using 100Mhz as my clock frequency.

Post-PAR means at least using the netlist instead of rtl code.
But is useless without timing information. I assume you used timing,
else start using sdf files.

> Next thing i did was put it on board and verify that design. Input
> clock was now 8Mhz. But the output I was getting was not desirable.

Identify differences between your testbench and the real world.
First thing to look: simulate asynchronous inputs switch typically
with fixed delay to clock, real asynchronous inputs need proper
handling.

The designflow you described seems to include all necessary steps, so
I expect the problem to arise from your design.

bye Thomas


Article: 120089
Subject: Re: ISE/EDK Kubuntu linux installation issues
From: "MM" <mbmsv@yahoo.com>
Date: Fri, 1 Jun 2007 01:24:53 -0400
Links: << >>  << T >>  << A >>
Hi Ken,

I had actually got the cable working before you posted your detailed 
instructions, but thanks a lot anyways, it's all very useful information!

I am now fighting the EDK, which doesn't want to start (the ISE seems to 
work fine), and the issues of equalizing the environment for all the 
possible ways of starting all of the Xilinx applications. I am just learning 
about how the environment variables are handled in Ubuntu and it is 
definitely not straightforward at all...At the moment my Impact works only 
when I start it from the shell... But I believe I am on the right track, 
just need a little bit of time to figure it all out...

> Three cheers to Michael Gernoth for his outstanding work in solving this 
> problem (not to mention realizing it *could* be solved)!

That is indeed a great achievement!!!

Thanks,
/Mikhail 



Article: 120090
Subject: Re: weird PACE Error, not one google result
From: ashes.man@gmail.com
Date: Thu, 31 May 2007 22:27:27 -0700
Links: << >>  << T >>  << A >>
On Jun 1, 2:54 pm, ashes....@gmail.com wrote:
> On May 22, 3:50 am, Ligeti <jlls...@gmail.com> wrote:
>
>
>
> > Hello
> > I get the same problem working with Spartan 3 and Virtex II Pro, it
> > started when I was trying the ISE 9.1i Quick Start Tutorial (am new to
> > ISE in general), when it comes to pin assigning the pins, PACE gives
> > me this message:
> > "PACE was unable to parse the HDL source file 'C:\...\counter.vhd' "
> > and after that PACE shows this (whatever you call it):
>
> > Loading device for application Rf_Device from file '3s200.nph' in
> > environmentC:\Xilinx91i.
> > ERROR:HDLParsers:3562 - pepExtractor.prj line 1  Expecting 'vhdl' or
> > 'verilog'   keyword,  found 'work'.
>
> > I searched and search, and the only result was this topic ... so I
> > sent an Email to mludwig hoping that he knows by now an answer for
> > this, but he didnt answer me :-(
> > So I am trying to refresh the topic ... Thats all for the moment,
> > thank you!
>
> > note: sorry for my bad English.
>
> The problem is in the pepExrtractor.prj file that ISE generates before
> calling Pace.  I dont know what generates this file, but in a project
> that is OK the file does not exist.  If you delete it, ISE just
> regenerates it.  I am sure if you can fix the generation of this file
> all problems will go away!  The contents of this file looks like:
>
> work    C:/Repository Working Copies/Link_Peak_and_Hold/
> top_level_schematic.vhd
>
> Notice the 'work' keyword it is complaining about at the start...

OK HERE IS THE ANSWER ... IF THERE ARE SPACES IN THE DIRECTORY NAMES
IN THE PATH THEN THIS PROBLEM AOCCURS.  Make sure all directory names
right back to the root directory have no spaces ... sheesh, that took
some working out!!!  Thanks for all the useful information on the
diagnostic code xilinx!!!


Article: 120091
Subject: Re: Cyclone 3 Starter Board Question
From: fpgabuilder <fpgabuilder-groups@yahoo.com>
Date: Fri, 01 Jun 2007 05:41:58 -0000
Links: << >>  << T >>  << A >>
On May 31, 4:42 pm, ghel...@lycos.com wrote:
> On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote:
>
> > Anyone know how the USB Blaster cable loads data to the C3 fpga on the
> > board?  The schematic shows a CPLD between the FPGA and the USB port.
> > There is a USB to parallel chip between the cpld and the usb port.
> > But I do not see any serial or parallel data going to the fpga.
>
> > I wish Altera added more details to the starter kit documentation.
> > There is all this source code but it is encrypted.  So  cannot even
> > look at that.
>
> > TIA
> > -sanjay
>
> That CPLD along with the FT245 is the "embedded USB Blaster".  You
> won't see any lines to the FPGA except for the JTAG leads.  (I found
> the JTAG lines on the schematic - look again.)
>
> The documentation looked pretty complete to me.  For the Xilinx board,
> the page of schematic with the USB loader is *missing*, and that area
> of the layout is obscured.
>
> Both companies used to ship separate dongles with their eval boards.
> But the plastic case of the dongle is the most expensive part,
> followed by the JTAG leads.  By leaving those out, they can add the
> USB programmer for almost nothing.
>
> It's possible that both companies contracted out the design of their
> USB programming pods, so they can't (legally) distribute the
> information on the device.  (Both companies make a ton of money
> selling IP; you have to understand that they will respect the IP
> rights of others.)
>
> Do a web search.  There are a number of people actively tring to
> reverse engineer both dongles.  At least until they discover hat
> they're spending 100's of hours to duplicate a gizmo that can be had
> for $50...
>
> G.

Sorry I wasn't clear.  By data I did not mean the configuration or
jtag stream.  Not sure if you are familiar with the C3 starter board.
But they have something called control panel, which you use to test
the dram access besides other things.  You can read and write to the
sdram.  Store entire files, etc.  And the only host interface I see
for this is the usb interface.  But I do not see any data lines.  So
that is what I mean by data.

Please let me know where to look if you find that in their
documentation.

Thanks.
Best,
-sanjay


Article: 120092
Subject: Re: accesing JTAG ports on GPIOs
From: Antti <Antti.Lukats@googlemail.com>
Date: Thu, 31 May 2007 23:06:10 -0700
Links: << >>  << T >>  << A >>
On 1 Jun., 06:12, maverick <sheikh.m.far...@gmail.com> wrote:
> On May 30, 6:54 pm, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > On May 30, 3:32 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > On 29 Mai, 15:33, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > > On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > maverick schrieb:> Hi there,
> > > > > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> > > > > > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> > > > > > from using ChipScope pro on this board to debug my design. Is it
> > > > > > possible somehow to tap the jtag ports internally and route them to
> > > > > > GPIOs which are available on th board! In that case, I will insert the
> > > > > > ChipScope Pro core in my design in the normal fashion and will put
> > > > > > that part of the code in the design that will tap the JTAG ports
> > > > > > internally and will map them to other GPIOs?
>
> > > > > > Farhan
>
> > > > > sure, get it here:
>
> > > > >http://code.google.com/p/fpga-tools/downloads/list
>
> > > > > Antti
>
> > > > Hi Antti,
> > > > Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd
> > > > file. Unfortunately, I am a Verilog writer and do not have much
> > > > exposure to VHDL code. What I have understood from the code is, I have
> > > > to instantiate this primitive into my design and map the IO to FPGA
> > > > IOs. It will make my life easy if you can demonstrate it by making
> > > > required changes in the following simple counter code as it is not
> > > > clear to me how would I make the chipscope logic communicate to this
> > > > primitive. In the following code, assume that I have to monitor 8-bit
> > > > counter reg in chipscope pro.
>
> > > just use the VHDL in your verilog design should be no issue
> > > all modern synthesis tools support mixed language designs.
>
> > > Antti- Hide quoted text -
>
> > > - Show quoted text -
>
> > Thanks Antti for the reply,
> > Yes, I am aware of the feature of mixed language synthesis. But here,
> > I am more interested to know how to use these soft BSCAN primitives in
> > the case where I need to use Chip SCope pro as well. Kindly modify the
> > sample program I posted earlier to show the changes required to
> > incorporate BSCAN primitive to use chip scope pro using GPIOs.
>
> > Thanks- Hide quoted text -
>
> > - Show quoted text -
>
> Hi Antti,
> I am anxiously waiting for your guidance on my problem. Kindly, do
> reply....
>
> Farhan- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -

Dear maverick,

sure I can: "Kindly modify the sample program you posted posted
earlier.."
so if you wish that please contact me in private  - the hourly fee is
50EUR + 19%TAX

if you just want other people to do your work, or things you dont want
to learn
then I guess you must wait, or seek another job

Antti


Article: 120093
Subject: s3 starterkit problem
From: Antti <Antti.Lukats@googlemail.com>
Date: Thu, 31 May 2007 23:15:58 -0700
Links: << >>  << T >>  << A >>
Hi

after adding just one GPIO to Xilinx spartan-3A webserver demo design,
the system started to fail

everything starts up ok, but after setting IP, at the time where lwip
should start there microblaze
seems to stall badly, so badly that XMD reports that reset is
activated (what isnt the case)
as long the webserver is not running the system is stable

the same happens when the filesystem image and webserver elf are
loaded from micro-SD card
(connected to that extra GPIO) or with XMD over JTAG

when the system gets stuck, it really looks like microblaze is in some
weird run-away stuck
state and cant recover any more

Antti


Article: 120094
Subject: Actel Cortex M1, any info on license fee?
From: Antti <Antti.Lukats@googlemail.com>
Date: Thu, 31 May 2007 23:20:44 -0700
Links: << >>  << T >>  << A >>
Actel is known lying before, they namly claimed that the use of ARM7
in Actel FPGA is free, actually the FPGA with AES128 that allows the
use of ARM7 costs 100 USD more then FPGA without the key, and well I
would not call 100USD "free"

Now Actel is about to release the smaller Cortex based FPGA (eg
another key for cortex-enable), again Actel claim its "Free" - I hope
they are not lying this time, and there extra cost for Cortex is 0.00,
but if that isnt the case, what is the license fee? is it the same
100USD as it is for ARM7 or is it smaller?

Antti

PS the 100 USD license fee has been quoted by the distributors for qty
1. For 100.000 qty the license fee per chip drops below 2 USD per FPGA
used.


Article: 120095
Subject: Re: Cyclone 3 Starter Board Question
From: Antti <Antti.Lukats@googlemail.com>
Date: Thu, 31 May 2007 23:36:32 -0700
Links: << >>  << T >>  << A >>
On 1 Jun., 07:41, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote:
> On May 31, 4:42 pm, ghel...@lycos.com wrote:
>
>
>
>
>
> > On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote:
>
> > > Anyone know how the USB Blaster cable loads data to the C3 fpga on the
> > > board?  The schematic shows a CPLD between the FPGA and the USB port.
> > > There is a USB to parallel chip between the cpld and the usb port.
> > > But I do not see any serial or parallel data going to the fpga.
>
> > > I wish Altera added more details to the starter kit documentation.
> > > There is all this source code but it is encrypted.  So  cannot even
> > > look at that.
>
> > > TIA
> > > -sanjay
>
> > That CPLD along with the FT245 is the "embedded USB Blaster".  You
> > won't see any lines to the FPGA except for the JTAG leads.  (I found
> > the JTAG lines on the schematic - look again.)
>
> > The documentation looked pretty complete to me.  For the Xilinx board,
> > the page of schematic with the USB loader is *missing*, and that area
> > of the layout is obscured.
>
> > Both companies used to ship separate dongles with their eval boards.
> > But the plastic case of the dongle is the most expensive part,
> > followed by the JTAG leads.  By leaving those out, they can add the
> > USB programmer for almost nothing.
>
> > It's possible that both companies contracted out the design of their
> > USB programming pods, so they can't (legally) distribute the
> > information on the device.  (Both companies make a ton of money
> > selling IP; you have to understand that they will respect the IP
> > rights of others.)
>
> > Do a web search.  There are a number of people actively tring to
> > reverse engineer both dongles.  At least until they discover hat
> > they're spending 100's of hours to duplicate a gizmo that can be had
> > for $50...
>
> > G.
>
> Sorry I wasn't clear.  By data I did not mean the configuration or
> jtag stream.  Not sure if you are familiar with the C3 starter board.
> But they have something called control panel, which you use to test
> the dram access besides other things.  You can read and write to the
> sdram.  Store entire files, etc.  And the only host interface I see
> for this is the usb interface.  But I do not see any data lines.  So
> that is what I mean by data.
>
> Please let me know where to look if you find that in their
> documentation.
>
> Thanks.
> Best,
> -sanjay- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -


well, there is no need for more then JTAG lines ;)
Altera FPGAs can have user logic in fabric connected to the JTAG TAP,
so the same JTAG pins can be used to talk to the user app as well.
this is how signaltap works as example

Antti




Article: 120096
Subject: Re: accesing JTAG ports on GPIOs
From: maverick <sheikh.m.farhan@gmail.com>
Date: Thu, 31 May 2007 23:42:57 -0700
Links: << >>  << T >>  << A >>
On Jun 1, 11:06 am, Antti <Antti.Luk...@googlemail.com> wrote:
> On 1 Jun., 06:12, maverick <sheikh.m.far...@gmail.com> wrote:
>
>
>
>
>
> > On May 30, 6:54 pm, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > On May 30, 3:32 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > On 29 Mai, 15:33, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > > > On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > > maverick schrieb:> Hi there,
> > > > > > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> > > > > > > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> > > > > > > from using ChipScope pro on this board to debug my design. Is it
> > > > > > > possible somehow to tap the jtag ports internally and route them to
> > > > > > > GPIOs which are available on th board! In that case, I will insert the
> > > > > > > ChipScope Pro core in my design in the normal fashion and will put
> > > > > > > that part of the code in the design that will tap the JTAG ports
> > > > > > > internally and will map them to other GPIOs?
>
> > > > > > > Farhan
>
> > > > > > sure, get it here:
>
> > > > > >http://code.google.com/p/fpga-tools/downloads/list
>
> > > > > > Antti
>
> > > > > Hi Antti,
> > > > > Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd
> > > > > file. Unfortunately, I am a Verilog writer and do not have much
> > > > > exposure to VHDL code. What I have understood from the code is, I have
> > > > > to instantiate this primitive into my design and map the IO to FPGA
> > > > > IOs. It will make my life easy if you can demonstrate it by making
> > > > > required changes in the following simple counter code as it is not
> > > > > clear to me how would I make the chipscope logic communicate to this
> > > > > primitive. In the following code, assume that I have to monitor 8-bit
> > > > > counter reg in chipscope pro.
>
> > > > just use the VHDL in your verilog design should be no issue
> > > > all modern synthesis tools support mixed language designs.
>
> > > > Antti- Hide quoted text -
>
> > > > - Show quoted text -
>
> > > Thanks Antti for the reply,
> > > Yes, I am aware of the feature of mixed language synthesis. But here,
> > > I am more interested to know how to use these soft BSCAN primitives in
> > > the case where I need to use Chip SCope pro as well. Kindly modify the
> > > sample program I posted earlier to show the changes required to
> > > incorporate BSCAN primitive to use chip scope pro using GPIOs.
>
> > > Thanks- Hide quoted text -
>
> > > - Show quoted text -
>
> > Hi Antti,
> > I am anxiously waiting for your guidance on my problem. Kindly, do
> > reply....
>
> > Farhan- Zitierten Text ausblenden -
>
> > - Zitierten Text anzeigen -
>
> Dear maverick,
>
> sure I can: "Kindly modify the sample program you posted posted
> earlier.."
> so if you wish that please contact me in private  - the hourly fee is
> 50EUR + 19%TAX
>
> if you just want other people to do your work, or things you dont want
> to learn
> then I guess you must wait, or seek another job
>
> Antti- Hide quoted text -
>
> - Show quoted text -

Hi Antti,
I never meant it that way that you do my work. , I am sorry in case if
I have made you feel like that. Anyways, thanks for your help.



Article: 120097
Subject: Re: accesing JTAG ports on GPIOs
From: Antti <Antti.Lukats@googlemail.com>
Date: Thu, 31 May 2007 23:44:52 -0700
Links: << >>  << T >>  << A >>
On 1 Jun., 08:42, maverick <sheikh.m.far...@gmail.com> wrote:
> On Jun 1, 11:06 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
>
>
>
>
> > On 1 Jun., 06:12, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > On May 30, 6:54 pm, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > > On May 30, 3:32 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > On 29 Mai, 15:33, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > > > > On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > > > maverick schrieb:> Hi there,
> > > > > > > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> > > > > > > > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> > > > > > > > from using ChipScope pro on this board to debug my design. Is it
> > > > > > > > possible somehow to tap the jtag ports internally and route them to
> > > > > > > > GPIOs which are available on th board! In that case, I will insert the
> > > > > > > > ChipScope Pro core in my design in the normal fashion and will put
> > > > > > > > that part of the code in the design that will tap the JTAG ports
> > > > > > > > internally and will map them to other GPIOs?
>
> > > > > > > > Farhan
>
> > > > > > > sure, get it here:
>
> > > > > > >http://code.google.com/p/fpga-tools/downloads/list
>
> > > > > > > Antti
>
> > > > > > Hi Antti,
> > > > > > Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd
> > > > > > file. Unfortunately, I am a Verilog writer and do not have much
> > > > > > exposure to VHDL code. What I have understood from the code is, I have
> > > > > > to instantiate this primitive into my design and map the IO to FPGA
> > > > > > IOs. It will make my life easy if you can demonstrate it by making
> > > > > > required changes in the following simple counter code as it is not
> > > > > > clear to me how would I make the chipscope logic communicate to this
> > > > > > primitive. In the following code, assume that I have to monitor 8-bit
> > > > > > counter reg in chipscope pro.
>
> > > > > just use the VHDL in your verilog design should be no issue
> > > > > all modern synthesis tools support mixed language designs.
>
> > > > > Antti- Hide quoted text -
>
> > > > > - Show quoted text -
>
> > > > Thanks Antti for the reply,
> > > > Yes, I am aware of the feature of mixed language synthesis. But here,
> > > > I am more interested to know how to use these soft BSCAN primitives in
> > > > the case where I need to use Chip SCope pro as well. Kindly modify the
> > > > sample program I posted earlier to show the changes required to
> > > > incorporate BSCAN primitive to use chip scope pro using GPIOs.
>
> > > > Thanks- Hide quoted text -
>
> > > > - Show quoted text -
>
> > > Hi Antti,
> > > I am anxiously waiting for your guidance on my problem. Kindly, do
> > > reply....
>
> > > Farhan- Zitierten Text ausblenden -
>
> > > - Zitierten Text anzeigen -
>
> > Dear maverick,
>
> > sure I can: "Kindly modify the sample program you posted posted
> > earlier.."
> > so if you wish that please contact me in private  - the hourly fee is
> > 50EUR + 19%TAX
>
> > if you just want other people to do your work, or things you dont want
> > to learn
> > then I guess you must wait, or seek another job
>
> > Antti- Hide quoted text -
>
> > - Show quoted text -
>
> Hi Antti,
> I never meant it that way that you do my work. , I am sorry in case if
> I have made you feel like that. Anyways, thanks for your help.- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -

well read what you wrote your self.
what you need can be done with a few mouseclicks.
but if I do it for you never learn.

Antti





Article: 120098
Subject: Re: accesing JTAG ports on GPIOs
From: maverick <sheikh.m.farhan@gmail.com>
Date: Thu, 31 May 2007 23:59:03 -0700
Links: << >>  << T >>  << A >>
On Jun 1, 11:44 am, Antti <Antti.Luk...@googlemail.com> wrote:
> On 1 Jun., 08:42, maverick <sheikh.m.far...@gmail.com> wrote:
>
>
>
>
>
> > On Jun 1, 11:06 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > On 1 Jun., 06:12, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > > On May 30, 6:54 pm, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > > > On May 30, 3:32 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > > On 29 Mai, 15:33, maverick <sheikh.m.far...@gmail.com> wrote:
>
> > > > > > > On May 28, 10:19 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > > > > maverick schrieb:> Hi there,
> > > > > > > > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are
> > > > > > > > > routed on this board (TMS, TDI, TDO, TCK ). This really deprives me
> > > > > > > > > from using ChipScope pro on this board to debug my design. Is it
> > > > > > > > > possible somehow to tap the jtag ports internally and route them to
> > > > > > > > > GPIOs which are available on th board! In that case, I will insert the
> > > > > > > > > ChipScope Pro core in my design in the normal fashion and will put
> > > > > > > > > that part of the code in the design that will tap the JTAG ports
> > > > > > > > > internally and will map them to other GPIOs?
>
> > > > > > > > > Farhan
>
> > > > > > > > sure, get it here:
>
> > > > > > > >http://code.google.com/p/fpga-tools/downloads/list
>
> > > > > > > > Antti
>
> > > > > > > Hi Antti,
> > > > > > > Thanks alot for the reply. I did have a look at the Spartan3-1000.vhd
> > > > > > > file. Unfortunately, I am a Verilog writer and do not have much
> > > > > > > exposure to VHDL code. What I have understood from the code is, I have
> > > > > > > to instantiate this primitive into my design and map the IO to FPGA
> > > > > > > IOs. It will make my life easy if you can demonstrate it by making
> > > > > > > required changes in the following simple counter code as it is not
> > > > > > > clear to me how would I make the chipscope logic communicate to this
> > > > > > > primitive. In the following code, assume that I have to monitor 8-bit
> > > > > > > counter reg in chipscope pro.
>
> > > > > > just use the VHDL in your verilog design should be no issue
> > > > > > all modern synthesis tools support mixed language designs.
>
> > > > > > Antti- Hide quoted text -
>
> > > > > > - Show quoted text -
>
> > > > > Thanks Antti for the reply,
> > > > > Yes, I am aware of the feature of mixed language synthesis. But here,
> > > > > I am more interested to know how to use these soft BSCAN primitives in
> > > > > the case where I need to use Chip SCope pro as well. Kindly modify the
> > > > > sample program I posted earlier to show the changes required to
> > > > > incorporate BSCAN primitive to use chip scope pro using GPIOs.
>
> > > > > Thanks- Hide quoted text -
>
> > > > > - Show quoted text -
>
> > > > Hi Antti,
> > > > I am anxiously waiting for your guidance on my problem. Kindly, do
> > > > reply....
>
> > > > Farhan- Zitierten Text ausblenden -
>
> > > > - Zitierten Text anzeigen -
>
> > > Dear maverick,
>
> > > sure I can: "Kindly modify the sample program you posted posted
> > > earlier.."
> > > so if you wish that please contact me in private  - the hourly fee is
> > > 50EUR + 19%TAX
>
> > > if you just want other people to do your work, or things you dont want
> > > to learn
> > > then I guess you must wait, or seek another job
>
> > > Antti- Hide quoted text -
>
> > > - Show quoted text -
>
> > Hi Antti,
> > I never meant it that way that you do my work. , I am sorry in case if
> > I have made you feel like that. Anyways, thanks for your help.- Zitierten Text ausblenden -
>
> > - Zitierten Text anzeigen -
>
> well read what you wrote your self.
> what you need can be done with a few mouseclicks.
> but if I do it for you never learn.
>
> Antti- Hide quoted text -
>
> - Show quoted text -

Sure,
I will work on it,
thanks


Article: 120099
Subject: Re: VHDL core for Hitachi H8S or H8/300H CPU?
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 01 Jun 2007 00:36:35 -0700
Links: << >>  << T >>  << A >>
On 7 Mai, 12:34, Michael Wilspang <mich...@wilspang.dk> wrote:
> Hi
> are there anybody who have knowledge about
> some free VHDL core for Hitachi H8S orH8/300H CPU?
>
> Regards
> /Michael Wilspang

http://japanese.sugawara-systems.com/opencores.htm

there is download link for H8 ip core

Antti




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1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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