Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Only one of the ports can be written, but in this case that works. Nicholas C. Weaver wrote: > In article <3718BD15.4E473B3@qub.ac.uk>, > Khaled benkrid <k.benkrid@qub.ac.uk> wrote: > >And how is the content of the RAM modified on the fly for the 4k series > >(JTAG?). > > THe later ones of the 4000 series allow both LUTS in a single > CLB to act as a single, dual ported, 16x1 RAM, so you have the > "compute lut" be one port, and reconfigure through the second. > > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15876
The idea there is you have two banks of configuration registers on the chip, so that you can load a new configuration into one bank while the chip is running with the configuration stored in the other bank. Then after the new configuration is loaded, you switch the control of the whole chip from one configuration to the other. It doesn't reduce the time to get a configuration onto the chip, it just allows you to switch between previously loaded configurations in one clock cycle. Such a beast could have application in certain data-path (read DSP) designs. One of the motivations toward such an animal is to reduce the actual gate count by reusing the logic resource. The extra overhead for switching between two configurations this way is significant, and the net power may be higher than an equivalent non-time-multiplexed design depending on how often it needed to be switched. Such a chip has no real advantage in traditional designs; it is a special architecture designed to answer some of the device limitations encountered in reconfigurable computing. Tim Tyler wrote: > Mark <mkinsley@xs4all.nl> wrote: > : I like to possibilities offered by reconfigurable FPGAs [...] > > : What i think would be really interesting, is being able to re-configure > : an entire FPGA really quickly (say 1 system clock period ideally) [...] > > One clock period for a whole FPGA's worth of LUT data? You are going to > need one fat pipe ;-) > > : ....any comments ? > > What applications are there which require such rapid reconfiguration - > and can't be reasonably cheaply implemented by using a number of parts? > -- > __________ > |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com > > 6.50129 - the natural logarithm of the Beast. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15877
I'm just starting out too. I got the Xilinx CPLD starter kit with the Foundation 1.5i series software from www.insight-electronics.com for $99. It's pretty good because it comes with everything you need including the XChecker parallel programming cable and the software as well as a prototype board with a XC9536 CPLD. The part comes programmed with a Johnson counter program. You will, however need to get a few parts to complete the board (this was somewhat disappointing). A LM2940 5v regulator, switch, and 22uF cap seems to be missing. Weird. The software that comes with the kit will program FPGAs as well as the CPLDs. The XChecker cable has both the JTAG and the FPGA signals. The only thing that's missing is support for VHDL. I'm programming using ABEL and schematic based designs. They want another $390 for the VHDL upgrade. I don't think it's worth it at this point for me. I needed to get all the patches on the www.xilinx.com site to successfully implement a design because the software was getting errors out of the box. Xilinx tech support was pretty good diagnosing the problem. Another thing that I'd suggest is to get "The Practical Xilinx Designers Lab Book" that's available at Amazon.com. Thanks to Jan Gray for suggesting this. Good book. They have schematics for both CPLD and FPGA development boards as well as lots of great projects including microcontoller based designs. I also read "Digital Design using ABEL". Bad book, I don't recommend it. GaryArticle: 15878
There seems to be a lot of people asking about learning about FPGAs. I want to start a discussion about good books. In the short term, I personally have a need for a good book describing Verilog (I did VHDL in the past) and PLI. Any other related categories are welcome. - VHDL - FPGA programming etc. -Edwin -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15879
I want to implement a Forth Engine like the RTX2000 on an FPGA. Any help would be appreciated. Don Golding Angelus Research Corp. (909) 794-8325 http://www.angelusresearch.comArticle: 15880
Don Golding wrote in message <7fcu4r$hd6@dfw-ixnews6.ix.netcom.com>... >I want to implement a Forth Engine like the RTX2000 on an FPGA. Any help >would be appreciated. One superb example is the MSL16 microprocessor. See Leong, P.H.W, P.K. Tsang, and T.K. Lee, "A FPGA based Forth microprocessor", pp. 254-255, in Proc. IEEE Symp. on FPGAs for Custom Computing Machines 1998, and at http://www.cse.cuhk.edu.hk/~phwl/msl16/msl16.html, and Paul Lee Wai Lun's thesis and presentation, "FPGA Implementation of a Forth Processor", at http://home.hkstar.com/~wail/project-7260/project.htm. Jan GrayArticle: 15881
My altera flex10k200e design takes about 8 hours to place and route. I needed to change one gate in my design (and inverter to a buffer) and Altera tech support told me I had to start the place and route (i.e. "recompile") from scratch. They said that there was no way to make a minor change like this and that there was no way to directly edit the LUT equations by hand. They say that this capbility may be available by year end. Is this true? When I used to work with the Xilinx Xact SW I remember that you could edit any block directly and then immediately write out a new chip file. No fitting or rerouting was neccesary of course becuase no interconnects were changed and no blocks were moved. Is it really possible that the Altera SW has no means of doing this? Note that in the past Altera tech support also told me that it was impossible to run the altera SW from the command line. They said that the GUI was the only way. A posting on this newsgroup show us how to do it. please help pasquale@zoran.comArticle: 15882
Yes, it is true. Get used to it.
There is no way to edit any post P&R logic equation using the Altera MAX
Plus + II software ("MP2"). If you want to change an inverter to a buffer,
you have to start over. I have this on good authority, as my Altera FAE,
Steve Kliman, out of Austin TX, is very knowledgeable.
What you want, of course, is the equivalent function of the Xilinx LCA
editor, and "you can't get there from here". The MP2 software does include
a "floor plan editor" but it is of very limited utility for actual editing
use, although it is handy for browsing a design to troubleshoot synthesis
and P&R problems.
I believe this is a deliberate strategy to prevent version mismatches
between the source files and the programming files, but I have to say that
IMHO, it can be a bitter pill to swallow. Although, I have to admit that
with Altera I've never had the problem of "orphan" designs that have been
tweaked in the LCA editor to the extent that you cannot do a complete
re-compile P&R cycle on them. In these situations the original source
code/schematics becomes a back-annotated piece of documentation for
informational purposes only, and it can kind of sneak up on you.
Having said that, there is one MP2 Fitter switch that you might want to
check, because it has made BIG difference for us. We have a number of 10K70
designs that are 95-99% full (LC utilization). The menu path is:
/Assign/Global Project Timing Requirements/Ignore Timing Assignments during
Fitting
For our designs, checking this box, to allow the fitter to ignore timing
assignments, brought our Fitter times down from 10-20 hours to 1-2 hours.
The default setting is for the Fitter to NOT ignore timing assignments
during fitting. The MP2 logic synthesizer still honors the timing
constraints, and structures the logic accordingly. We were initially
concerned that this would interfere with meeting our 25 MHz critical paths,
but our designs usually come out even BETTER with the fitter ignorant of
timing. Go figure...
The future ability to do low-level post P&R editing must be in the new
"Quartus" software package that is in beta right now, is this what you are
referring to?
Tom Meagher A Xilinx refugee in the strange world of Altera.
(I would love to be wrong on this one and have someone correct me.)
pasquale wrote in message <371A1D1F.2E618F3C@zoran.com>...
>
>My altera flex10k200e design takes about 8 hours to place and route.
>I needed to change one gate in my design (and inverter to a buffer)
>and Altera tech support told me I had to start the place and route
>(i.e. "recompile") from scratch. They said that there was no way
>to make a minor change like this and that there was no way
>to directly edit the LUT equations by hand.
>They say that this capbility may be available by year end.
>
>Is this true?
>
>When I used to work with the Xilinx Xact SW I remember that you could edit
>any block directly and then immediately write out a new chip file.
>No fitting or rerouting was neccesary of course becuase no
>interconnects were changed and no blocks were moved.
>Is it really possible that the Altera SW has no means of doing this?
>Note that in the past Altera tech support also told me that
>it was impossible to run the altera SW from the command line.
>They said that the GUI was the only way. A posting on this newsgroup
>show us how to do it.
>
>
>please help
>
>pasquale@zoran.com
Article: 15883I would venture to say that it would require a new paradigm in EDA tool functionality to actually develop useful multi-context FPGA configurations. The conceptual hardware extension to the FPGA architecture is simple and straighforward, but to manage this flexibility and apply it to general problems seems like another thing altogether. Without the proper design environment it would rapidly become an albatross around the poor visionary's neck, eh? I am sure that this is a rich field for researchers, and the EE Times article on the NEC device ( http://www.eetimes.com/story/OEG19990215S0004 ) does make slight mention of it, along with older Xilinx work in the multi-context area. Frankly, I doubt the world is quite ready for it yet. Sort of like the Transputer. Hopefully I am wrong on this, as there may be enough specialized applications, such as MPEG encoding/decoding, encryption/decryption, etc., where it may make economic sense to use a multi-context FPGA, since you never have to have silicon "just sitting aroung". Could there actually be an important class of applications where a multi-context FPGA might be able to do the same job in the same time frame with *less* silicon than an ASIC? This would make it cost effective from every standpoint, instead of being the slow, bloated, and expensive poor relation to the ASIC that it is today. Tom Meagher Ray Andraka wrote in message <3718E256.ABA0C0AB@ids.net>... >The idea there is you have two banks of configuration registers on the chip, >so that you can load a new configuration into one bank while the chip is >running with the configuration stored in the other bank. Then after the new >configuration is loaded, you switch the control of the whole chip from one >configuration to the other. It doesn't reduce the time to get a >configuration onto the chip, it just allows you to switch between previously >loaded configurations in one clock cycle. > >Such a beast could have application in certain data-path (read DSP) designs. >One of the motivations toward such an animal is to reduce the actual gate >count by reusing the logic resource. The extra overhead for switching >between two configurations this way is significant, and the net power may be >higher than an equivalent non-time-multiplexed design depending on how often >it needed to be switched. Such a chip has no real advantage in traditional >designs; it is a special architecture designed to answer some of the device >limitations encountered in reconfigurable computing. > >Tim Tyler wrote: > >> Mark <mkinsley@xs4all.nl> wrote: >> : I like to possibilities offered by reconfigurable FPGAs [...] >> >> : What i think would be really interesting, is being able to re-configure >> : an entire FPGA really quickly (say 1 system clock period ideally) [...] >> >> One clock period for a whole FPGA's worth of LUT data? You are going to >> need one fat pipe ;-) >> >> : ....any comments ? >> >> What applications are there which require such rapid reconfiguration - >> and can't be reasonably cheaply implemented by using a number of parts? >> -- >> __________ >> |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com >> >> 6.50129 - the natural logarithm of the Beast. > > > >-- >-Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email randraka@ids.net >http://users.ids.net/~randraka > >Article: 15884
I don't usually do VHDL but I think I see what the problem is:
> entity bidir is
> PORT (in_data : IN STD_LOGIC;
> data_oe: IN STD_LOGIC;
> out_data: OUT STD_LOGIC;
> bi_data: inout std_ulogic);
> end bidir;
>
You need an output and an input not output and inout. Here is how the
IO should look like
OE >--------
|
|\|
OUT >---- | \___________ PIN
| / |
|/ |
|
IN <-------------
So what you need is (given bi_data is PIN) :
entity bidir is
PORT (in_data : OUT STD_LOGIC;
data_oe: IN STD_LOGIC;
out_data: IN STD_LOGIC;
bi_data: inout std_ulogic);
end bidir;
architecture bidir_arch of bidir is
begin
process (in_data, data_oe, bi_data)
begin
in_data <= bi_data;
if data_oe='1' then
bi_data <= out_data;
else
bi_data <= 'Z';
end if;
end process;
end bidir_arch;
Now you can drive your out_data signal to the pin and when your driver
is Z, you can read the pin by in_data signal.
Alois HAHN <alois.hahn@neuroth.co.at> wrote:
>Thanks Thomas,
>The code is now accepted by the MAXPLUS synthesizer.
>But ... Simulation of the resulting netlist shows that
>the block does not work as I expected.
>
>I want to have a birectional IO Pad, whose logic state can be
>read inside the chip (at 'out_data').
>In your example the synthesizer places at tristate buffer
>to 'out_data'. So 'outdata' becomes High-Z exactly at the
>time I want to use the input function.
>
>Any ideas ?
>Alois
>
>
>Thomas Hellerforth wrote:
>>
>> This one should work:
>>
>> library IEEE;
>> use IEEE.std_logic_1164.all;
>>
>> entity bidir is
>> PORT (in_data : IN STD_LOGIC;
>> data_oe: IN STD_LOGIC;
>> out_data: OUT STD_LOGIC;
>> bi_data: inout std_ulogic);
>> end bidir;
>> .........
muzo
Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email)
Article: 15885Ray Andraka <randraka@ids.net> wrote: > There are a few devices out there that support partial reconfiguration to > varying degrees. Currently sold devices include Atmel 6K and 40K, Xilinx > 6200 and Virtex. And Lucent. You always forget Lucent. Am I the only one in the world using these chips?Article: 15886
CALL-FOR-PAPER
AP-ASIC'99
THE FIRST IEEE ASIA-PACIFIC CONFERENCE ON ASICS
August 22-25, 1999
Seoul, Korea
Organized by IEEE SSCS/EDS
Sponsored by IEEE SSCS,IEEE SSCS Tokyo Chapter
IEEE SSCS Taipei Chapter
IEEK,KIEE,KICS,KISS, IEEE Seoul Section
Prospective authors should submit an unpublished extended summary
of about 800 words along with equations and figures.
Topics for regular sessions include, but are not limited to the followings:
1.Analog Circuits
2.Digital Circuits
3.Communication Circuits
4.Memory Circuits
5.Microprocessors & Microcontrollers
6.Signal Processing Circuits
7.Design Reuse and IP
8.Sensor/Imager/Mems Circuits
9.Design for Testability
Submission should include:
1) A cover sheet containing:
a) Title of the submitted paper, authors' names and
affiliations
b) Postal address, phone & FAX numbers and e-mail
address of the contact author
c) Paper category numbers (from the above list) that best
describe the paper
d) Name of the presenter author
2) The extended abstract summary containing:
e) Paper title, authors' names, affilations, addresses, and emails
f) Paper category numbers (from the above list)
Author's schedule:
¡Ý Submission of Extended Summary: May 10, 1999
¡Ý Notification of Acceptance: May 30, 1999
¡Ý Submission of Camera-ready Paper: July 20, 1999
¡Ý Special Session and Tutorial Proposal: May 30, 1999
An electronic summary should be submitted to the following email address:
AP-ASIC¡¯99 E-mail: asic@spark.yonsei.ac.kr
If electronic submission is not possible, three hard copies of the
extended summary should be sent directly to:
AP-ASIC¡¯99
Research Institute of ASIC Design
Yonsei University
Seoul 120-749, Korea
Tel: +82-2-361-3523
Fax: +82-2-364-8162
General Chair:
Moon-Key Lee, Yonsei University
E-mail: mklee@bubble.yonsei.ac.kr
Conference Chair:
Hyung-Kyu Lim, Samsung Electronics Co.
E-mail: sshklim@samsung.co.kr
Technical Program Chair:
Oh-Hyun Kwon, Samsung Electronics Co.
E-mail: ssohkwon@samsung.co.kr
Secretary:
Kwang S. Yoon, Inha University
E-mail: ksyoon@dragon.inha.ac.kr
Manuscript guide-lines ( MS Word, PS or
PDF) and further informations can be found at:
http://www.ee.inha.ac.kr/ap-asic99
--
------------------------------------------------------
Prof. Jun-Dong Cho, Ph.D. SrMIEEE, MACM
VLSI Algorithmic Design Automation Lab.
Dept. of Electrical and Computer Engineering
Sungkyunkwan University
300 Chunchun-Dong, Changan-Ku, Suwon, Korea 440-746
office: (0331) 290-7127 fax: (0331) 290-5819
home: (02) 504-2976 pcs: (018) 247-7127
http://vada.skku.ac.kr/jdcho jdcho@yurim.skku.ac.kr
------------------------------------------------------
Article: 15887
Hi,
Flex(MAX?) can not DIRECTLY connect bidirectional pin to
output pin. So Internal LE(LCELL primitive) must be used.
(maxplus helpfile "Primitive/Port Interconnections" section)
The ports name of LCELL may be different in your synthesizer.
And when bidir pin='Z', output pin will be X in simulation, because Flex
can not have internal tristate.
VHDL compiler in Maxplus2 will accept next example.
------- example.---------
library IEEE;
use IEEE.std_logic_1164.all;
entity test is
PORT (in_data : IN STD_LOGIC;
data_oe: IN STD_LOGIC;
out_data: OUT STD_LOGIC;
bi_data: inout std_ulogic);
end test;
architecture bidir_arch of test is
component LCELL
port(
a_in : in std_logic;
a_out : out std_logic
);
end component;
begin
process (in_data,data_oe)
begin
if data_oe='1' then
bi_data <= in_data;
else
bi_data <= 'Z';
end if;
end process;
inside : LCELL port map(
a_in => bi_data,
a_out => out_data
);
end bidir_arch;
>The code is now accepted by the MAXPLUS synthesizer.
>But ... Simulation of the resulting netlist shows that
>the block does not work as I expected.
>
>I want to have a birectional IO Pad, whose logic state can be
>read inside the chip (at 'out_data').
>In your example the synthesizer places at tristate buffer
>to 'out_data'. So 'outdata' becomes High-Z exactly at the
>time I want to use the input function.
>
>Any ideas ?
>Alois
>
>
>Thomas Hellerforth wrote:
>>
>> This one should work:
>>
>> library IEEE;
>> use IEEE.std_logic_1164.all;
>>
>> entity bidir is
>> PORT (in_data : IN STD_LOGIC;
>> data_oe: IN STD_LOGIC;
>> out_data: OUT STD_LOGIC;
>> bi_data: inout std_ulogic);
>> end bidir;
>> .........
Article: 15888I have a tool designed expressely for that purpose. Check my sig at the bottom. Simon ======================= On Sun, 18 Apr 1999 08:40:47 -0700, "Don Golding" <angelus@ix.netcom.com> wrote: >I want to implement a Forth Engine like the RTX2000 on an FPGA. Any help >would be appreciated. > >Don Golding >Angelus Research Corp. >(909) 794-8325 > >http://www.angelusresearch.com > > > Simon - http://www.tefbbs.com/spacetime/index.htmlArticle: 15889
Ok, Finally I'm going on with VHDL I found a good interactive tutorial an a good VHDL book from Cypress, which comes with some useful examples. Now I'm looking for free or low cost software for circuit simulation, starting from VHDL code. Any suggestion welcome. P.S.: Did someone use Cypress chips and tools here? Thanks in advance Damiano Rullo Trezzano S/N Milan, Italy http://members.it.tripod.de/Damianoux/index.html mailto: dmn@cheerful.com mailto: damiano@mclink.itArticle: 15890
Hi All. Is there a site where I can find PCB schematics for circuits using FPGA chips (expecially Lattice ISPs)? Thanks Damiano Rullo Trezzano S/N Milan, Italy http://members.it.tripod.de/Damianoux/index.html mailto: dmn@cheerful.com mailto: damiano@mclink.itArticle: 15891
Thanx Ken, your input is excellent. The bidir problem is solved now. greetings from Vienna/Austria Alois Ken Yasui wrote: > > Hi, > Flex(MAX?) can not DIRECTLY connect bidirectional pin to > output pin. So Internal LE(LCELL primitive) must be used. > (maxplus helpfile "Primitive/Port Interconnections" section) > > The ports name of LCELL may be different in your synthesizer. > And when bidir pin='Z', output pin will be X in simulation, because Flex > can not have internal tristate. ...Article: 15892
Mark wrote: > I like to possibilities offered by reconfigurable FPGAs, but it seems > most of the devices around are designed to be loaded once on power up, > and maybe reconfigured to do something different if the designer is > being really ingenuitive. > > an entire FPGA really quickly (say 1 system clock period ideally). This > translates into the idea of having 'layers' of FPGA config data which > can be latched into the FPGA config area. The inactive 'layers' being > updated or replaced while not in use -> pretty much like a video display > where an image is built up in the off screen buffer before the active > video buffer is toggled. > To some extent the Xilinx FPGA's are reprogrammable on the fly -- today. Remember that they use sram based CLB's that implement Universal Logic Modules (ULMs). The 4 input look up tables are just 1x16 rams. Consequently, if its just the logic equations you want to modify then reloading the rams should be straightforward. (IE this exercise left to the reader -- perhaps using a microcode approach :) This would imply that your placement and interconnect didn't need to change. That would limit the scope of reconfiguration but might still solve a few problems. Thinking of reconfiguration as a whole scale change might be making the problem to large. Perhaps not all problems require a complete logic re-map, placement, and routing effort. I would think that the regularity of DSP structures <insert Andraka comment here> would be amenable to fixed placement of resources but with a degree of variable routing. With that in mind it wouldn't require vast numbers of pentiums to recompute the P&R and you might also have some chance of getting a one-clock reconfiguration (though perhaps not in the current breed of part.) without huge amounts of configuration silicon overhead. I guess what also would be ideal is to have the bitstream load order designed in such a way that you could load or reload one row of CLB's at a time. That way you could choose to have a large fixed portion of the design with a few rows reconfigured on the fly without having to reload the whole device. Just thinking out loud. -- Tim Davis Timothy Davis Consulting TimDavis@TDCon.com - +1 (303) 426-0800 - Fax +1 (303) 426-1023Article: 15893
This is a multi-part message in MIME format.
--------------E8DBC18E5550BDC5EC61AA15
Content-Type: multipart/alternative;
boundary="------------7F4331147336E0F920759E08"
--------------7F4331147336E0F920759E08
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
George,
Be sure you are specifying a reset or intializing state for your state
machine:
i.e. in VHDL
process (CLOCK, RESET)
begin
if (RESET='1') then
Current_state <= Init_State;
elsif (CLOCK'event and CLOCK = '1') then
Current_state <= Next_State;
endif
end process
i.e. in Verilog
always @ (posedge CLOCK or posedge RESET)
begin
if (RESET == 1'b1)
Current_State = Init_State;
else
Current_State = Next_State;
end
If the RESET is not described for the registers of the State machine, most
(if not all) synthesis tools would defaultly infer an initialization state
of '0' for all FFs which would instantly put you in an undefined state for
true one-hot state machines.
If you wish to see some example code of a few state machine, take a look
at the Synthesis and Simulation Design guide at:
http://support.xilinx.com/appnotes/hdl_dg.pdf
Hope this helps you out.
-- Brian
"George E. Smith, Jr" wrote:
> Hi
> Has anyone experienced problems with one hot FSM's not getting there
> initial state
> set? I'm useing Xilinx Alliance 1.5i and Synplicity. Seems that a reset
> ff is being selected
> instead of a preset.
>
> Thanks
>
> --
> George Smith
> Avalex Technologies
> Atlanta, Ga.
> 404.256.3010
>
> I.R.S. We have what it takes to take what you have.
> -- Support the national sales tax.
--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------
--------------7F4331147336E0F920759E08
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
<p>George,
<p> Be sure you are specifying a reset or intializing
state for your state machine:
<p>i.e. in VHDL
<p>process (CLOCK, RESET)
<br>begin
<br> if (RESET='1') then
<br> Current_state <= Init_State;
<br> elsif (CLOCK'event and CLOCK = '1') then
<br> Current_state <= Next_State;
<br> endif
<br>end process
<p>i.e. in Verilog
<p>always @ (posedge CLOCK or posedge RESET)
<br>begin
<br> if (RESET == 1'b1)
<br> Current_State = Init_State;
<br> else
<br> Current_State = Next_State;
<br>end
<p>If the RESET is not described for the registers of the State machine,
most (if not all) synthesis tools would defaultly infer an initialization
state of '0' for all FFs which would instantly put you in an undefined
state for true one-hot state machines.
<p>If you wish to see some example code of a few state machine, take a
look at the Synthesis and Simulation Design guide at: <A HREF="http://support.xilinx.com/appnotes/hdl_dg.pdf">http://support.xilinx.com/appnotes/hdl_dg.pdf</A>
<br>
<p>Hope this helps you out.
<br>
<p>-- Brian
<br>
<br>
<br>
<p>"George E. Smith, Jr" wrote:
<blockquote TYPE=CITE>Hi
<br> Has anyone experienced problems with one hot FSM's not getting
there
<br>initial state
<br>set? I'm useing Xilinx Alliance 1.5i and Synplicity. Seems that a reset
<br>ff is being selected
<br>instead of a preset.
<p>Thanks
<p>--
<br> George Smith
<br> Avalex Technologies
<br> Atlanta, Ga.
<br> 404.256.3010
<p> I.R.S. We have what it takes to take what you have.
<br> -- Support the national sales tax.</blockquote>
<pre>--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------</pre>
</html>
--------------7F4331147336E0F920759E08--
--------------E8DBC18E5550BDC5EC61AA15
Content-Type: text/x-vcard; charset=us-ascii;
name="brianp.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Brian Philofsky
Content-Disposition: attachment;
filename="brianp.vcf"
begin:vcard
n:Philofsky;Brian
tel;fax:(408) 879-4442
tel;work:1-800-255-7778
x-mozilla-html:TRUE
org:<br><img src="http://www.xilinx.com/images/xlogoc.gif" alt="Xilinx"><BR><BR>;Xilinx Design Center
version:2.1
email;internet:brianp@xilinx.com
title:Application Engineer
adr;quoted-printable:;;2100 Logic Drive=0D=0ADept. 2510;San Jose;CA;95124-3450;USA
x-mozilla-cpt:;-12504
fn:Brian Philofsky
end:vcard
--------------E8DBC18E5550BDC5EC61AA15--
Article: 15894
This is a multi-part message in MIME format.
--------------2675ED314BADBB88C461353E
Content-Type: multipart/alternative;
boundary="------------BA71FC25A65B632B21FB6AE5"
--------------BA71FC25A65B632B21FB6AE5
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Ken,
The best way this can be implemented in VHDL is to structurally
describe it. While it is possible to behaviorally describe a similar
structure (excluding the pullup), it will consume more resources than if
it is structurally instantiated. I will include a little sample code to
help you out with this implementation.
-- Brian
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity wand_test is
port (A: in STD_LOGIC_VECTOR(7 downto 0);
Z: out STD_LOGIC);
end wand_test;
architecture STRUCTURAL of wand_test is
component WAND1
port (I : in STD_LOGIC;
O : out STD_LOGIC);
end component;
component PULLUP
port (O : out STD_LOGIC);
end component;
begin
U0: WAND1 port map (I=>A(0), O=>Z);
U1: WAND1 port map (I=>A(1), O=>Z);
U2: WAND1 port map (I=>A(2), O=>Z);
U3: WAND1 port map (I=>A(3), O=>Z);
U4: WAND1 port map (I=>A(4), O=>Z);
U5: WAND1 port map (I=>A(5), O=>Z);
U6: WAND1 port map (I=>A(6), O=>Z);
U7: WAND1 port map (I=>A(7), O=>Z);
U8: PULLUP port map (O=>Z);
end STRUCTURAL;
Ken Chung wrote:
> Hi,
> I would like to ask how can I make use of the wire-AND
> property in the longline of Xilinx XC4000 series? Can I write
> VHDL code to describe it? or I can only do it by manual routing?
> Any advice is much appreciated.
>
> Regards,
> Ken
--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------
--------------BA71FC25A65B632B21FB6AE5
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
<p>Ken,
<p> The best way this can be implemented in VHDL is to
structurally describe it. While it is possible to behaviorally describe
a similar structure (excluding the pullup), it will consume more resources
than if it is structurally instantiated. I will include a little
sample code to help you out with this implementation.
<p>-- Brian
<br>
<p>library IEEE;
<br>use IEEE.std_logic_1164.all;
<br>use IEEE.std_logic_unsigned.all;
<p>entity wand_test is
<br> port (A: in STD_LOGIC_VECTOR(7 downto 0);
<br> Z: out STD_LOGIC);
<br>end wand_test;
<br>
<br>architecture STRUCTURAL of wand_test is
<br>
<br>component WAND1
<br> port (I : in STD_LOGIC;
<br>
O : out STD_LOGIC);
<br>end component;
<p>component PULLUP
<br> port (O : out STD_LOGIC);
<br>end component;
<br>
<br> begin
<p> U0: WAND1 port map (I=>A(0), O=>Z);
<br> U1: WAND1 port map (I=>A(1), O=>Z);
<br> U2: WAND1 port map (I=>A(2), O=>Z);
<br> U3: WAND1 port map (I=>A(3), O=>Z);
<br> U4: WAND1 port map (I=>A(4), O=>Z);
<br> U5: WAND1 port map (I=>A(5), O=>Z);
<br> U6: WAND1 port map (I=>A(6), O=>Z);
<br> U7: WAND1 port map (I=>A(7), O=>Z);
<p> U8: PULLUP port map (O=>Z);
<br>
<br>end STRUCTURAL;
<br>
<br>
<br>
<br>
<p>Ken Chung wrote:
<blockquote TYPE=CITE>Hi,
<br> I would like to ask how
can I make use of the wire-AND
<br>property in the longline of Xilinx XC4000 series? Can I write
<br>VHDL code to describe it? or I can only do it by manual routing?
<br>Any advice is much appreciated.
<p>Regards,
<br>Ken</blockquote>
<pre>--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------</pre>
</html>
--------------BA71FC25A65B632B21FB6AE5--
--------------2675ED314BADBB88C461353E
Content-Type: text/x-vcard; charset=us-ascii;
name="brianp.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Brian Philofsky
Content-Disposition: attachment;
filename="brianp.vcf"
begin:vcard
n:Philofsky;Brian
tel;fax:(408) 879-4442
tel;work:1-800-255-7778
x-mozilla-html:TRUE
org:<br><img src="http://www.xilinx.com/images/xlogoc.gif" alt="Xilinx"><BR><BR>;Xilinx Design Center
version:2.1
email;internet:brianp@xilinx.com
title:Application Engineer
adr;quoted-printable:;;2100 Logic Drive=0D=0ADept. 2510;San Jose;CA;95124-3450;USA
x-mozilla-cpt:;-12504
fn:Brian Philofsky
end:vcard
--------------2675ED314BADBB88C461353E--
Article: 15895If you would like to learn about the latest developments in PLD and FPGA technology then visit the Ninth Annual Advanced PLD and FPGA Conference and Exhibition at Sandown Park on 12th May 1999. Full details of the technical conference programme, a list of exhibitors and how to register can be found at www.pldconf.comArticle: 15896
I had a similar problem with FLEX8000 from Altera. I made a simple solution: I do an serial EPROM emulator. I have a logic circuit that it take a paralel EVPROM (or EEPROM) and converts its data to serial data. You can make your experiments in the paralel EEPROM and when the design is ended, you can fit it in a OTP ROM or EPROM. Bye !!!Article: 15897
Grzegorz Labiak wrote in message <371c9ef7.4103360@news.amu.edu.pl>... >Hi! > >I'm looking for any information about Statechart. Does anyone have any >interesting links and info about software releated to Statechart? I downloaded a Lite version of BetterState from their web site. BetterState uses Statechart formalism, and can optionally generate VHDL code. I can't find the URL, but you should be able to find it with a web search. Statemate is a similar product, but I don't think they have a downloadable version. LeonArticle: 15898
Hi. I'm looking for the paper for texture mapping hardware. I want to download this document. ThanksArticle: 15899
Does anybody has instantiated a TDO pin for output with Exemplar ?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z