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mehdi bousfiha <el.mehdi.bousfiha@gmail.com> wrote: > Hi everyone, i'm realy excited about starting my first project > in VHDl programming, by using FPGA card, my project is about > monitoring cameras, and i didn't find any information about it, > basiclly i'm realy confused about starting this project > without any guides or information sources, it's my first > step trought materials and FPGA card, except some basic > tranings on it, i hope someone will help me to get what i need. There are many USB webcams available. That should be easier than interfacing to one with an analog output. But it depends a lot on what you want it to do. -- glenArticle: 154451
On Sunday, November 4, 2012 3:21:14 PM UTC, Andy Bartlett wrote: > "mehdi bousfiha" <el.mehdi.bousfiha@gmail.com> wrote in message > > news:fc33de64-691d-4193-ad81-dc7ed266e52f@googlegroups.com... > > > On Sunday, November 4, 2012 10:18:14 AM UTC, Andy Bartlett wrote: > > >> "mehdi bousfiha" <el.mehdi.bousfiha@gmail.com> wrote in message > > >> > > >> news:edbf8b3f-72af-4f9c-b170-b88283a28cc6@googlegroups.com... > > >> > > >> On Sunday, November 4, 2012 5:56:12 AM UTC, Robert Miles wrote: > > >> > > >> > On Saturday, November 3, 2012 9:00:50 PM UTC-5, mehdi bousfiha wrote: > > >> > > >> > > > >> > > >> > > On Sunday, November 4, 2012 1:14:23 AM UTC, mehdi bousfiha wrote: > > >> > > >> > > > >> > > >> > > > > >> > > >> > > > >> > > >> > > > Hi everyone, i'm realy excited about starting my first project in > > >> > > > VHDl > > >> > > >> > > > programming, by using FPGA card, my project is about monitoring > > >> > > >> > > > cameras, and i didn't find any information about it, basiclly i'm > > >> > > >> > > > realy confused about starting this project without any guides or > > >> > > >> > > > information sources, it's my first step trought materials and FPGA > > >> > > >> > > > card, except some basic tranings on it, i hope someone will help me > > >> > > > to > > >> > > >> > > > get what i need. > > >> > > >> > > > >> > > >> > > > > >> > > >> > > > >> > > >> > > > Thank you in advance. > > >> > > >> > > > >> > > >> > > > > >> > > >> > > > >> > > >> > > first of all thank you for your reply, > > >> > > >> > > > >> > > >> > > > > >> > > >> > > > >> > > >> > > My project is about surveillance camera, it means a camera that can > > >> > > >> > > stock a video, and only on a presence of mouvement, and after that we > > >> > > >> > > can display these sequence of videos on a LCD screen > > >> > > >> > > > >> > > >> > > > >> > > >> > > > >> > > >> > Is the wind blowing enough to move lightweight objects enough that it > > >> > > >> > should be displayed? > > >> > > >> > > >> > > >> >We suppose that the camera is inside a building, such details are far > > >> >from > > >> > > >> >what i want, i need the first steps > > >> > > >> > > >> > > >> OK one step at a time. > > >> > > >> > > >> > > >> What are the cameras you wish to use - are they analog or digital output? > > >> > > >> If they are analog then what format of video do they provide? > > >> > > >> If baseband then probably either RS170 or CCIR. You need to read up and > > >> > > >> understand these video formats, then you will need to build an Analog to > > >> > > >> digital converter to allow you to interface to the FPGA - how many > > >> bits? - > > >> > > >> you need to understand sampling theory to get a handle on the conversion > > >> > > >> rate you will need to preserve the analog bandwidth, and understand what > > >> > > >> level of quantization you will need. > > >> > > >> > > >> > > >> Having got the digitised input to the FPGA you will need to strip the > > >> sync > > >> > > >> pulses from it to allow you to form the images properly into some kind of > > >> > > >> frame store. You probably (almost certainly) will not have enough memory > > >> on > > >> > > >> the FPGA for a frame store, so you will need external memory. > > >> > > >> > > >> > > >> This will probably be DRAM or SDRAM. You need to define the devices your > > >> > > >> need, speed and capacity, and understand how to drive the memory devices > > >> > > >> from your FPGA. > > >> > > >> > > >> > > >> If the cameras are digital - what format - camera link? Ethernet? > > >> > > >> proprietary? > > >> > > >> > > >> > > >> We have not even scratched the surface yet. > > >> > > >> > > >> > > >> You need to do some background work and system design first before you > > >> even > > >> > > >> think about coding the FPGA. > > >> > > >> > > >> > > >> Just a few thoughts ... > > > > > > OK i see, So what are you suggestions for a beginner like me, i'm realy > > > excited about building my own project, and i'll work hard to realize that, > > > i juste need support and a push from professional people like you. > > > any ideas for easy projects ?? > > > > As rickman suggested earlier - perhaps a traffic light controller. > > > > You need to walk before you run - understand the fundamentals. > > > > Personally I would suggest:- > > > > 1) Flashing LED - say 1Hz, 500ms on, 500ms off based on your system clock. > > > > 2) A counter that drives a decoder/seven segment display, using your 1Hz > > output from 1) > > > > 3) A frequency counter - drives the seven segment decoder/display from 2) > > and measures the frequency from 1) > > > > When you have got that all going come back for some more help. > > > > Andy thank you very much :)Article: 154452
On 11/4/2012 8:31 AM, mehdi bousfiha wrote: > > OK i see, So what are you suggestions for a beginner like me, i'm realy excited about building my own project, and i'll work hard to realize that, i juste need support and a push from professional people like you. > any ideas for easy projects ?? The first thing I would suggest is that you trim your posts when you quote. There is no need to include the entire thread in every post and it makes it hard for others to read. Just quote the parts you are replying to. I gave you a suggestion on how to get started. How well do you know an HDL like VHDL or Verilog? Do you need to start with coding tutorials? Or are you past that point yet? RickArticle: 154453
Hello all I am facing a strange problem: I am not able to generate a properly working= bitstream from an original set of files that worked perfectly well just a = few days ago. I mean, the FPGA gets programmed OK but the design doesn't wo= rk. If I use last week's bitstream it works, if I generate a new one from l= ast week's source files it doesn't. I use ISE 13.1. Any clue or hint ? Thanks NicolasArticle: 154454
Le lundi 5 novembre 2012 11:53:53 UTC+1, nmat...@gmail.com a =E9crit=A0: > [...] If I use last week's bitstream it works, if I generate a new one fr= om > last week's source files it doesn't. Problem update (and partial solution) : there seems to be a conflict on the= serial PROM pins, the 3.3V regulator gets really hot. If I unplug the PROM= it works fine. NicolasArticle: 154455
On 11/05/2012 11:53 AM, nmatringe@gmail.com wrote: > Hello all > I am facing a strange problem: I am not able to generate a properly working bitstream from an original set of files that worked perfectly well just a few days ago. I mean, the FPGA gets programmed OK but the design doesn't work. If I use last week's bitstream it works, if I generate a new one from last week's source files it doesn't. > I use ISE 13.1. > Any clue or hint ? > > Thanks > Nicolas > Is your design fully constrained and does it meet all timing requirements? I remember having trouble once when removing or adding a debug pin gave a working/not working design. However, it was not exactly the same files. PereArticle: 154456
Le lundi 5 novembre 2012 14:08:20 UTC+1, o pere o a =E9crit=A0: > Is your design fully constrained and does it meet all timing=20 > requirements? I remember having trouble once when removing or adding a=20 > debug pin gave a working/not working design. However, it was not exactly= =20 > the same files. The pinout is fully defined and the max clock frequency exceeds the constra= int. As I added, there is something wrong with the serial PROM pins. My design d= oesn't use the dual-use pins (Din, Init_n & Busy) though. NicolasArticle: 154457
On Monday, November 5, 2012 4:53:53 AM UTC-6, nmat...@gmail.com wrote: > Hello all I am facing a strange problem: I am not able to generate a prop= erly working bitstream from an original set of files that worked perfectly = well just a few days ago. I mean, the FPGA gets programmed OK but the desig= n doesn't work. If I use last week's bitstream it works, if I generate a ne= w one from last week's source files it doesn't. I use ISE 13.1. Any clue or= hint ? Thanks Nicolas Are you absolutely, positively sure that what you are using as "last week's= source files" actually produced "last week's bitstream"? Including all pro= ject configuration/script files?=20 Was "last week's bitstream" created with a script, or was it just button-pu= shing in the GUI? Generating exact sequences of button-pushing is not very = repeatable. If it was a script, has the script changed?=20 Is or was the synthesis/P&R tool using incremental synthesis/P&R, or is/was= the build a "clean" build from scratch?=20 Is the same version of synthesis, P&R tools used? Given the issue with the PROM, I would look at the options that went into p= roducing the programming file first. AndyArticle: 154458
Le 05/11/2012 18:18, jonesandy@comcast.net a écrit : > On Monday, November 5, 2012 4:53:53 AM UTC-6, nmat...@gmail.com wrote: >> Hello all I am facing a strange problem: I am not able to generate a properly working bitstream from an original set of files that worked perfectly well just a few days ago. I mean, the FPGA gets programmed OK but the design doesn't work. If I use last week's bitstream it works, if I generate a new one from last week's source files it doesn't. I use ISE 13.1. Any clue or hint ? Thanks Nicolas > > Are you absolutely, positively sure that what you are using as "last week's source files" actually produced "last week's bitstream"? Well I retrieved a backed-up version of the directory, the files time & date seem to indicate that yes, the bitstream has been generated from the source files (VHDL, UCF and tcl script) > Was "last week's bitstream" created with a script, or was it just button-pushing in the GUI? It's a script called from a .bat command file. > Generating exact sequences of button-pushing is not very repeatable. If it was a script, has the script changed? The only difference between the runs is that the script sets a generic parameter based on time & date at runtime so that the design is time-stamped but it has never caused any such problem before. > Given the issue with the PROM, I would look at the options that went into producing the programming file first. I hadn't used the PROM on this project until I had a working design, and then I needed to test some USB issue and programmed the FPGA through JTAG with a slightly modified design and I ran into this pin conflict. I still don't know where it comes from. The pad report indicates that the dual-function pins are not used. CCLK pin ? NicolasArticle: 154459
Nicolas Matringe wrote: > Le 05/11/2012 18:18, jonesandy@comcast.net a écrit : >> On Monday, November 5, 2012 4:53:53 AM UTC-6, nmat...@gmail.com wrote: >>> Hello all I am facing a strange problem: I am not able to generate a >>> properly working bitstream from an original set of files that worked >>> perfectly well just a few days ago. I mean, the FPGA gets programmed >>> OK but the design doesn't work. If I use last week's bitstream it >>> works, if I generate a new one from last week's source files it >>> doesn't. I use ISE 13.1. Any clue or hint ? Thanks Nicolas >> >> Are you absolutely, positively sure that what you are using as "last >> week's source files" actually produced "last week's bitstream"? > > Well I retrieved a backed-up version of the directory, the files time & > date seem to indicate that yes, the bitstream has been generated from > the source files (VHDL, UCF and tcl script) > > >> Was "last week's bitstream" created with a script, or was it just >> button-pushing in the GUI? > > It's a script called from a .bat command file. > > >> Generating exact sequences of button-pushing is not very repeatable. >> If it was a script, has the script changed? > > The only difference between the runs is that the script sets a generic > parameter based on time & date at runtime so that the design is > time-stamped but it has never caused any such problem before. > > >> Given the issue with the PROM, I would look at the options that went >> into producing the programming file first. > > I hadn't used the PROM on this project until I had a working design, and > then I needed to test some USB issue and programmed the FPGA through > JTAG with a slightly modified design and I ran into this pin conflict. I > still don't know where it comes from. The pad report indicates that the > dual-function pins are not used. CCLK pin ? > > Nicolas What's the setting for unused IOB's when you run BitGen? I seem to remember that active low drive (not pulldown) is one of the options. -- GaborArticle: 154460
in my pc there is a DB with songs and i want to send/ transmit using RTP real time protocol to different devices so I want send media over RTP/UDP/IP using fpgasArticle: 154461
On Monday, November 5, 2012 3:55:15 PM UTC-7, Emil Imrith wrote: > in my pc there is a DB with songs and i want to send/ transmit using RTP real time protocol to different devices so I want send media over RTP/UDP/IP using fpgas I have the understanding of the RTP header and I know there so ip libraries for ethernet networking so I want to descript a hardware to transmit my media probably I will need an encoder within ?Article: 154462
Le 05/11/2012 20:43, Gabor a écrit : > What's the setting for unused IOB's when you run BitGen? I seem to > remember that active low drive (not pulldown) is one of the options. That was a default setting that stung me several times in the past. But Xilinx have finally changed it to something else, like "pulled low". I checked that too (but will recheck anyway) NicolasArticle: 154463
i know VHDL, and i do know how to code with it, but i still need more mini project on VHDL programmingArticle: 154464
mehdi bousfiha wrote: > i know VHDL, and i do know how to code with it, but i still need more mini project on VHDL programming > http://www.amazon.com/FPGA-Prototyping-VHDL-Examples-Spartan-3/dp/0470185317Article: 154465
Emil Imrith <emrith@gmail.com> writes: > in my pc there is a DB with songs and i want to send/ transmit using RTP real time protocol to different devices so I want send media over RTP/UDP/IP using fpgas Why do you want to use an FPGA for this? Unless you *need* an FPGA, I'd avoid it... http://electronics.stackexchange.com/questions/45466/compare-implementing-a-simple-automation-design-on-a-mcu-vs-an-fpga-cpld/45474#45474 Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 154466
On Mon, 5 Nov 2012 21:12:30 -0800 (PST) mehdi bousfiha <el.mehdi.bousfiha@gmail.com> wrote: > i know VHDL, and i do know how to code with it, but i still need more mini project on VHDL programming Andy Bartlett suggested 3 excellent ones for you. Is there some specific problem with his suggestions, or have you simply already finished them? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 154467
On 11/5/2012 5:57 PM, Emil Imrith wrote: > On Monday, November 5, 2012 3:55:15 PM UTC-7, Emil Imrith wrote: >> in my pc there is a DB with songs and i want to send/ transmit using RTP real time protocol to different devices so I want send media over RTP/UDP/IP using fpgas > > > > I have the understanding of the RTP header > and I know there so ip libraries for ethernet networking > so I want to descript a hardware to transmit my media > probably I will need an encoder within ? Why not use a wire? They are low power and very inexpensive. They don't require any coding either. If you are talking about generating the RTP protocol, why not do that in software in your PC? Isn't that where the music data base is? How would you get the music into the FPGA? RickArticle: 154468
I use the MachXO2=99-1200ZE Breakout Board. I noticed that independent programmers for the FPGA (LCMXO2-1200ZE) are expensive. Is it possible to bridge wires from the Demo board to an external board to program chip on that board. Instructions? Where is this mentioned in the documentation. The schematic diagram is quite unclear.Article: 154469
A PCI Express master (a "root complex") generates a 100 MHz reference clock to target devices. In some cases that we've observed, the master (in this case, an AMI based motherboard) ramps the clock down to 12.5 MHz, in apparently a smooth transition, like a PLL being cranked down. We can find no reference as to when, and why, the ref clock would be stepped down in frequency, or what might bring it back up. Does anybody know anything about this? -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulationArticle: 154470
On 7 Nov., 21:26, John Larkin <jlar...@highlandtechnology.com> wrote: > A PCI Express master (a "root complex") generates a 100 MHz reference > clock to target devices. In some cases that we've observed, the master > (in this case, an AMI based motherboard) ramps the clock down to 12.5 > MHz, in apparently a smooth transition, like a PLL being cranked down. > > We can find no reference as to when, and why, the ref clock would be > stepped down in frequency, or what might bring it back up. Does > anybody know anything about this? > got to do with Active State Power Management (ASPM) ? http://www.intel.com/content/www/us/en/io/pci-express/pci-express-architecture-power-management-rev-1-1-paper.html -LasseArticle: 154471
On Wed, 7 Nov 2012 13:41:30 -0800 (PST), "langwadt@fonz.dk" <langwadt@fonz.dk> wrote: >On 7 Nov., 21:26, John Larkin <jlar...@highlandtechnology.com> wrote: >> A PCI Express master (a "root complex") generates a 100 MHz reference >> clock to target devices. In some cases that we've observed, the master >> (in this case, an AMI based motherboard) ramps the clock down to 12.5 >> MHz, in apparently a smooth transition, like a PLL being cranked down. >> >> We can find no reference as to when, and why, the ref clock would be >> stepped down in frequency, or what might bring it back up. Does >> anybody know anything about this? >> > >got to do with Active State Power Management (ASPM) ? > >http://www.intel.com/content/www/us/en/io/pci-express/pci-express-architecture-power-management-rev-1-1-paper.html > >-Lasse Intel (and all the other references we can find) talks about "removing" the clock in shutdown states, to save power. It looks like only the AMD chipset ramps it down to about 12 MHz in the L1 powerdown state. That's weird, and we can't find any mention of it anywhere. Maybe this keeps the coupling caps halfway charged up and speeds return to operating states. Or something. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulationArticle: 154472
On Sunday, November 4, 2012 4:40:12 AM UTC+1, rickman wrote: > What is the lowest power design you have done in an FPGA or CPLD? There > > have been some very low power devices on the market for a number of > > years now. I assume there have been some designs that push the power > > consumption to new lows in various "zero power" parts. > > > > What design did you do that was very power sensitive, what parts did you > > use and how low did you get your power consumption? > > > > Did you use any special tricks to get the power lower than you thought > > possible? Were you able to meet the goals you estimated before you did > > the design? In other words, any surprises? > > > > Did you learn any limitations of the parts in what you could do in low > > power modes? Features you couldn't use or ways the parts didn't work as > > well as expected? > > > > One thing that has occurred to me is that many RAM based parts have to > > be configured. This often takes a fair amount of power that might be a > > lot more than zero. Is there any way to stretch this out so the rate of > > configuration reduces the power level? > > > > Rick Flash-based FPGAs consume less than SRAM-based FPGAs. A few examples are Igloo and SmartFusion2 from Microsemi. I think dynamic power is about the same, but static power is close to zero and configuration power is zero (because they retain the configuration when powered down!) TullioArticle: 154473
On 11/8/2012 12:20 PM, tullio wrote: > On Sunday, November 4, 2012 4:40:12 AM UTC+1, rickman wrote: >> What is the lowest power design you have done in an FPGA or CPLD? There >> have been some very low power devices on the market for a number of >> years now. I assume there have been some designs that push the power >> consumption to new lows in various "zero power" parts. >> >> What design did you do that was very power sensitive, what parts did you >> use and how low did you get your power consumption? >> >> Did you use any special tricks to get the power lower than you thought >> possible? Were you able to meet the goals you estimated before you did >> the design? In other words, any surprises? >> >> Did you learn any limitations of the parts in what you could do in low >> power modes? Features you couldn't use or ways the parts didn't work as >> well as expected? >> >> One thing that has occurred to me is that many RAM based parts have to >> be configured. This often takes a fair amount of power that might be a >> lot more than zero. Is there any way to stretch this out so the rate of >> configuration reduces the power level? >> >> Rick > > > Flash-based FPGAs consume less than SRAM-based FPGAs. > A few examples are Igloo and SmartFusion2 from Microsemi. > I think dynamic power is about the same, but static power is close to zero and configuration power is zero (because they retain the configuration when powered down!) > > Tullio Posting through Google I see... double spacing needs to be trimmed out of quotes with them. I don't know where you got your info on power consumption. Power consumption depends on many other things than just RAM vs Flash. I don't know of any FPGA type devices that are as low power as the iCE40 from Lattice. They have static power down to 19 uA and very low dynamic power. I haven't seen any figures from the Igloo that make me think they have lower power than this. Do you have dynamic power figures for the Igloo parts? RickArticle: 154474
On Sun, 04 Nov 2012 15:21:16 +0000, Andy Bartlett wrote: > "mehdi bousfiha" <el.mehdi.bousfiha@gmail.com> wrote in message > news:fc33de64-691d-4193-ad81-dc7ed266e52f@googlegroups.com... >> On Sunday, November 4, 2012 10:18:14 AM UTC, Andy Bartlett wrote: >>> "mehdi bousfiha" <el.mehdi.bousfiha@gmail.com> wrote in message >>> >>> news:edbf8b3f-72af-4f9c-b170-b88283a28cc6@googlegroups.com... >>> >>> On Sunday, November 4, 2012 5:56:12 AM UTC, Robert Miles wrote: >>> >>> > On Saturday, November 3, 2012 9:00:50 PM UTC-5, mehdi bousfiha >>> > wrote: >>> >>> >>> > >>> > > On Sunday, November 4, 2012 1:14:23 AM UTC, mehdi bousfiha wrote: >>> >>> >>> > >>> >>> > > >>> >>> > >>> > > > Hi everyone, i'm realy excited about starting my first project >>> > > > in VHDl >>> >>> > > > programming, by using FPGA card, my project is about monitoring >>> >>> > > > cameras, and i didn't find any information about it, basiclly >>> > > > i'm >>> >>> > > > realy confused about starting this project without any guides or >>> >>> > > > information sources, it's my first step trought materials and >>> > > > FPGA >>> >>> > > > card, except some basic tranings on it, i hope someone will help >>> > > > me to >>> >>> > > > get what i need. >>> >>> >>> > >>> >>> > > >>> >>> > >>> > > > Thank you in advance. >>> >>> >>> > >>> >>> > > >>> >>> > >>> > > first of all thank you for your reply, >>> >>> >>> > >>> >>> > > >>> >>> > >>> > > My project is about surveillance camera, it means a camera that >>> > > can >>> >>> > > stock a video, and only on a presence of mouvement, and after that >>> > > we >>> >>> > > can display these sequence of videos on a LCD screen >>> >>> >>> > >>> >>> > >>> >>> > >>> > Is the wind blowing enough to move lightweight objects enough that >>> > it >>> >>> > should be displayed? >>> >>> >>> >>> >We suppose that the camera is inside a building, such details are far >>> >from >>> >>> >what i want, i need the first steps >>> >>> >>> >>> OK one step at a time. >>> >>> >>> >>> What are the cameras you wish to use - are they analog or digital >>> output? >>> >>> If they are analog then what format of video do they provide? >>> >>> If baseband then probably either RS170 or CCIR. You need to read up >>> and >>> >>> understand these video formats, then you will need to build an Analog >>> to >>> >>> digital converter to allow you to interface to the FPGA - how many >>> bits? - >>> >>> you need to understand sampling theory to get a handle on the >>> conversion >>> >>> rate you will need to preserve the analog bandwidth, and understand >>> what >>> >>> level of quantization you will need. >>> >>> >>> >>> Having got the digitised input to the FPGA you will need to strip the >>> sync >>> >>> pulses from it to allow you to form the images properly into some kind >>> of >>> >>> frame store. You probably (almost certainly) will not have enough >>> memory on >>> >>> the FPGA for a frame store, so you will need external memory. >>> >>> >>> >>> This will probably be DRAM or SDRAM. You need to define the devices >>> your >>> >>> need, speed and capacity, and understand how to drive the memory >>> devices >>> >>> from your FPGA. >>> >>> >>> >>> If the cameras are digital - what format - camera link? Ethernet? >>> >>> proprietary? >>> >>> >>> >>> We have not even scratched the surface yet. >>> >>> >>> >>> You need to do some background work and system design first before you >>> even >>> >>> think about coding the FPGA. >>> >>> >>> >>> Just a few thoughts ... >> >> OK i see, So what are you suggestions for a beginner like me, i'm realy >> excited about building my own project, and i'll work hard to realize >> that, >> i juste need support and a push from professional people like you. >> any ideas for easy projects ?? > > As rickman suggested earlier - perhaps a traffic light controller. > > You need to walk before you run - understand the fundamentals. > > Personally I would suggest:- > > 1) Flashing LED - say 1Hz, 500ms on, 500ms off based on your system > clock. > > 2) A counter that drives a decoder/seven segment display, using your 1Hz > output from 1) > > 3) A frequency counter - drives the seven segment decoder/display from > 2) and measures the frequency from 1) > > When you have got that all going come back for some more help. > > Andy After you get that done, if you're still interested in the motion detection problem, then make a video generator that generates some simple scene (horizontal or vertical bars are good, or a checkerboard) and shows it on your LCD. Once you've got that code nailed down, then work on interfacing memory to your FPGA. This isn't trivial, so don't be surprised if it's hard. Making sure you have the bandwidth to read in one frame buffer from a camera while you read out another to a screen is harder. When you can write a test pattern into RAM then read it back bit-correct, fast enough to do video, then proceed. Then, define some frame buffers in RAM, and make code that displays a frame buffer from RAM on your LCD screen. In an ideal world this will just be glue between the two things you've done already; in the real world a beginner may find himself re-writing something. Once that works, then tackle reading from the camera into a frame buffer at the same time that you're reading out from a frame buffer to the LCD. Success will be measured when you can wave your hand in front of the camera and see it on the screen, perhaps delayed by a frame or two. At this point, you'll be a lot less of a beginner than you are now. Finally, you can then start trying to implement motion detection algorithms. Have fun -- it ain't easy. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com
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