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Yes. But, you can always simulate it, and find out where to put the stub, and how bad it looks. Austin newman wrote: > > > > The DCM will have feed back from the middle on the PCB trace, > > > > for delay compensation. > > > > > > Do you think the creation of a trace stub from the feedback from the > middle of the PCB trace will mess up the clock signal integrity? > > NewmanArticle: 39276
Could somebody tell me please why all of you seem to prefer those large Xilinx and Altera devices. From my point of view 80% of all applications do not require larger devices than 16V8 or 20V8. I never used a device larger than the 22V10 I I canīt think of an application which would require a bigger device. BTW, Lattice rules!! Furthermore, I really must say that VHDL and Verilog is bullsh...! Why not use CUPL. Thatīs much better to describe hardware!!Article: 39277
If all I wanted was a sea of small devices to accomplish my functionality, I wouldn't have to get into the larger devices. Ever try to do an FFT with GALs? The functionality required in most designs involve tens/hundreds of thousands of gates, not dozens. I can hardly think of an application for a single 22V10 except for the rare glue logic between devices that already have the high functionality (rarely flexble) built in. ls_user wrote: > Could somebody tell me please why all of you seem to prefer those large Xilinx and Altera devices. From my point of view 80% of all applications do not require larger devices than 16V8 or 20V8. I never used a device larger than the 22V10 I I canīt think of an application which would require a bigger device. BTW, Lattice rules!! Furthermore, I really must say that VHDL and Verilog is bullsh...! Why not use CUPL. Thatīs much better to describe hardware!!Article: 39278
Thank you, John. But: What is a FFT. Why should I wnat to implement something what I do not know? I can do everything I could imagine by using 16V8s and 20V8s and I believe most of you guys could do the same. However, it seems to be the trend to use larger devices. My believe is that most people use large FPGAs and leave all the not used area free. All of them could use 16V8s and save a lot of money. I just want my applications to be functional and have the lowest device cost. Poor stupid FPGA users!Article: 39279
Ciao I really must say that you are right! I was using a Virtex device to implement a counter. I spent a lot of time and couldnīt achieve the requested timing. It is much easier to go on with GALīs or PALīs and have a little bit relaxed performance but fast place&route times and no stress at all! FPGAs suck!Article: 39280
"ls_user" <ls@swissonline.ch> schrieb im Newsbeitrag news:ee74ad1.1@WebX.sUN8CHnE... > Thank you, John. But: What is a FFT. Fast Fourier Transformation. Converts a signal into its frequency representation. You mobile phone does this. Your MP3 player too (ok, the inverse of this) >Why should I wnat to implement something what I do not know? So you better seek out and learn. > I can do everything I could imagine by using 16V8s and 20V8s and I believe most of you guys could do the same. However, it seems to be the trend to use Then your imagination is weak. Get inspired . . > larger devices. My believe is that most people use large FPGAs and leave all the not used area free. All of them could use 16V8s and save a lot of money. I just You are wrong. > want my applications to be functional and have the lowest device cost. Poor stupid FPGA users! Now its, clear. GET LOST, TROLL. -- Nevertheless with kind Regards FalkArticle: 39281
"Antonio" <dottavio@ised.it> schrieb im Newsbeitrag news:ee74ad1.2@WebX.sUN8CHnE... > Ciao > > I really must say that you are right! I was using a Virtex device to implement a counter. I spent a lot of time and couldnīt achieve the requested timing. It is much easier to go on with GALīs or PALīs and have a little bit relaxed performance but fast place&route times and no stress at all! FPGAs suck! Is there a smily missing? Such comments from YOU? Hmm, if this is not a joke, then you are really a small, lazy JAVA programmer who wants to be an FPGA specialist overnight. Get alife, boy. -- Regards FalkArticle: 39282
rickman wrote: > > I checked your web site over the weekend and found that you do support > the AVR and use the Atmel eval board with an ATmega103 which I believe > is somewhat similar to the chip I am evaluating, the ATmega64/128. > > However, this chip and even the eval board are on the list of "older > tools" and parts. In fact, the ATmega103 is "not recommeded for new > designs". I see that Atmel has a newer STK500 which can support all of > the newer chips. How likely is it that Forth, Inc will bundle SwiftX > with this newer board instead of the older board? Yes, we support the STK500. It's a somewhat more cumbersome environment than the STK200 and STK300, though, because it requires the use of Atmel's tools to download code to flash, whereas the older boards can be entirely supported from within the SwiftX environment. Cheers, Elizabeth -- ================================================== Elizabeth D. Rather (US & Canada) 800-55-FORTH FORTH Inc. +1 310-491-3356 5155 W. Rosecrans Ave. #1018 Fax: +1 310-978-9454 Hawthorne, CA 90250 http://www.forth.com "Forth-based products and Services for real-time applications since 1973." ==================================================Article: 39283
I have to say.... both your posts have set me laughing. You are really good joker! To the topics - everyone can use devices that he wants. I do for example some signal and video processing. I'd never want to do it using tons of 16V8s and CUPL:)))))))) Jan "ls_user" <ls@swissonline.ch> wrote in message news:ee74ad1.1@WebX.sUN8CHnE... > Thank you, John. But: What is a FFT. Why should I wnat to implement something what I do not know? I can do everything I could imagine by using 16V8s and 20V8s and I believe most of you guys could do the same. However, it seems to be the trend to use larger devices. My believe is that most people use large FPGAs and leave all the not used area free. All of them could use 16V8s and save a lot of money. I just want my applications to be functional and have the lowest device cost. Poor stupid FPGA users!Article: 39284
I really do not know what is wrong with you guys. Why donīt you just admit that 80% of your applications could be implemented by using 16V8s? I believe a very intelligent guy like Ray Andraka could fill up a ispLSI1032 (have you seen all that complicated stuff on his web page??). But: most of you guys?? Be serios with me, please!! I mean, you guys use a Spartan or even Virtex part and leave 99% of the resources free, donīt you? Then you sell the application and claim that you have spend weeks or month to fill it up. Honest engineers like me do only charge the real work they have done. And this usually fits into a 16V8 and sometimes into a 20V8 and for real big stuff into a 22V10. Why donīt you just admit that I am right? And: What do you want to tell me about MP3 players and so. I mean, I can buy a MP3 player at Freys or so and nobody really develops that complicated stuff himself. This usually is the hard work of multiple engineers at Sony or so.Article: 39285
Rick Lyons wrote:
>
> ...
>
> That original post just sounded fishy.
> Can you imagine someone saying, "I want
> solution manuals to textbooks. I don't
> care which books, just help me get
> solutions manuals." Just doesn't sound
> kosher. The solutions manuals I've seen
> contain answers, but not the questions.
> Now tell me, just exactly how the heck are ya'
> gonna tell if a book is useful by looking at
> the algebraic answers to homework problems.
>
...
>
> [-Rick-]
Be fair! As I read the original question, my impression was that he
wanted to know of any algorithm texts for which an answer manual is
available. If there is one, he wants it for self study. I don't leave my
car keys in the ignition when I park, but I don't assume that every
passerby is a thief. I should have thought to tell him that many texts
have answers to, say, odd-numbered problems.
Jerry
--
Besides a mathematical inclination, an exceptionally good mastery of
one's native tongue is the most vital asset of a competent programmer.
Edsger W. Dijkstra
-----------------------------------------------------------------------
Article: 39286Amateur, For real amusement, leave it to the professionals. For the best in professional satire, http://www.satirewire.com/features/siliconpines/acf.shtml Austin ls_user wrote: > I really do not know what is wrong with you guys. Why donīt you just admit that 80% of your applications could be implemented by using 16V8s? I believe a very intelligent guy like Ray Andraka could fill up a ispLSI1032 (have you seen all that complicated stuff on his web page??). But: most of you guys?? Be serios with me, please!! I mean, you guys use a Spartan or even Virtex part and leave 99% of the resources free, donīt you? Then you sell the application and claim that you have spend weeks or month to fill it up. Honest engineers like me do only charge the real work they have done. And this usually fits into a 16V8 and sometimes into a 20V8 and for real big stuff into a 22V10. Why donīt you just admit that I am right? > > And: What do you want to tell me about MP3 players and so. I mean, I can buy a MP3 player at Freys or so and nobody really develops that complicated stuff himself. This usually is the hard work of multiple engineers at Sony or so.Article: 39287
I'm a 3rd year engineering student who is trying to implement an Associative List Memory (ALM) algorithm on an FPGA (see Neural Networks Vol 10 No.6 pp1117-1131, 1997). I have no experience of using FPGA's and have had to teach myself VHDL. I was wondering if some experienced ASIC/FPGA engineers could give me an idea how long it takes to implement Algorithms on an FPGA. I know the development time varies with algorithm complexity but some 'ball-park' figures would be useful along with the algorithm implemented. It would really help my final report to have an idea of how long an experienced engineer requires to do this kind of task. Any help on this matter would be appreciated, mail me directly if preferred and thanks in advance. Dan.Article: 39288
Austin: Very funny!Article: 39289
thomas.stanka@tesat.de (Thomas Stanka) writes: > Hi all, > > Arvin Patel <apatel@chello.no> wrote: > > > Does anyone have any experience with the latest version of > > Xilinx XST? I would be interested in any comments on stability > > of the tool and of the quality of results. > > Interessting point. We do the same test (as all abround the world I guess) > since FE-lizence is no longer included in Xilinx. I will post, wehn we > have results. > > > Does anyone have any comparisons of XST and Synopsys FPGA Express? > > I have made some tests and it seems that XST gives slightly > > better timing results than FPGA Express. > > Do you mean after PAR your bitfile is faster, or is it just, that you get > better timing values after synthesis which results in equivalent results > after PAR? > > bye Thomas > > -- > Thomas Stanka TE/EMD4 > Space Communications Systems > Tesat Spacecom GmbH & Co KG > thomas.stanka@tesat.de Actually we obtained better results after PAR (I don't regard the FE timing report as very a good estimate). In one case almost 30% improvement. ArvinArticle: 39290
ls_user wrote: > And: What do you want to tell me about MP3 players and so. I mean, I can buy a MP3 player at Freys or so and nobody really develops that complicated stuff himself. This usually is the hard work of multiple engineers at Sony or so. ROTFL :) FPGA-based MP3 decoder is going to be my graduate project :) -=Czaj-nick=-Article: 39291
It's a TROLL, don't encourage it.Article: 39292
next time i will tell you something about 74LS00īs. Will get some of you with that as well. have a nice eveningArticle: 39293
Austin, Peter, Thanks, now I just I have to convince my colleagues that It'll work :) -Lasse Austin Lesea wrote: > > Lasse, > > (From the cube down the hall), if the clock signal comes from the same > DCM, then the arrival time at the other end of the two BUFGs to the same > IOB (for example) is +/- 10 ps (basically we can't measure it). Now the > DCM has some error for its two outputs (say CLK0 and CLK180) of a tap > value (~60ps). > > Any individual BUFG is from 0 to 120 ps in a 2V6000, and from 0 to 100 > ps in a 2V4000 or 2V3000, and from 0 to 60 ps in a 2V1000. > > I would expect the worst case skew from any DCM driving a BUFG to any > IOB receiving the BUFG to be less than the total skew of one BUFG, as > they can't really add together, as they are both always greater than 0, > and increasing. If they are both increasing together, then the skew > might be 0. Skews/delays to CLBs are less or equal to skew to IOBs > (they are closer). > > Austin > > Lasse Langwadt Christensen wrote: > > > I'm about to build an ASIC prototype in a Virtex2, > > The design has several clk domains, all the same > > frequency (24Mhz) but separately gated, I'd rather > > not change too much in the design to get it a working > > fpga protype so, > > if I use the clk gating in Virtex2 to replace the > > gating in design will I be guaranteed that all the > > clks will be aligned? > > > > thanks, > > --Lasse > > ---------------------------- > > - Lasse Langwadt Christensen > > - Aalborg - Danmark -- ---------------------------- - Lasse Langwadt Christensen - Aalborg - DanmarkArticle: 39294
Hi, A friend asked me a question and perhaps someone out there can help. There was a Xilinx 4036XL hooked up to an SDRAM (no, he didn't know what manufacturer and model) and the claim was that groundbounce in the FPGA from SSO's caused the SDRAM to latchup; this was supposed to explain a functional failure that would be cleared by cycling the power. That sounds a bit odd to me, although I haven't used SDRAM and am not familiar with their details. For a low, quiet output, they measured a 710 mV peak below ground; that doesn't sound too bad, about a diode drop. Again, I don't know what's going on inside SDRAM technology so I thought I'd ask and see if anyone has any experience with this. Thanks in advance, -- Just an OldEngineerArticle: 39295
I'm investigating ways of improving my development throughput. At the moment I'm using Leonardo Altera Edition for synthesis, Altera Quartus 2 for P&R and Quartus 2's simulator. Targeting Apex 20KE600-1X devices I'm using an Athlon 1GHz with 512MB RAM. I'm in the middle of a project and am finding that as the design comes together, compilation and more especially simulation is becoming a real problem. I realise that the most positive step may be to either use the Modelsim Altera edition or invest in a full Modelsim license. The problem is that Modelsim does appear somewhat more cryptic than using Alteras offering. Plus I'm mid-project so changing from my *.vwf approach to modelsim may take time I haven't got. :) What I'd like is a) How much better is Modelsim than Altera's own simulator especially for post layout analysis. Since that's like asking about string length, I'd accept anecdotal evidence based on your own designs :Ž) b) Are full versions of Modelsim that much faster than the Altera edition. c) I've been toying with getting a 2GHz P4 or an AMD 1900+ or even a dual processor rig. (With 1Gb RAM). Does performance scale well (i.e. CPU bound or memory bandwidth bound) and does an MP setup provide any noticeable improvement or are all tools resolutely single threaded. d) Any other suggestions. I am already trying as best I can to restructure testing to minimise the issues, but these 10 hour simulation times (when it doesn't crash) are really non-productive. Paul Background on the design, though probably of limited additional help: Typically my designs use a lot of EABs as FIFOs, a lot of 32bit register moving about and various high speed memory interfaces 120MHz SDRAM x 2 on each chip. Logic is relatively simple and I believe I've taken enough pipelining precautions to limit routing problems. I'm trying to simulate passing message packets in, processing them, storing them, acting upon them etc. To capture a large part of this as the system comes together I'm finding I need simulations of up to 10ms (though 1ms is more typical). I've simulated at individual block level, so its really only the last level of testing thatArticle: 39296
--------------472B2B391712B18C28D08B3A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit RK, The concern is that if you inject enough current below ground, and forward bias the parasitic SCR structure, you may cause latchup. A few years ago we were really worried about this for 4K (a customer had done no signal integrity engineering, and created an SI nightmare for his company), so we wired 128 outputs through 1 foot of transmssion lines (50 ohm coax) to 128 inputs in order to provide the horrendous overshoot and undershoot required. We were slamming > 20 mA on each and every pin, both above 3.3 Vdc and below 0.0 V by as much as .71 volts (after all, the diode is clamping as hard as it can, so voltage doesn't tell you anything at all--you need to know the current). No problem. It seems that to trigger the SCR latchup, it requires a steady currents for many tens of nanoseconds, at currents greater than 300 mA for the entire edge, at a voltage above or below ground by a diode drop. These tests were done on 4Kxl and 4Kxla, which had almost identical 0.35u IO transistor structures. Bottom line, don't do that! Even if the design doesn't latch up, it will have incredible jitter, and probably have other problems caused by all of that ground bounce. Any voltage that causes the diodes to be forward biased is going to lead to problems, one way or another. As "just an old engineer" you should be familiar with signal integrity from the days when being an engineer meant you knew what Ldi/dt meant, and knew how to calculate the voltage at the end of a transmission line. Now latching up the SDRAM might well be possible (maybe they didn't have time to characterize the parasitic SCR structure, or to control the alphas of the npnp stucture), but don't blame the FPGA! If you hit it with a hammer, it would break, too. Is it the hammer's fault? Austin rk wrote: > Hi, > > A friend asked me a question and perhaps someone out there can help. There > was a Xilinx 4036XL hooked up to an SDRAM (no, he didn't know what > manufacturer and model) and the claim was that groundbounce in the FPGA > from SSO's caused the SDRAM to latchup; this was supposed to explain a > functional failure that would be cleared by cycling the power. > > That sounds a bit odd to me, although I haven't used SDRAM and am not > familiar with their details. For a low, quiet output, they measured a 710 > mV peak below ground; that doesn't sound too bad, about a diode drop. > Again, I don't know what's going on inside SDRAM technology so I thought > I'd ask and see if anyone has any experience with this. > > Thanks in advance, > > -- > Just an OldEngineerArticle: 39297
Why use one device when I can populate my board with 67 off 22V10 because: a) we know the risks with them (20 yr experience) b) you can program exactly what you want into the device and it will be exactly as you asked. None of this synthesis and fangled logic optimisation. c) We have a lot of expertise with them d) Because of the experience we are sure they are much more reliable. (Never mind the fact you've soldered 67 devices to a board.) e) JTAG programming is problematic. Give me a good PROM any day. Can use my old reliable programmer. And if you think I'm having a laugh, these were the exact reasons given by someone to me when I remarked on his 67 22V10 brand new board design. Paul "ls_user" <ls@swissonline.ch> wrote in message news:ee74ad1.-1@WebX.sUN8CHnE... > Could somebody tell me please why all of you seem to prefer those large Xilinx and Altera devices. From my point of view 80% of all applications do not require larger devices than 16V8 or 20V8. I never used a device larger than the 22V10 I I canīt think of an application which would require a bigger device. BTW, Lattice rules!! Furthermore, I really must say that VHDL and Verilog is bullsh...! Why not use CUPL. Thatīs much better to describe hardware!!Article: 39298
Hi, just scored some used, but reusable EPM7064 gate arrays that I would like to use in some home projects. Unfortunately they are NOT "in circuit programmable" and require a seperate programmer. The Altera web site has no details on programming these devices, but do have free software for circuit entry etc. Can a programmer be built by me for these parts (I don't need high speed or flexibility)? Obviously my budget doesn't allow for a bought one - unless extremely cheap (few 10s of $), else I'd just buy one. Does anyone know where programming details can be found? Surely such details are freely available! My return address has been corrupted. To reply either remove the 'xxx', or reply to the group, or email james.fenech (at) nec.com.au Thanks, James.Article: 39299
Why don't you give it a rough cut, then synth, and P&R and see what you get. If you're a designer of similar caliber to some of the regular posters on here then you should have a good shot at it. We run our ECC SDRAM interface at 25MHz, but then again, its a standard cell design being proto'd in a Vertex 2 6000, not a purpose build FPGA design. Ray Andraka <ray@andraka.com> wrote in message news:<3C5EB370.4BF9C1B8@andraka.com>... > Venu wrote: > > > Hi, > > > > I am planning to implement a SDRAM Controller to run at 133MHz and I am > > targetting Virtex-II device. It would be of great help to me if people > > can let me know their experiences in this regard . More specifically I > > am looking for some inputs on the following: > > > > a) Is this freq of 133MHZ for SDRAM Controller easily achievable in a Virtex-II > > device > > Should be very easy to hit 133 Hz in VII. Of course, it depends on your design > expertise, which is why I said "should" not "is". > > > > > b) What is the Max frequency that Xilinx claims in their application-notes > > for SDRAM Controller using Virtex-II > > > > Thanks > > Venu > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759
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