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Messages from 44100

Article: 44100
Subject: Re: 20,000 gates?
From: "Roger King" <roger@king.com>
Date: Tue, 11 Jun 2002 23:37:53 GMT
Links: << >>  << T >>  << A >>
I don't have the info, but what about the XC2S50 chip/family?

and is that a good number?



"Peter Alfke" <Peter.Alfke@xilinx.com> wrote in message
news:3D068771.DCD64D62@xilinx.com...
> Watch out for CLB-count.
> One CLB had 2 LUTs/flip-flops in XC4000,
> then four of them in Virtex,
> and now eight LUTs/flip/flops in Virtex-II.
> There are architectural reasons for these changes, but they make CLB count
> meaningless, unless you specify the family.
> Peter Alfke
>
> Roger King wrote:
>
> > Ok, let me give you a better statistic, 384 CLBs? 384 sounds like a
really
> > low number, it looks like I can only develop extremely simple projects.
> >
> > "Roger King" <roger@king.com> wrote in message
> > news:CUmN8.248826$ah_.140060@news01.bloor.is.net.cable.rogers.com...
> > > Is 20,000 gates enough for creating a nice project? What are some
projects
> > > one can create by using 20,000 gates? I am trying to decide if 20,000
> > gates
> > > fpga board would be sufficient for a hobbyist that wants to use it for
> > about
> > > 2 years.
> > >
> > > I have another question. How many megs of RAM will I be able to
develop
> > > using 20,000 gates fpga? I mean if I want to use the fpga as a ram.
> > >
> > >
> > >
> > >
>



Article: 44101
Subject: Synopsys, Spartan2, and Viewsim...
From: ebrunvand@hotmail.com (Erik Brunvand)
Date: 11 Jun 2002 16:47:00 -0700
Links: << >>  << T >>  << A >>
Hi - 

I'm trying to synthesize a circuit from VHDL using Synopsys, and read
the result back into Powerview Viewsim. What a frustrating experience!

Here's what's happening: 

- The spartan2 synthesis from synopsys is synthesizing in terms of
LUTs. I'm using the xfpga_spartan2_6 libraries, and the virtex dw
libraries.

- For some of the LUTs (the ones it calls DWLUT2_L), things are fine.
The generated edif netlist file has INIT and EQN attributes that
define what the initial value of the LUT is, and with a suitable
translation from INIT to @INIT using the edifatts.cfg file, viewsim
(and more importantly vsm) recognizes the @INIT attribute and
everything simulates fine

- BUT, for other LUTs (the ones it calls LUT2, LUT3, and LUT4), I
don't get INIT and EQN attributes in the EDIF file, instead I get a
"lut_function" atribute which is a string that describes the logic
function that should go into the LUT. It appears that viewsim/vsm has
no idea how to interpert this string into an INIT string (i.e. convert
the logic function into bits of the LUT). I have NO idea why some LUTs
are being treated differently than other LUTs in terms of which
attributes are being generated. Is it a DW vs. syn issue in Synopsys?
In any case, I'm stymied.

Does anyone have a solution for this? Likely solutions (that I haven't
been able to find) might be to force Synopsys to generate INIT and EQN
for all LUT cells, to post-process the EDIF file to expand the
lut_function string into an @INIT string, to force vsm to interpert
the lut_function, or even to go through some other tool that reads the
lut_function-style EDIF and writes @INIT-style EDIF.

Any help would be HUGELY appreciated! I'm using Synopsys 2000.05,
powerview v6.12, viewsim v2.4, all on Solaris. Thanks!

-Erik Brunvand
ebrunvand@hotmail.com
School of Computing, University of Utah

Article: 44102
Subject: Re: burning a design
From: kayrock66@yahoo.com (Jay)
Date: 11 Jun 2002 17:08:54 -0700
Links: << >>  << T >>  << A >>
I've seen a few designs I'd like to burn...


Peter Alfke <Peter.Alfke@xilinx.com> wrote in message news:<3D063241.D1777389@xilinx.com>...
> Even more fundamentally, all Xilinx FPGAs can instigate their own complete
> reconfiguration, by using one of their outputs connected to PROGRAM, and pulling
> it down. This triggers reconfiguration, and is a 100% safe operation, even
> though it seems to violate a data sheet timing parameter.
> 
> Peter Alfke, Xilinx Applications
> (back from a one-week seminar tour of Australia.
> I was impressed by the enormous interest in Virtex-II and Virtex-IIPro!)
> ==================================
> Steve Casselman wrote:
> 
> > Yes an FPGA can change it's own design.  It should be no problem to do a
> > partial reconfiguration by hooking into the Jtag on a Virtex. The old xc6200
> > let you get to the configuration lines from the inside of the device.
> >
> > Steve
> >
> > > Hmm, theoretical yes. But Iam doubtfull if this will work out really good.
>  A
> > > FPGA can not DIRECTLY change its own design, but another FPGA/uC can
> > > reprogramm it.

Article: 44103
Subject: Re: Busses & permutations
From: kayrock66@yahoo.com (Jay)
Date: 11 Jun 2002 17:15:26 -0700
Links: << >>  << T >>  << A >>
You could constrain (locate) all pins (including unused ones) except
the largest group of pins that are interchangeable, then let the
placer have at it.  I personally don't think that I/O is going to have
that much effect on a large FPGA though, especially if you register
your outputs.

Regards

Iwo Mergler <Iwo.mergler@soton.sc.philips.com> wrote in message news:<3D05F62D.A17572D4@soton.sc.philips.com>...
> Hi all,
> 
> I interface FPGAs/CPLDs quite frequently to various types
> of memory. The wide busses regularly mess up the routing
> resources when the device approaches 100% utilization. Things
> are bad in CPLDs and worse in FPGAs.
> 
> Now, I know that I don't care about the bit order on the
> memory busses, but the fitter software always does. One
> option is to not constrain the pins, but that means PCB
> redesign.
> 
> My wish is to be able to constrain a group of signals
> (e.g. a bus) to a group of pins. That way, the fitter
> has more freedom and I don't have to change the board.
> 
> Do any of the available tools support this? 
> 
> Kind regards,
> 
> Iwo

Article: 44104
Subject: virtual ground in Xilinx XC9572 CPLD?
From: Patrick Robin <circaeng@hotmail.com>
Date: Tue, 11 Jun 2002 20:36:05 -0400
Links: << >>  << T >>  << A >>
Hi

How do I define a specific pin to be a "virtual ground" on a Xilinx
XC9572 CPLD.

I have a couple of unused I/Os that I would like to locate on each side
on my input clock signal and use as extra grounds to the CPLD.

I am using Xilinx WebPack and Verilog source.

Thanks

  Patrick


Article: 44105
Subject: Re: IBIS to Spice Translation (part1)
From: nospam@needed.com (Paul)
Date: Tue, 11 Jun 2002 20:36:50 -0400
Links: << >>  << T >>  << A >>
In article <3D067B77.AA28ACB0@xilinx.com>, Austin Lesea
<austin.lesea@xilinx.com> wrote:

> Paul,
> 
> Hey this is nifty.  This should allow anyone to download the IBIS models
> from any vendor, convert to spcie .model statements, and then simulate it in
> spice.
> 
> Sounds like you did this for 3.3V driver model.
> 
> Do the free versions of spice support the simple transmission line model?
> 
> Austin

Simulators based on Spice 3F5 have a lossless model (Txxx) and the lossy
model ltra (Oxxx). The lossy model is not perfectly general and cannot handle
the setting of RLCG at the same time. You can do an RLC based model, setting
G=0. I guess I was spoiled by HSPICE, as it is going to take me a long time
to create a model and parameters that look right. The alternative is to 
construct a model based on lumps, where you can do anything you want. In
the past, I've heard of one individual who characterized a conductor in a
test board with a network analyser, then mathematically fitted a ladder
network of components to match that characteristic. This is certainly 
beyond my capabilities. Such models have extended simulation times, due
to the large number of passive components involved.

If you examine the three files ltra_1.cir, ltra_2.cir and ltra_3.cir in
the Spice package ftp://ic.eecs.berkeley.edu/pub/Spice3/sp3f4.kit.tar.Z
you can see how both approaches can be constructed. 

I guess even with all this "free" software, there still is no free lunch.

      Paul

Article: 44106
Subject: Re: IBIS to Spice Translation (part1)
From: nospam@needed.com (Paul)
Date: Tue, 11 Jun 2002 21:00:43 -0400
Links: << >>  << T >>  << A >>
In article <3D067B77.AA28ACB0@xilinx.com>, Austin Lesea
<austin.lesea@xilinx.com> wrote:

> Paul,
> 
> Hey this is nifty.  This should allow anyone to download the IBIS models
> from any vendor, convert to spcie .model statements, and then simulate it in
> spice.
> 
> Sounds like you did this for 3.3V driver model.
> 
> Do the free versions of spice support the simple transmission line model?
> 
> Austin

Something else.

Maybe some of you out there can help me. I'd like to compare the Intusoft
converted Spice model against a real Spice model. The Philips web site
is the closest I've come, to finding commercial device models in both
IBIS and Spice form. Unfortunately, the Philips Spice model for LVC32
devices uses a LEVEL=3 MOS model and the channel is 0.8u. The Spice 3F5
level 3 code computes Leff and Weff and checks to see if they are smaller
than 1.0u, so this model won't run in Spice. This is the closest I've
come to having models of both that I can use to compare Spice with 
translated IBIS.

http://www.philipslogic.com/support/ibis/
http://www.philipslogic.com/support/ibis/lvc32/ibs/lvch32244a.ibs
http://www.philipslogic.com/support/spice/lvc32.zip

Does anyone know what valid changes I could make to these
models from the LVC32 Spice files ? Here are the transistor models
and a couple of instances of them, from the lvc32.zip collection.

************************************************ 
*         NOMINAL N-CHANNEL TRANSISTOR         * 
*            UCB-3 PARAMETER SET               *  
************************************************ 
.MODEL MNEN NMOS 
+LEVEL = 3 
+KP    = 154E-6 
+VTO   = 0.57 
+TOX   = 15E-9 
+NSUB  = 7.8E16 
+GAMMA = 0.70 
+PHI   = 0.65 
+VMAX  = 187E3 
+RS    = 7.5 
+RD    = 7.5 
+XJ    = 0.26E-6 
+LD    = 0.11E-6 
+DELTA = 1.89 
+THETA = 0.072 
+ETA   = 0.043 
+KAPPA = 0.0 
+WD    = 0.0 
 
*********************************************** 
*        NOMINAL P-CHANNEL TRANSISTOR         * 
*           UCB-3 PARAMETER SET               *  
*********************************************** 
.MODEL MPEN PMOS 
+LEVEL = 3 
+KP    = 63.7E-6 
+VTO   = -0.67 
+TOX   = 15.0E-9 
+NSUB  = 6.0E16 
+GAMMA = 0.84 
+PHI   = 0.65 
+VMAX  = 1.0E6 
+RS    = 10 
+RD    = 10 
+XJ    = 0.30E-6 
+LD    = 0.04E-6 
+DELTA = 2.88 
+THETA = 0.189 
+ETA   = 0.091 
+KAPPA = 0.0 
+WD    = -0.03E-6 

Here are a couple of transistors using these models.

MP1 3  4 50 50 MPEN W=150U L=0.8U AD=220P AS=400P PD=175U PS=175U 
MN3 3  4 60 60 MNEN W= 70U L=0.8U AD= 80P AS=170P PD= 80U PS= 80U 

Thanks,
        Paul

Article: 44107
Subject: IBIS to Spice translation (part2)
From: nospam@needed.com (Paul)
Date: Tue, 11 Jun 2002 21:07:23 -0400
Links: << >>  << T >>  << A >>
I'm having trouble posting my PostScript picture of the Intusoft
subcircuit. I think my USENET provider is filtering posts, as
I've tried to post this several times. This time, I'm going to
use ROT13 on the following text, to see if I can beat the filter.

This figure is to accompany the text description in my previous post.

It is a PostScript picture of the Intusoft subcircuit representation
of the IBIS driver. The picture should be viewable in GhostScript or 
distillable with Acrobat Distiller. Keep everything from
"%!PS-Adobe-3.0" to "%%EOF". Note: Use the ROT13 function in your
newsreader on everything from here to the bottom of the page.

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234 309 y 234 310 y s 234 311 z 235 311 y 249 306 y 249 305 y 248 305 y
234 310 y s 248 306 z 249 306 y 249 305 y 235 300 y 234 300 y 234 301 y
s 234 301 z 235 301 y 249 296 y 249 295 y 248 295 y 234 300 y s
235 291 z 236 291 y 243 286 y 243 285 y 242 285 y 235 290 y s 248 296 z
249 296 y 249 295 y 235 290 y 234 290 y 234 291 y s 242.5 286 z
242.5 268 y e 240.5 360 z 240.5 335 y e 242.5 268 z 242.5 241 y e
148 240.5 z 315 240.5 y e 12 0 0 12 54 296 Z 110.4167 (F2)n A
77.5 299.5 z 77.5 290.6635 70.3365 283.5 61.5 283.5 p
52.6635 283.5 45.5 290.6635 45.5 299.5 p
45.5 308.3365 52.6635 315.5 61.5 315.5 p
70.3365 315.5 77.5 308.3365 77.5 299.5 p u e 61.5 360 z 61.5 315 y e
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77.5 564.6635 70.3365 557.5 61.5 557.5 p
52.6635 557.5 45.5 564.6635 45.5 573.5 p
45.5 582.3365 52.6635 589.5 61.5 589.5 p
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289.6944 156.5 293.5 152.6944 293.5 148 p 293.5 147 y
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165.5 410.6635 158.3365 403.5 149.5 403.5 p
140.6635 403.5 133.5 410.6635 133.5 419.5 p
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165.5 289.6635 158.3365 282.5 149.5 282.5 p
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543 239.1193 541.8807 238 540.5 238 p
539.1193 238 538 239.1193 538 240.5 p
538 241.8807 539.1193 243 540.5 243 p
541.8807 243 543 241.8807 543 240.5 p s 542.5 240.5 z
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390 360.1193 388.8807 359 387.5 359 p
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318 360.1193 316.8807 359 315.5 359 p
314.1193 359 313 360.1193 313 361.5 p
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241.8807 364 243 362.8807 243 361.5 p s 242.5 361.5 z
242.5 360.3954 241.6046 359.5 240.5 359.5 p
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454.6046 545.5 455.5 544.6046 455.5 543.5 p u e 366 595.5 z
366 594.1193 364.8807 593 363.5 593 p
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365.5 594.3954 364.6046 593.5 363.5 593.5 p
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366 534.1193 364.8807 533 363.5 533 p
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(Vaghfbsg VOVF2FCVPR V/B Qevire Fhoppg)m RZ RC raq fubjcntr
%%CntrGenvyre
%%Genvyre
%%RBS
************* raq Vaghfbsg VOVF2FCvpr Fhoppg Fpurzngvp *****************

Article: 44108
Subject: Re: MAP problem with RLOC'ed macros
From: Ray Andraka <ray@andraka.com>
Date: Wed, 12 Jun 2002 02:03:28 GMT
Links: << >>  << T >>  << A >>
That happens when MAP puts something in the way of the F LUT, usually the
case you mention in b).   When instantiating carry chains, you can avoid
this by putting BEL constraints on the F and G LUTs to force them into the
correct half of the slice.  Here are some code snippets to help you out with
that.  It can also happen if the synthesizer duplicates some of your RLOC'd
logic.

  type bel_lut_type is array (0 to 1) of string (1 to 1);
 type bel_ff_type is array (0 to 1) of string (1 to 3);
 type bel_xor_type is array (0 to 1) of string (1 to 4);
 constant bel_lut:bel_lut_type:= ("F","G");
 constant bel_ff:bel_ff_type:= ("FFX","FFY");
 constant bel_xor:bel_xor_type:=("XORF","XORG");
(the above is in a package)


constant rloc_str : string := "R" & itoa( ((width-1)/2)-(i/2))  & "C0" &
".S" & itoa(slice mod 2);
 attribute BEL of U1:label is bel_lut(i mod 2);
 attribute BEL of U3:label is bel_xor(i mod 2);
 attribute BEL of U4:label is bel_ff(i mod 2);
 attribute RLOC   of U1 : label is rloc_str;
 attribute RLOC   of U2 : label is rloc_str;
 attribute RLOC   of U3 : label is rloc_str;
 attribute RLOC   of U4 : label is rloc_str;

Rick Filipkiewicz wrote:

> I've contructed some logic using the Xilinx carry chain [see synthesis
> query: Xilinx + Synplify] and used Synplify's xc_map, xc_uset, xc_rloc
> to contruct an RPM that includes this and a few other LUTs.
>
> In one design it worked fine but in another (its part of an SDRAM
> controller) MAP bombs out with an error message saying it can't place
> the F-LUT because of a conflict on the F input pins! As far as I can see
> the only possible sources of conflict are:
>
> (a) a MULT_AND having been mapped to the slice concerned.
>
> (b) The G-LUT of the chain having been mapped to where the F-LUT should
> go.
>
> I can't find any reference to this in the answers database but there's
> one vaguely related that's to do with MULT_ANDs.
>
> If the problem is caused by (b) is there any way for Virtex to specifiy
> that an LUT goes into a specific one of the 2 positions in a slice ? You
> could do this for the 4K series but the obvious try of applying the .<F
> | G> extension to the slice ident doesn't work.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 44109
Subject: Re: 20,000 gates?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 12 Jun 2002 02:04:59 GMT
Links: << >>  << T >>  << A >>
LUT count is more universal, as it applies across xilinx families as well as to
Altera families.  The xilinx families have different numbers of LUTs per CLB.

Roger King wrote:

> Ok, let me give you a better statistic, 384 CLBs? 384 sounds like a really
> low number, it looks like I can only develop extremely simple projects.
>
> "Roger King" <roger@king.com> wrote in message
> news:CUmN8.248826$ah_.140060@news01.bloor.is.net.cable.rogers.com...
> > Is 20,000 gates enough for creating a nice project? What are some projects
> > one can create by using 20,000 gates? I am trying to decide if 20,000
> gates
> > fpga board would be sufficient for a hobbyist that wants to use it for
> about
> > 2 years.
> >
> > I have another question. How many megs of RAM will I be able to develop
> > using 20,000 gates fpga? I mean if I want to use the fpga as a ram.
> >
> >
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 44110
Subject: Re: synthesis query: Xilinx + Synplify
From: Ray Andraka <ray@andraka.com>
Date: Wed, 12 Jun 2002 02:13:14 GMT
Links: << >>  << T >>  << A >>
You can always instantiate the FDRE or FDSE.  Then again, you may still need
syn_keeps on any logic you put in front of them.  Synplicity has recently (v7.03)
ripped up instantiated components and 'optimized' them on me.  Apparently there is
an optimize phase after synthesis to primitives and at that point it can't tell
the difference between an inferred and an instantiated primitive.  I think this
one got fixed in 7.1, but it also isn't the first time I've seen Synplicity
ripping up stuff that I instantiated.  I think it needs an internal
syn_the_user_instantiated_this_primitive_so_I_better_leave_it_alone flag on
instantiated primitives (it should be easy to identify anything that is
black-boxed when parsing the code in the first pass, especially if there is a
syn_black_box atribute on the component.

John_H wrote:

> I like the directive thought...
>
> /* synthesis syn_for_all_that_is_holy_please_oh_please_use_an_FDSE */;
>
> Rick Filipkiewicz wrote:
>
> > What we need is a directive like ``syn_carry_chain'' or, to make quite sure,
> >
> > ``syn_this_is_a_carry_chain_so_just_do_it_and_dont_ask_questions''.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 44111
Subject: Searching for high performance PLD
From: i_wok@hotmail.com (Peter Brenner)
Date: 11 Jun 2002 20:09:03 -0700
Links: << >>  << T >>  << A >>
Does anyone know of a programmable logic device or FPGA that can
operate to the folowing specifications:

>311 MHz operating speed
Industrial temperatures (-40 to 85 degrees Celcius)
Low Power (< 1 Watt)
Small footprint
2 global clocks (minimum)
Immediate Availability

one-time programmable devices are okay, although would prefer not to
use one.

Article: 44112
Subject: Re: Searching for high performance PLD
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 12 Jun 2002 15:53:58 +1200
Links: << >>  << T >>  << A >>
Peter Brenner wrote:
> 
> Does anyone know of a programmable logic device or FPGA that can
> operate to the folowing specifications:
> 
> >311 MHz operating speed
> Industrial temperatures (-40 to 85 degrees Celcius)
> Low Power (< 1 Watt)
> Small footprint
> 2 global clocks (minimum)
> Immediate Availability
> 
> one-time programmable devices are okay, although would prefer not to
> use one.

 This is too vague for usefull replies.....

One designers small is anothers large.
What package type/dimensions ? Is BGA ok ?
How many IO / registers/ ram ?
is the 311MHz for a Serial Capture, or floating point maths  ?
How many nodes need to clock at 300+MHz

 There are data sheets claiming > 300MHz for CPLD, and FPGA's can get to
that locally.

-jg

Article: 44113
Subject: Digital FM demodulator in FPGA
From: jaideep@sasken.com (jaideep)
Date: 11 Jun 2002 21:35:58 -0700
Links: << >>  << T >>  << A >>
Hi Newsgroup,

Any pointers to how to implement a digital FM demodualtor in a FPGA? I am
planning to sample the analog FM signal at 10.7 MHz and then use digital
signal proceesing to recover the baseband data. Any help in suggesting a
suitable architecture and algorithms to be used will be highly appreciated.
Thanks in advance.

Jaideep Bose

Article: 44114
Subject: Re: Digital FM demodulator in FPGA
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Wed, 12 Jun 2002 09:22:56 +0200
Links: << >>  << T >>  << A >>
Jaideep,

What you could do is the following. Sample you signal at 4 times t your
center bandwidth. ie. if you have a 5 MHz bandwidth signal centered at 10
MHz, sample at 40 MHz. Then, you just need to digitally mix the bandwidth
down to be 0 Hz. You can do this by multiplying the signal by the sequence
0,1,0,-1 to generate the imaginary samples, and 1,0,-1,0 to generate the
real signal samples. You now have a complex signal centered about 0 Hz,
which is easily retrievable.

adrian


> Hi Newsgroup,
>
> Any pointers to how to implement a digital FM demodualtor in a FPGA? I am
> planning to sample the analog FM signal at 10.7 MHz and then use digital
> signal proceesing to recover the baseband data. Any help in suggesting a
> suitable architecture and algorithms to be used will be highly
appreciated.
> Thanks in advance.
>
> Jaideep Bose



Article: 44115
Subject: Re: Visual SourceSafe and VHDL files
From: Muzaffer Kal <kal@dspia.com>
Date: Wed, 12 Jun 2002 07:39:47 GMT
Links: << >>  << T >>  << A >>
On Tue, 11 Jun 2002 16:25:44 -0400, "Jerry Francis" <jerryf@vt.edu>
wrote:

>Hi All,
>
>I am trying to use Microsoft Visual Source Safe to store VHDL files and have
>the $Log:  $ and $History:  $ keywords expand.  Can someone tell me where
>and how I can modify the
>settings so that VSS will use "--" for files of type *.vhd.  I read in the
>help that I can modify the srcsafe.ini file to do this, but the help does
>not describe in what section or how.

try 

[Keyword Comments]
*.vhd = "-- "

you also have to turn on keyword expansion in ss admin options.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Article: 44116
Subject: Re: where did my MHz go!
From: "Ken Mac" <aeu96186@yahoo.co.uk>
Date: Wed, 12 Jun 2002 08:59:52 +0100
Links: << >>  << T >>  << A >>

Jay,

Thanks for your response.

I would like to try your suggestion about using primary I/O's.

Can you just confirm exactly how I connect my ports to primary I/O's - do I
do it in my VHDL, or in my UCF?

Thanks,

Ken

"Jay" <kayrock66@yahoo.com> wrote in message
news:d049f91b.0206110904.856dfbc@posting.google.com...
> Good point about the post -MAP time, I think thats best case timing,
> and also, to answer your question "Does my choice of LOCs effect
> circuit speed?"  the answer is yes, the placer does its best but if
> you tie its hands then it can only do its best.  It gave a really good
> hint about higher placement effort because it could see the long
> routing delay.  Instead of using LOCs to stop your circuit from being
> optimized away, connect your ports to primary I/O's- unassigned, and
> see what the tool does for you.
>
> and to answer the other gentlemans question about what to do with high
> fanout nets, most modern synthesizers will reduce your fan (when
> instructed) out by trying first to duplicate the driving logic, and
> secondly by buffering.
>
> Regards
>
> Davis Moore <davism@NOSPAMxilinx.com> wrote in message
news:<3D050729.E51EDBBC@NOSPAMxilinx.com>...
> > Ken,
> >
> > The post-MAP timing report will always report a clock frequency greater
> > than the post-PAR timing report. This is because the post-MAP NCD
> > does not contain any routing delay information as the design has not yet
> > been placed or routed.
> >
> > Ken Mac wrote:
> >
> > [...SNIP...]
> >
> >   Anyway, after mapping, the maximum clock frequency is reported to be
> >   138.947MHz.
> >
> >   But, after place and route, the max clock freq. is reported to be
91.166MHz.
> >
> >   Where could I be losing so much MHz?  Can my choice of LOCs in the UCF
> >   affect the max clock freq.?
> >
> > [...SNIP...]



Article: 44117
Subject: Re: where did my MHz go!
From: "Ken Mac" <aeu96186@yahoo.co.uk>
Date: Wed, 12 Jun 2002 09:40:57 +0100
Links: << >>  << T >>  << A >>

Jay,

I switched on the option to ignore LOC constraints to let par use whatever
pins it likes.

With 9.24ns as my clock period the result was 9.263ns (Maximum frequency:
107.956MHz)

which is obviously less than my 109MHz result I had before.

No doubt with stabbing around in the dark I could find 109MHz again and
maybe exceed it...

Cheers,

Ken

"Jay" <kayrock66@yahoo.com> wrote in message
news:d049f91b.0206110904.856dfbc@posting.google.com...
> Good point about the post -MAP time, I think thats best case timing,
> and also, to answer your question "Does my choice of LOCs effect
> circuit speed?"  the answer is yes, the placer does its best but if
> you tie its hands then it can only do its best.  It gave a really good
> hint about higher placement effort because it could see the long
> routing delay.  Instead of using LOCs to stop your circuit from being
> optimized away, connect your ports to primary I/O's- unassigned, and
> see what the tool does for you.
>
> and to answer the other gentlemans question about what to do with high
> fanout nets, most modern synthesizers will reduce your fan (when
> instructed) out by trying first to duplicate the driving logic, and
> secondly by buffering.
>
> Regards
>
> Davis Moore <davism@NOSPAMxilinx.com> wrote in message
news:<3D050729.E51EDBBC@NOSPAMxilinx.com>...
> > Ken,
> >
> > The post-MAP timing report will always report a clock frequency greater
> > than the post-PAR timing report. This is because the post-MAP NCD
> > does not contain any routing delay information as the design has not yet
> > been placed or routed.
> >
> > Ken Mac wrote:
> >
> > [...SNIP...]
> >
> >   Anyway, after mapping, the maximum clock frequency is reported to be
> >   138.947MHz.
> >
> >   But, after place and route, the max clock freq. is reported to be
91.166MHz.
> >
> >   Where could I be losing so much MHz?  Can my choice of LOCs in the UCF
> >   affect the max clock freq.?
> >
> > [...SNIP...]



Article: 44118
Subject: Re: programming xc3030 using atmel's ATDH2225 programmer cable
From: t.t.withaar@student.etc.etc (Thijs)
Date: Wed, 12 Jun 2002 08:43:28 GMT
Links: << >>  << T >>  << A >>

>You can get a SpartanII XC2S50 for between $14 and $20 depending on the
>package, and that gives you about 15x the gate capacity, plus RAM
>capabilities, plus is supported by the current free tools.  You'll spend
>way more than that $10 difference trying to find a programming solution
>for the antique parts.  The cheapest package is, IIRC, the TQ144 package

Thanks all for the response. I know the XC3030 is antique. I'm lucky
enough to have found an old student version of foundation which still
supports the xc3030. So i can make things work.

If, however, i could buy a single FPGA for about $15, it 'd be a
better option indeed. The only supplier for the netherlands who
delivers single parts is www.farnell.com. They don't seem to have
cheap FPGA's. Do you know another ?

i know using an antique part seems not reasonable, but it is the only
cheap FPGA i can get hold of, and because it's for hobby purposes
only, price is important.

Greetz,

Thijs

Article: 44119
Subject: Digital FM demodulator in FPGA-continue
From: jaideep@sasken.com (jaideep)
Date: 12 Jun 2002 01:57:15 -0700
Links: << >>  << T >>  << A >>
Hi Newsgroup,

In continuation to my earlier post with the same subject, I would
appreciate very much, if someone can provide me with the following
answer: what is highest frequency analog signal that I can sample with
the currently available data converters. I am considering 2 sampling
rates; one Nyquist and the other 4x upsampling.

Thanks to Noddy for providing the information. I forgot to mention
that the IF signal (10.7 MHz +/- 125 KHz) contains FM data around
another subcarrier located 70KHz from the center of 10.7 MHz. The FM
data BW is 10 KHz around this subcarrier. Therefore I guess we need to
have a very sharp BPF centered at 70 KHz with a BW of 10KHz.Invite any
suggestion/discussion on this subject and also as how to implement
this in FPGA.

Thanks in advance.

Jaideep Bose

Article: 44120
Subject: Re: Digital FM demodulator in FPGA-continue
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Wed, 12 Jun 2002 09:44:59 GMT
Links: << >>  << T >>  << A >>
On 12 Jun 2002 01:57:15 -0700, jaideep@sasken.com (jaideep) wrote:

>Hi Newsgroup,
>
>In continuation to my earlier post with the same subject, I would
>appreciate very much, if someone can provide me with the following
>answer: what is highest frequency analog signal that I can sample with
>the currently available data converters. I am considering 2 sampling
>rates; one Nyquist and the other 4x upsampling.
>
>Thanks to Noddy for providing the information. I forgot to mention
>that the IF signal (10.7 MHz +/- 125 KHz) contains FM data around
>another subcarrier located 70KHz from the center of 10.7 MHz. The FM
>data BW is 10 KHz around this subcarrier. Therefore I guess we need to
>have a very sharp BPF centered at 70 KHz with a BW of 10KHz.Invite any
>suggestion/discussion on this subject and also as how to implement
>this in FPGA.

Hi,  Is this 70kHz subcarrier _really_ additive?  It sounds a little
like one of the subcarriers used on broadcast FM radio (although
they're usually 67kHz and 92kHz IIRC).
They are added to the baseband audio prior to modulation, and must be
extracted from the baseband audio after the demodulation.  You can't
filter them out at IF.  (FM isn't "linear" in that sense.)

Regarding sampling the 10.7MHz IF ...  Nyquist says that you only need
to sample at twice the bandwidth.  The bandwidth is determined by the
width of the start of the stopband of your analog IF filters, which
may be in the order of a MHz or so.  So you might not need to sample
at more than a few MHz.
Sampling at (say) 3MHz sounds a lot cheaper than sampling at 42.8MHz.

Do a web search for "IF sampling ADC" and also for "aperture jitter".


Here's the first hit that Google produced:
http://www.eetasia.com/ARTICLES/2001APR/2001APR03_AMD_RFD_TAC.PDF

Regards,
Allan.

Article: 44121
Subject: Re: MAP problem with RLOC'ed macros
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 12 Jun 2002 11:09:59 +0100
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

> That happens when MAP puts something in the way of the F LUT, usually the
> case you mention in b).   When instantiating carry chains, you can avoid
> this by putting BEL constraints on the F and G LUTs to force them into the
> correct half of the slice.  Here are some code snippets to help you out with
> that.  It can also happen if the synthesizer duplicates some of your RLOC'd
> logic.
>
>   type bel_lut_type is array (0 to 1) of string (1 to 1);
>  type bel_ff_type is array (0 to 1) of string (1 to 3);
>  type bel_xor_type is array (0 to 1) of string (1 to 4);
>  constant bel_lut:bel_lut_type:= ("F","G");
>  constant bel_ff:bel_ff_type:= ("FFX","FFY");
>  constant bel_xor:bel_xor_type:=("XORF","XORG");
> (the above is in a package)
>
> constant rloc_str : string := "R" & itoa( ((width-1)/2)-(i/2))  & "C0" &
> ".S" & itoa(slice mod 2);
>  attribute BEL of U1:label is bel_lut(i mod 2);
>  attribute BEL of U3:label is bel_xor(i mod 2);
>  attribute BEL of U4:label is bel_ff(i mod 2);
>  attribute RLOC   of U1 : label is rloc_str;
>  attribute RLOC   of U2 : label is rloc_str;
>  attribute RLOC   of U3 : label is rloc_str;
>  attribute RLOC   of U4 : label is rloc_str;
>
> Rick Filipkiewicz wrote:
>
> > I've contructed some logic using the Xilinx carry chain [see synthesis
> > query: Xilinx + Synplify] and used Synplify's xc_map, xc_uset, xc_rloc
> > to contruct an RPM that includes this and a few other LUTs.
> >
> > In one design it worked fine but in another (its part of an SDRAM
> > controller) MAP bombs out with an error message saying it can't place
> > the F-LUT because of a conflict on the F input pins! As far as I can see
> > the only possible sources of conflict are:
> >
> > (a) a MULT_AND having been mapped to the slice concerned.
> >
> > (b) The G-LUT of the chain having been mapped to where the F-LUT should
> > go.
> >
> > I can't find any reference to this in the answers database but there's
> > one vaguely related that's to do with MULT_ANDs.
> >
> > If the problem is caused by (b) is there any way for Virtex to specifiy
> > that an LUT goes into a specific one of the 2 positions in a slice ? You
> > could do this for the 4K series but the obvious try of applying the .<F
> > | G> extension to the slice ident doesn't work.
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

Thanks for the tip but after trying to put BELs either into the EDIF via the
xc_props attribute [the only way in Verilog] or via UCF constraints I'm still
getting the same error. So it looks like either

o MAP is ignoring the BEL constraints, or

o I'm actually in the MULT_AND case (a).

Either way its a MAP bug. The problem is that MAP doesn't seem to output any
file showing exactly what element was causing the conflict. It has got as far as
producing a .ngm so I wonder if there's any way of looking at that.

Taking out all the RPM stuff => it works. Its this that I don't understand since
the macro is only used in one place and, basically, the carry chain rloc'ing
shouldn't be necessary. All I'm really trying to do is make sure that some LUTs
that use the output of the chain are in the slices next to the one with the
carry chain; S0 for the chain and S1 for the other LUTs.

I'll need to play around with this but meanwhile I've got a client waiting who's
happy with 83MHz at the moment instead of 100!





Article: 44122
Subject: Re: Digital FM demodulator in FPGA-continue
From: "Bevan Weiss" <kaizen__@hotmail.NOSPAMcom>
Date: Wed, 12 Jun 2002 22:27:11 +1200
Links: << >>  << T >>  << A >>
Analog Devices have some pretty nice high speed ADC's.
AD6645 : 14bits @ 105MSPS
AD9430 : 12bits @ 200MSPS
AD9410 : 10bits @ 210MSPS
AD9054 : 8bits @ 200MSPS

So it becomes a bit of a tradeoff between speed and resolution.  And then
there's cost...
And power dissipation...

You've also got to remember that any mixing(intentional or not) that you do
will create intermodulation products, some of these will most likely fall
within the bandwidth of any basic (non-crystal/ceramic-resonator) filter.

You could always use a 455kHz IF.  Btw, why did you choose the 10.7MHz IF??

With a 455kHz IF you could probably then just follow it up with a low
pass/bandpass filter that would create a narrow enough signal to feed into
your ADC's.  Then do most of the more specific filtering in the FPGA
hardware (if you've got the room).
As for the actual FPGA implementation, you could use something like a
90degree transform and then the CORDIC algorithm on both the phase and
quadrature signals.  This will get you the magnitude, and the angle.  Over
time that's also the frequency.

"jaideep" <jaideep@sasken.com> wrote in message
news:c4312ee4.0206120057.65e089f@posting.google.com...
> Hi Newsgroup,
>
> In continuation to my earlier post with the same subject, I would
> appreciate very much, if someone can provide me with the following
> answer: what is highest frequency analog signal that I can sample with
> the currently available data converters. I am considering 2 sampling
> rates; one Nyquist and the other 4x upsampling.
>
> Thanks to Noddy for providing the information. I forgot to mention
> that the IF signal (10.7 MHz +/- 125 KHz) contains FM data around
> another subcarrier located 70KHz from the center of 10.7 MHz. The FM
> data BW is 10 KHz around this subcarrier. Therefore I guess we need to
> have a very sharp BPF centered at 70 KHz with a BW of 10KHz.Invite any
> suggestion/discussion on this subject and also as how to implement
> this in FPGA.
>
> Thanks in advance.
>
> Jaideep Bose



Article: 44123
Subject: Re: Digital FM demodulator in FPGA-continue
From: "Ulf Samuelsson" <ulf@atmel.REMOVE.com>
Date: Wed, 12 Jun 2002 13:04:35 +0200
Links: << >>  << T >>  << A >>
>
> In continuation to my earlier post with the same subject, I would
> appreciate very much, if someone can provide me with the following
> answer: what is highest frequency analog signal that I can sample with
> the currently available data converters. I am considering 2 sampling
> rates; one Nyquist and the other 4x upsampling.
>
You can get into the 1-2 GigaSample but I am sure that the design can be
complex.

--
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.




Article: 44124
Subject: Re: Problems initialising an FPGA - SPARTAN II
From: "Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it>
Date: Wed, 12 Jun 2002 11:37:14 GMT
Links: << >>  << T >>  << A >>
"Peter Alfke" <Peter.Alfke@xilinx.com> ha scritto nel messaggio
news:3D066CB4.DE6A2688@xilinx.com...

> John is right.
> On all the modern (Virtex and Spartan class) devices, the
> larger speed-file
> number describes the faster part.

Whoops, I believed that -n in FPGAs had the same meaning of -n in CPLDs.
For CPLDs, -n is actually the pad-to-pad delay.

I have the Virtex development system on the desk from weeks, maybe I'd
better see what the boxes contain. :)

--
Lorenzo





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