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Thank you Gabor for the information.Article: 80951
Andrés <nospam_nussspucke@gmx.de> wrote in message news:<39lghjF62701cU1@individual.net>...
> A Beaujean wrote:
>
> > OK. Well, there follows a link with a very interesting paper on
> > potential problems with (too) simple asynchronous resets.
> >
> > http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf
> >
> > Having acknowledged the potential dangers described in that paper, I
> > now systematically create for my VHDL designs a synced reset per clock
> > domain and uses those synced resets as async reset inputs on all
> > registers of the design. I just let the synthesis and PAR tool operate
> > as usual, giving no special directive, and got not problem until now.
>
> Hi Beaujean,
>
> do the registers which are used to sync the external reset
> have an asynchronous reset input ? If yes, what signal does feed these
> reset inputs ?
>
>
> Thanks for all posts.
>
> Best Rgds
> Andrés
The setups for the two flip-flops used are very well described in the
paper mentioned :
http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf
on pages 21 and 22 (page 22 gives a VHDL implementation).
The form I used in VHDL is very slightly different, but strictly
equivalent in terms of functionality.
Architecture Arch_Of_SAFE_ASYNC_RESET Of SAFE_ASYNC_RESET Is
--
-- Signals
--
Signal First_Ff : std_logic ;
--
Begin
--
-------------------------------------------------------------------------------
--
-- SYNCHRONOUS PROCESSES
--
-------------------------------------------------------------------------------
--
First_Ff_Process:
Process(Reset_Not_In,Clock)
Begin
If (Reset_Not_In = '0') Then
First_Ff <= '0' ;
Else
If Rising_Edge(Clock) Then
First_Ff <= '1' ;
End If ;
End If ;
End Process ;
--
Reset_Not_Out_Process:
Process(Reset_Not_In,Clock)
Begin
If (Reset_Not_In = '0') Then
Reset_Not_Out <= '0' ;
Else
If Rising_Edge(Clock) Then
Reset_Not_Out <= First_Ff ;
End If ;
End If ;
End Process ;
--
End Arch_Of_SAFE_ASYNC_RESET ;
Hope this serves a bit.
A. Beaujean
Article: 80952Hi wo knows a cheap 100baseTX MAC/PHY daughterboard (eg equipped with LAN91C111 from smsc) to use with an fpga dev.board? thanks marcoArticle: 80953
Hi all, I'm a student and newbie in FPGA design. I have a port of uC/OS-II on Memec Virtex-II MB1000 Development Kit from the Micrium's website and i want to port it on a Spartan3 Board from Digilent (https://www.digilentinc.com/Sales/Product.cfm?Prod=S3BOARD). All services of the OS are disabled. There is only 1 task and print. The program size is 21 KB. On S3, there is 216Kbits/27KB of BRAM. In parameters Tab of EDK, i set C_MEMSIZE if Bram to 27000 and my both lmb controller to 16KB (max). I have always ".elf cannot reside completely in bram", i set microblaze_0_bootloop to "marked to initialize BRAMs" and follow the instructions as written in many tutorials for debugging. XMD told me : "unable to stop Microblaze, verify if FPGA is configured and Microblaze system clock is connected properly". I have change the .ucf file to correspond with my card and the system clock is set. Are there other files to change? Could someone help me to understand that is wrong? Thanks for your answer !Article: 80954
Hi there, I have the same problem: two presorted arrays have to be merged (but here in Verilog). Can anybody provide me code fragments or hints? Thanks a lot, ChrisArticle: 80955
Andrew Smallshaw wrote: > On a slightly different note, does anyone know why most serial protocols > use simple voltage levels to denote a logic 0 or 1? I admit I'm no expert > but I recall from my A-level electronics an edge-triggered system where a > '0' would be (say) low-followed-by-high whereas a '1' would be > high-followed-by-low. Yes, this means _at_least_ twice as many voltage > transitions per bit but I would have thought that given its greater resilience > mismatched clocks or any stray capacitance it would be worth the trade off. This is used already, and is called Bi-Phase or Manchester encoding, for the two phase variants of this Clock+Data Scheme. -jgArticle: 80956
Hi Doug, there are versions of DSE that supports seeds like 1-10 20-30, other versions need that you write 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30. Maybe you are writing "1-10" in a version that does not support this? Beside that DSE worked always fine for me (not tested distributed usage yet). Thomas www.entner-electronics.com "Douglas Sykora" <djsykoraNOSPAMM@execpc.com> schrieb im Newsbeitrag news:113cqgdrss51rbf@corp.supernews.com... > Altera includes the Design Space Explorer (DSE) along with Quartus II. I > have found this tcl script to be very helpful when I can get it to work > for > me. But lately, it has been very frustrating because it fails to explore > the space I set it up to explore. > > Has anyone else seen this behavior? > - I set up the exploration space in the DSE GUI, for example, to do a > seed > sweep. > - DSE starts by running a compilation flow on the base. > - DSE finishes this and archives the results. > - DSE stops and displays a message that there are no errors or warnings. > It doesn't go on to the next point in the exploration space. > > I have also tried this with the distributed computing option. DSE will > create archives, one for each exploration point. It then submits one to a > remote computer and fails to actually compile it, and the process ends. > > If you have seen this behavior, do you know what could be causing it and > how > to correct it. > > I have not found any references to this problem in the archives and > haven't > received much help yet from the Altera support group, but I am hoping this > is forthcoming. > > I am running with the Windows XP operating system (also tried Windows > 2000) > and using the latest version of Quartus II (4.2 SP1). > > I have used DSE successfully, so it doesn't always display this behavior. > > Thanks in Advance, > Doug > >Article: 80957
Gog wrote: > Hi all, > > I'm a student and newbie in FPGA design. > I have a port of uC/OS-II on Memec Virtex-II MB1000 Development Kit > from the Micrium's website and i want to port it on a Spartan3 Board > from Digilent > (https://www.digilentinc.com/Sales/Product.cfm?Prod=S3BOARD). > All services of the OS are disabled. There is only 1 task and print. > The program size is 21 KB. On S3, there is 216Kbits/27KB of BRAM. > In parameters Tab of EDK, i set C_MEMSIZE if Bram to 27000 and my both > lmb controller to 16KB (max). I have always ".elf cannot reside > completely in bram", i set microblaze_0_bootloop to "marked to > initialize BRAMs" and follow the instructions as written in many > tutorials for debugging. XMD told me : "unable to stop Microblaze, > verify if FPGA is configured and Microblaze system clock is connected > properly". I have change the .ucf file > to correspond with my card and the system clock is set. > > Are there other files to change? Could someone help me to understand > that is wrong? > > Thanks for your answer ! > Hi, You can't get a 21kbyte program into a 16kbyte memory. The memory blocks in EDK can only have the size of 2**N so you need two memory blocks, one of 16kbyte and one of 8 kbyte. This should give you enough memory. But I would suggest that you starting to use the external memory on the board. On the problem with debugging, much more information is needed about your system. Have you enabled HW debug logic on MicroBlaze? GöranArticle: 80958
On Mon, 14 Mar 2005 21:44:18 +0000, Andy Main <a.s.main@gmail.com> wrote: >John Adair wrote: >> Xilinx have started selling some stuff direct. I don't know if XCF01s are on >> list, or if there are any problems, or costs, in getting UK delivery but >> have a look. > >They sell a few Spartans, but not the proms to go with them! > >> >> Alternatively try both halves of Memec with the franchaise. They are >> technically in competition. I would use the telephone for maximum result. If >> after trying all that you still have a problem give me a call and I'll try >> and assist. > >Thanks for the offer. I'll try and give them a ring first but may take >you up on that. > >I still can't get over the fact that there are no hobbiest type >distributers for these entry level devices. That would be because there is negligible business - I would imagine the number of UK hobbyist users of these parts would barely make double figures.Article: 80959
Hi, I am trying to create my own reusable Relationally Placed Macro (RPM) using ISE 6.3.03i without much success. I have followed the procedure defined in the "Creating a reusable RPM core" manual page without much luck. I am using the "Write RPM to UCF" command in the floorplanner to create the UCF (RLOC'ed) and NGC file. This works fine for a single instantiation connected to the package pins but not for the desired general case of a macro used several times internally to a larger design. I appear to be getting IIOB & OIOB objects in the NGC netlist for the RPM and cannot get NGDbuild to recognise when it has already used slices in the case where more than one instance is created (suspect not recognising boundary area for RPM?). If any one has any ideas or a simple example (VHDL preferred)...... Many thanks, TimArticle: 80960
Hi. I'm a newbie to fpga design and I'd like to know whether it's possible to simulate the behaviour of a bitstream generated with ISEWebPack without implementing it on board. Can I use for this the Virtex DeviceSimulator? Where can I download it? And i'd also like to test on my computer a vhdl program that writes some stuff to screen. Is it possible? Thanks a lot.Article: 80961
Hello Guys, How do i call an IP core which is avaiable in netlist form in my design. Can some one please tell me call the module. Thanks and regards WilliamsArticle: 80962
Thomas, Thanks for the tip. I will try the enumerated seed specification as soon as I get into work. I have been using the range specification such as 2-10. Thanks Doug "Thomas Entner" <aon.912710880@aon.at> wrote in message news:42369e19$0$15878$91cee783@newsreader02.highway.telekom.at... > Hi Doug, > > there are versions of DSE that supports seeds like 1-10 20-30, other > versions need that you write 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 > 29 30. Maybe you are writing "1-10" in a version that does not support this? > Beside that DSE worked always fine for me (not tested distributed usage > yet). > > Thomas > > www.entner-electronics.com > > "Douglas Sykora" <djsykoraNOSPAMM@execpc.com> schrieb im Newsbeitrag > news:113cqgdrss51rbf@corp.supernews.com... > > Altera includes the Design Space Explorer (DSE) along with Quartus II. I > > have found this tcl script to be very helpful when I can get it to work > > for > > me. But lately, it has been very frustrating because it fails to explore > > the space I set it up to explore. > > > > Has anyone else seen this behavior? > > - I set up the exploration space in the DSE GUI, for example, to do a > > seed > > sweep. > > - DSE starts by running a compilation flow on the base. > > - DSE finishes this and archives the results. > > - DSE stops and displays a message that there are no errors or warnings. > > It doesn't go on to the next point in the exploration space. > > > > I have also tried this with the distributed computing option. DSE will > > create archives, one for each exploration point. It then submits one to a > > remote computer and fails to actually compile it, and the process ends. > > > > If you have seen this behavior, do you know what could be causing it and > > how > > to correct it. > > > > I have not found any references to this problem in the archives and > > haven't > > received much help yet from the Altera support group, but I am hoping this > > is forthcoming. > > > > I am running with the Windows XP operating system (also tried Windows > > 2000) > > and using the latest version of Quartus II (4.2 SP1). > > > > I have used DSE successfully, so it doesn't always display this behavior. > > > > Thanks in Advance, > > Doug > > > > > >Article: 80963
Brian Philofsky <brian.philofsky@no_xilinx_spam.com> writes: > Hmmm. That is not how it is supposed to work. We are looking into > this and either I or someone else will get back to you. Excellent! Thank you very much. If you need more information to reproduce this bug, I will be happy to provide it, of course. -- GPG: D5D4E405 - 2F9B BCCC 8527 692A 04E3 331E FAF8 226A D5D4 E405Article: 80964
lecroy7...@chek.com wrote: > > So far, it would appear the problem is not related to the supply > voltage or operating temperature. > I don't believe the supply tests you've described so far would have certainly induced the configuration problem. > > I ran the supply at 4.5 volts and injected a 500mV signal. > I did multiple sweeps from 100KHz up to a bit over a GHz > Was that 500 mV measured at the device VCC pins, or on the front panel of the 50 ohm signal source driving the bias-T? Either way, I second Philip's suggestion that you should try to re-create the problem with a brief, not-quite-to-zero glitch on the supply. My own encounter with this problem (long ago) occurred under rapid AC power switch cycling as described in his original link. > >The Reset normally idles high and it along with the > Program pin are pulled low for 7.5us > When you next induce this problem, here are some random thoughts on additional sticks with which to poke at the stuck FPGA: - longer ( >>6us ) reset and program pulses - send more config data than needed and look for data to appear on DOUT - if possible, stop driving CCLK externally, switch the mode pins on the stuck device to master serial, then reset and look for CCLK coming out of the part BrianArticle: 80965
Thanks again. I will try the pulsed supply as suggested today and post my findings. To give you an idea of the MTBF, of about 90 ICs being run, I have seen or heard of the problem 5 times over about a six month period. There is not a good way to probe the parts after the fact to see what is going on. Reproducing the problem seems to be the only good way to solve it at this point.Article: 80966
> Hello Guys, > How do i call an IP core which is avaiable in netlist form in my design. > Can some one please tell me call the module. You don't "call" the module. You instantiate it. e.g. ip_core core_inst0 (port connection goes here...); HTH, JimArticle: 80967
Is the memory gate count in ASIC the same number as in FPGA? For example I have 300Kbyte rom in ASIC needs to be implemented in Xilinx FPGA, what the gate count in FPGA I expect? THanks!Article: 80968
On Tue, 15 Mar 2005 09:03:59 +0000, Tim Good <elp04trg@sheffield.ac.uk> wrote: >Hi, > >I am trying to create my own reusable Relationally Placed Macro (RPM) >using ISE 6.3.03i without much success. I have followed the procedure >defined in the "Creating a reusable RPM core" manual page without much luck. 6.3 has quite a few problems with floorplanning, RPM generation, and multiple RPM instantiation. 7.1 is reported to fix a LOT of these problems, so if you need to use RPMs, I would strongly recommend upgrading to 7.1 at the earliest possible moment. (the problem you describe below is however NOT a 6.3 bug as far as I can see) >I am using the "Write RPM to UCF" command in the floorplanner to create >the UCF (RLOC'ed) and NGC file. This works fine for a single >instantiation connected to the package pins but not for the desired >general case of a macro used several times internally to a larger design. > >I appear to be getting IIOB & OIOB objects in the NGC netlist for the >RPM and cannot get NGDbuild to recognise when it has already used slices > in the case where more than one instance is created (suspect not >recognising boundary area for RPM?). Ah. The RPM is not supposed to contain ANY IOBs. You have to turn OFF IOB instantiation in both the Synthesis and Translate phases (either via command line, or "Properties" for each tool. You can confirm that IOBs have been successfully disabled in the "map" report file. Then create the RPM .ngc file as now, and multiple instantiations should work. Connecting up IOBs is best done at the top level. Even if it is possible to build an RPM with package pins included, and you can live with the restrictions placed on placing the resulting RPMs (they have to be aligned with IOBs!) it is quite likely that tool support for this practice may be buggy. >If any one has any ideas or a simple example (VHDL preferred)...... Here's one - a simple RPM instantiated 8 times in VHDL. http://www.shapes.demon.co.uk/files/crashme.zip It illustrates some of the issues which 6.3 had with RPMs, but (if you modify the RPM placements given) shows that it can be done. I look forward to seeing how 7.1 treats this example... - BrianArticle: 80969
On Mon, 14 Mar 2005 14:56:29 +0000, Andy Main <a.s.main@gmail.com> wrote: >Hi there, > >I still can't find a UK supplier for a low quantity (8) of XCF01 memory. > Memec don't reply to my messages, and the only supplier in the states >I found (nuhorizons) were charging $75 to ship to me! Memec/Insight DO work, but it's best to make contact by phone, and speak to a real person. Number is buried somewhere deep in their website... - BrianArticle: 80970
xing1234@yahoo.com wrote: > Is the memory gate count in ASIC the same number as in FPGA? For > example I have 300Kbyte rom in ASIC needs to be implemented in Xilinx > FPGA, what the gate count in FPGA I expect? > > THanks! First of all I would suggest to forget the "gate count" numbers from the FPGA vendors and look at the features of the FPGA. To build a ROM in an FPGA is easiest using dedicated block memory of the device. Most FPGA's allow memory to be generated from distributed logic cell elements. In the case of a ROM, you can generate the memory you need from LUTs in the FPGA fabric even if the distributed memory is not available, but it will be a bigger headache. >From Xilinx, you would need a very large part to get 300Kbytes of block memory. Note that the datasheet counts bits not bytes so you're talking 2.4 Megabits - something like a Virtex-II 6000 "6 million gate" - but of course that leaves pretty much all of the logic resources for the rest of your design.Article: 80971
Hi Williams, It goes like this... library lib_name ; -- Name of the library where IP Core is use lib_name package_name ; -- name of the package where the component interface is defined Later in the architecture body you can instantiate it .... U1 : ip_core_name port map ( .........); Mohammed A khader.Article: 80972
Oh, the problem was because the cable was still connected in IMPACT. I can successfully run the get device ID xsvf, but when I tried to program the chip, I get this error: ERROR: "DATA overflows allocated MAX_LEN buffer size ERROR at or near XSVF #27. See line 27 in the XSVF ASCII file. Does anyone know why? Thanks, ALArticle: 80973
xing1234@yahoo.com wrote: > Is the memory gate count in ASIC the same number as in FPGA? For > example I have 300Kbyte rom in ASIC needs to be implemented in Xilinx > FPGA, what the gate count in FPGA I expect? > > THanks! Hi Xing1 Your 300Kbyte ASIC rom would use up about 150 BRams assuming 16Kbit useage (18b might take some less. If thats is mostly Firmware then thats alot of Bram to use up for 1 item. I generally budget 1Bram at about $1 of FPGA cost so thats alot of $ cost and also note that Asic rom is maybe 10x-20x cheaper than regular sram in same process so using Brams for just code storage might be extravagent. You could look at storing that off chip and use that BRam as cache if its for a cpu or work out an external Flash interface. If by chance you were storing very high precision coeff tables that you could also synthesize with an engine or two, that may well take up far less resources, something you could care less perhaps in an ASIC but FPGAs are just not that cheap Yet! Is it Firmware or coeff data? regards johnjakson at usa dot comArticle: 80974
Jezwold wrote:
> I would say that everyone else seems to manage in producing working
> designs without rewritting either vhdl or verilog,niether of them are
> meant to be a 'programming language' so aproaching them from the point
> of view of a programmer isnt the best way of looking at them.
Genericity is not a programming language approach. This is an
abstract concept, which is used by many programming languages,
but is not a part of them. Moreover, it is much more useful in
hardware specifications than in programming languages. However,
its support in VHDL and Verilog is very restricted and annoying.
So the only reasonable thing I can do is to create my own HDL
and a translator to VHDL, to reuse existing tools. :-)
Best regards
Piotr Wyderski
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