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strshn99@my-deja.com wrote: > > Dear Gurus, > > I have a newbie question to ask you. What kind of Revision control > tools do you use when you are working on a design? Any recommendation > as to which is better? I used RCS and SCCS and was quite happy with both of them > > What tools are recommended for coverage analysis? VHDLCOVER is easy to use but the big gun called specman does more. > > What tools are recommended for formal verification The new Synopsys tool should be fine > > What tools are recommended for timing verification, I like Synopsys' Primetime > is it acceptable to > conduct timing verification by embedding timing delays in a VHDL test > bench? you know X <== ( Y AND Z ) AFTER 12 NS No, it is isn't > > thanks in advance > > Sent via Deja.com > http://www.deja.com/ -- Mit freundlichen Grüßen Christof Abt +---------------------------------------------------------------+ | Christof Abt Marconi Communications MC-AC/ASD | | P.O.Box 30 00 Phone: +(7191) 13-2820 | | D-71520 Backnang Fax : +(7191) 13-4321 | | Germany email: Christof.Abt@marconi.com | +---------------------------------------------------------------+Article: 28626
<eml@riverside-machines.com.NOSPAM> wrote in message news:3a66ce37.8952109@news.dial.pipex.com... > 1) > the obvious one - it's got a GUI. Ok, I'm not in favour of GUIs for > the sake of it, but if any tool needs a GUI then it's a VCS (or any > file manager, come to think of it). You get an immediate view of the > whole project, you can see which files are modified, you can sort on > tags, you can sort on modified files (irrespective of directory) so > that you can check in all modded files at once, you can checkout only > the required files without having to painfully remember and type each > one, or creating a new module name for each set you're likely to want, > you can see who's got what file checked out, and a dozen other things. WinCVS can also you a flat view of the project. You can also save several project settings (the local directory where you've checked it out, and the location/type of the repository, and some other options). One of the less-used features "watch" can also let you know who's got a file checked out. > 2) > The other obvious one - CVS doesn't have reserved checkouts. In fact, > I did a quick survey of VCS tools recently, and opinion was divided on > whether a tool should support reserved checkouts or not. RCS, SCCS, > MKS, Clearcase, WebDAV, Sourcesafe, and Perforce all thought that it > should, CVS thought that it shouldn't. Isn't this what "cvs admin -l" does? > I had an argument with someone recently who had used CVS on a large > ASIC project, and their reply was that "this doesn't happen in > practice". IMO, it will happen eventually, and the whole point of a > management tool is to enforce systems to prevent this sort of thing > happening. There's a reason I'm not sure how the locking features works, it hasn't been necessary "in practice". :) > 3) > MKS implements a security mechanism in which you can set up projects > and groups, and assign permissions to people in groups, within a given > project. For instance, you may want to give a couple of people write > access to a given project, and give everyone else only read access; or > you may want to make sure that only some people can create or delete > archives. IMO, this is important when you have development groups with > a large range of abilities in them (and in which only a few people, if > any, have previously used a VCS). CVS can also do this using its password, readers, etc. files in the CVSROOT folder. This doesn't seem to get used very often (other than creating a single read-only account). Still, it's there for the case you describe above. > >CVS. However, I had some problems with the Windows port of CVS. Today > >I tried to check in a netlist and I got: > > > >cvs server: Up-to-date check failed for `PSB63.edf' > >cvs [server aborted]: correct above errors first! > > > >I had to transfer the files over to Solaris and check them in from > >there... > > Unfortunately, I occasionally get errors as well The main problem seems to be with CVS repositories that are mounted as a local directory under Windows, instead of using pserver (or ntserver). There are problems overriding the read-only file permissions in the repository. I don't know if this applies to MKS or not. > Here's an example from a couple of weeks ago. I wanted to import a > module using WinCVS. The "import module" selection is the next one > down on the menu from "create repository". I clicked "create > repository" by mistake, and then quickly clicked "ok" by mistake, > instead of "cancel". The new repository defaults to the same place as > the old repository - it took several hours to find out what had > happened and to restore from tape afterwards. Ok, you can't make this > mistake from the command line interface, but my point is that project > security is more complex than making sure that you have a secure > connection to the server, and that's one thing that commercial > products do better than CVS. Sounds like you should have read-only access... Seriously, though, I would much rather see someone take it on and improve it, rather than buying into a proprietary product like ClearCase or Synchronicity (no one's mentioned this one yet). Cyclic was trying this, but seemed to be afraid to break compatibility. At one point, I was trying to set up a CVS pserver, and was having all sorts of problems with it trying to find local preferences files. Browsing through the CVS source, it was quite amusing to see that they put into comments that they wanted to do away with this feature altogether. How about CVS2 anyone, all the things that are good in CVS, minus the junk no one needs, and some new features (such as locking?) thrown in. Cheers, JamieArticle: 28627
When I was at HP we used to use an internal tool called HMS, worked great for multisite HDL projects and binaries. It then became productized by HP under the name of Softbench, but the HP dropped it and the developer formed his own company for it, but I forgot what the name of the company is. Any pointers on where I could get it would be welcomed. I like it better than CVS (which we are now using). And it was not as complicated as Clearcase (which I have used for software projects in the past too). And it handled binaries, which RCS does not, and worked very well for both geographically disperse and close projects. Doug Hillmer.Article: 28628
Is there a tool to partially dynamical reconfigure a Virtex FPGA via JTAG-Interface? I think with JTAG-Programmer it isn't possible. The Virtex FPGA is configured with bitstream 1. With JBits I manipulate this bitstream 1 to get a new bitstream 2. What tool can I use to download the bitstream 2 without generating a device reset. I'd like the unaffected parts to continue their work without interruption. Is this possible? Thanks, Michael PS: My board doesn't support the JBits XHWIF so I think somehow I have to use the JTAG-Interface directly for reconfiguration.Article: 28629
Ken, I didn't realize you were a lurker here. Thanks for chiming in. You are, of course, absolutely correct. DSP processors can't hope to keep up in software radio/radar applications where the sampling is being done at IF at tens of MHz. In the case of downconversion, there are a number of hardware tricks that can be used including polyphase decomposition filters, distributed arithmetic, and CORDIC. It is quite possible using these techniques to get 100x the performance of a DSP microprocessor for close to the same cost. For some details on downconversion, see my article in the winter 2000 issue of the Xilinx XCell Journal (sorry, it is not on-line at this time, you can order your subscription by searchning for XCell on the Xilinx website). I've got some radar and radar simulator examples in papers available on my website. One is doing the equivalent of 11 billion multiplies per second in a Virtex-4 (slow speed grade) part. The catch is there are not all that many people versed in hardware DSP, so it can be challenging to get this kind of performance. Xilinx has closed the gap somewhat with their system generator tool, but it is far from a complete solution (It basically lets you intantiate cores from within Matlab simulink). THe tool knows nothing about algorithms, and in hardware DSP the big thing is tailoring the algorithm to a hardware-friendly implementation. The new virtex II is also exciting because it offers some more "software DSP like" features. My advice is, if it will run at the desired sample rate in a single DSP processor, use the DSP: It is alot easier and cheaper to find software DSP expertise than hardware DSP expertise. If a DSP doesn't cut it by just a little, you might still be better off going with a few DSPs, depending on the available expertise. For much more than that, you probably want to bring someone in who can either do the design or architecture, or teach you people how to do it (the learning is not an over night process, but pointing out some of the hardware techniques goes along way toward breaching some of the hurdles.) Ken Chapman wrote: > > Dear Tom, > > In simple terms, this is about the required horsepower for the application. > If you can really perform all the processing that you need to in a single > DSP processor chip then it does provide you with a very easy way to > prototype your system. > > However, at 50MHz sample rate you will soon burn up the available number of > MIPS available to you in a DSP processor. If we consider the > TMS320VC5410-10 device, it has a single 17x17 multiplier clocked at 100MHz. > This would only allow you to perform 2 operations at 50MHz. Obviously you > will be performing down-conversion to carry out most of your work at a > lower sample rate, but this down-conversion in itself will almost certainly > require more than this 100MIPS. These processors are really excellent when > you have lots of time between samples such as in audio. At At 48KHz the > 100MIPS provides over 2000 operations per sample. > > In contrast, a device such as the Xilinx Spartan-II XC2S150 is a 'blank > sheet' onto which a DSP design can be implemented. It contains 864 > Configurable Logic Blocks which could implement 10 full 16x16 multipliers > operating at over 100MHz. That provides over 1000 MIPS. Unlike the fixed > architecture of a processor where flexability is derived via software code > that utilises 'spare' clock cycles (if you have any), the Xilinx route > provides you the flexability to produce any architecture containing > multipliers, adders, comaparitors etc all working in parallel. It is highly > unlikely you will need full 16x16 multipliers and this means that the > effective MIP count can be increase as smaller modules are constructed. > > The Spartan devices are in the $5 to $20 range providing a lot of > processing potential per $ compared with a DSP processor. If you have not > looked at Xilinx DSP before then you will need to take some time to look > into it and how designs can be implemented. There are tools that generate > complete FIR filters and NCOs for you as well as the simple blocks. > > I have worked on RADAR systems before joining Xilinx, and many times with > Xinlinx customers during my 10 years with the company. Some of the most > successful systems are the ones that combine the merits of both the Xilinx > devices and the DSP processors. The Xilinx device is used to perform the > intensive processing of the data path flow. The DSP processor acts as a > controller and less time critical calculator. In your case the actual beam > forming would probably be done by the FPGA, but the calculation of > coefficients to set the beam pattern would be made by the DSP processor. > > There are DSP seminars by Xilinx on the 25th January all over North > America. Try to go to one! > > Yours sincerely, > > Ken Chapman > > Xilinx Applications (UK) -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28630
I want to design an interface between a DSP and a FPGA. The DSP should be able to access FPGA registers, via the DSP parallel port. The DSP parallel port has address, data, chip select, read and write lines. Just the usual stuff. I just designed this interface, but I am not happy with the results in terms of speed and design stability. So I want to ask this audience for some design hints. 1) Write access: I just synchronize the DSP write signal and generate an internal write strobe to fetch the data. Is it a better solution to use the write signal to store the data in a register and then synchronize the register contents to the internal clock? This makes it possible to detect very short write strobes of the DSP and to reduce the number of WS, in the application. 2) Read access: I use a async. read access at the moment. Is it possible to make this work synchronously? The problem is that synchronizing just eats up a lot of time, and timing constraints of modern DSP are pretty tight. There will be a problem if the FPGA does not release the DSP data bus fast enough, because read and write accesses can appear very soon after each other. Any suggestions, or literature tips? -- chrisArticle: 28631
Austin Lesea wrote: > > Bob, > > The impedance updates are asynchronous, and are done in such a manner that > the updates trim values are all extremely small. The resultant dR/dt is > undetectable in the signal integrity of the output. How will you handle the variable impedances in the IBIS models? Please tell me you'll have IBIS models ... -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 28632
#ROBERTUS WAHENDRO ADI# wrote: > > Hi all, > Can variable be shared between one process to another? > if yes, How to do it? You can use a shared variable. You might want to ask your question in comp.lang.vhdl. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 28633
On Thu, 18 Jan 2001 11:50:44 -0500, "Jamie Sanderson" <jamie@nortelnetworks.com> wrote: >WinCVS can also you a flat view of the project. I haven't found this (I'm on 1.1b16) - can you tell me how do it? > You can also save several >project settings (the local directory where you've checked it out, and the >location/type of the repository, and some other options). One of the >less-used features "watch" can also let you know who's got a file checked >out. I've never used it - email notification seems a very clunky way to find out what's going on. It's nice to able to run up the GUI and immediately see who's doing what. >> 2) >> The other obvious one - CVS doesn't have reserved checkouts. In fact, >> I did a quick survey of VCS tools recently, and opinion was divided on >> whether a tool should support reserved checkouts or not. RCS, SCCS, >> MKS, Clearcase, WebDAV, Sourcesafe, and Perforce all thought that it >> should, CVS thought that it shouldn't. > >Isn't this what "cvs admin -l" does? Hmmm... not really sure. The docs say that you can use it in conjunction with the Perl script I mentioned, to give reserved checkouts. I read somewhere else that it didn't work particularly well. So, I found the script (which I understand only marginally) after reading your reply, and it tells you to lock the file with rcs, and the script can then prevent a commit if someone else has the lock. Maybe admin -l is actually rcs -l, the rcs lock. It all seems very kludgey - the CVS docs say you're on your own if you use it. >> 3) >> MKS implements a security mechanism in which you can set up projects >> and groups, and assign permissions to people in groups, within a given >> project. For instance, you may want to give a couple of people write >> access to a given project, and give everyone else only read access; or >> you may want to make sure that only some people can create or delete >> archives. IMO, this is important when you have development groups with >> a large range of abilities in them (and in which only a few people, if >> any, have previously used a VCS). > >CVS can also do this using its password, readers, etc. files in the CVSROOT >folder. This doesn't seem to get used very often (other than creating a >single read-only account). Still, it's there for the case you describe >above. Very interesting - I haven't heard of this; I'll have a look. >Sounds like you should have read-only access... Seriously, though, I would >much rather see someone take it on and improve it, rather than buying into a >proprietary product like ClearCase or Synchronicity (no one's mentioned this >one yet). Cyclic was trying this, but seemed to be afraid to break >compatibility. At one point, I was trying to set up a CVS pserver, and was >having all sorts of problems with it trying to find local preferences files. >Browsing through the CVS source, it was quite amusing to see that they put >into comments that they wanted to do away with this feature altogether. How >about CVS2 anyone, all the things that are good in CVS, minus the junk no >one needs, and some new features (such as locking?) thrown in. Sounds good, but it's back to the old 'free' v. commercial argument - if I'm paying someone, then their job depends on it, and they're hopefully going to be more likely to get it right than a volunteer. Anyone doing a chip has to invest a minimum of several K$, and maybe several hundred K$ - I personally am certainly willing to pay a small fraction of that for a commercial tool. To each his own. EvanArticle: 28634
Did somebody try to archive to tools as well? -- chrisArticle: 28635
eml@riverside-machines.com.NOSPAM wrote: > >Isn't this what "cvs admin -l" does? > > Hmmm... not really sure. The docs say that you can use it in > conjunction with the Perl script I mentioned, to give reserved > checkouts. I read somewhere else that it didn't work particularly > well. So, I found the script (which I understand only marginally) > after reading your reply, and it tells you to lock the file with rcs, > and the script can then prevent a commit if someone else has the lock. > Maybe admin -l is actually rcs -l, the rcs lock. It all seems very > kludgey - the CVS docs say you're on your own if you use it. It works fine. It has been used on several projects. It is kludgey though. We have scripts called lock and unlock. All files are checked-out read-only (a CVS setting). Lock, locks the file (cvs admin -l), updates it to the newest version and then gives it write permissions. Unlock, unlocks the file (cvs admin -u), removes write permissions. Unlock is rarely used as a checkin will unlock the file anyway. The annoying thing about this is that when you checkin the file it unlocks it automatically. If you are just doing an incremental checkin and still want the file locked you have to re-lock it again. The perl script is there to prevent checkins of files that are not locked. The perl script is called in CVS (add a line in the commitinfo file to call the script). I personally would rather not use locks because it gets annoying during top level edits. You have to run over and tell the person that has it locked to either: unlock the file or do the edit for you. Everyone seems leery of unreserved checkins, I like them. Once you are using file locking, you can write a script to parse "cvs log" and determine who has which files are locked. CVS works fine. It has its problems, but it is simple. Very short learning curve (a few simple commands to remember). No problems with repository corruption. MD -- Martin Darwin ASIC Design Engineer Tel +1 (613) 784-8873 Alcatel Networks CorporationArticle: 28636
--------------25706E7DA74EADA6AEACA0EE Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Chris, you may want to look at an article about crossing asynchronous clock boundaries that I published about a year ago. Mayeb it helps you. http://www.isdmag.com/editorial/2000/design0003.html Peter Alfke, Xilinx Applications ================================ "Chris G. Schneider" wrote: > I want to design an interface between a DSP and a FPGA. The DSP should > be able to access FPGA registers, via the DSP parallel port. The > DSP parallel port has address, data, chip select, read and write lines. > Just the usual stuff. > > I just designed this interface, but I am not happy with the results in > terms of speed and design stability. So I want to ask this audience for > some design hints. > > 1) Write access: I just synchronize the DSP write signal and generate an > internal write strobe to fetch the data. Is it a better solution to use > the write signal to store the data in a register and then synchronize > the register contents to the internal clock? This makes it possible to > detect very short write strobes of the DSP and to reduce the number of > WS, in the application. > > 2) Read access: I use a async. read access at the moment. Is it possible > to make this work synchronously? The problem is that synchronizing just > eats up a lot of time, and timing constraints of modern DSP are pretty > tight. There will be a problem if the FPGA does not release the DSP data > bus fast enough, because read and write accesses can appear very soon > after each other. > > Any suggestions, or literature tips? > > -- > chris --------------25706E7DA74EADA6AEACA0EE Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Chris, you may want to look at an article about crossing asynchronous clock boundaries that I published about a year ago. Mayeb it helps you.<u></u> <p><u><A HREF="http://www.isdmag.com/editorial/2000/design0003.html">http://www.isdmag.com/editorial/2000/design0003.html</A></u> <p>Peter Alfke, Xilinx Applications <br>================================ <br>"Chris G. Schneider" wrote: <blockquote TYPE=CITE>I want to design an interface between a DSP and a FPGA. The DSP should <br>be able to access FPGA registers, via the DSP parallel port. The <br>DSP parallel port has address, data, chip select, read and write lines. <br>Just the usual stuff. <p>I just designed this interface, but I am not happy with the results in <br>terms of speed and design stability. So I want to ask this audience for <br>some design hints. <p>1) Write access: I just synchronize the DSP write signal and generate an <br>internal write strobe to fetch the data. Is it a better solution to use <br>the write signal to store the data in a register and then synchronize <br>the register contents to the internal clock? This makes it possible to <br>detect very short write strobes of the DSP and to reduce the number of <br>WS, in the application. <p>2) Read access: I use a async. read access at the moment. Is it possible <br>to make this work synchronously? The problem is that synchronizing just <br>eats up a lot of time, and timing constraints of modern DSP are pretty <br>tight. There will be a problem if the FPGA does not release the DSP data <br>bus fast enough, because read and write accesses can appear very soon <br>after each other. <p>Any suggestions, or literature tips? <p>-- <br>chris</blockquote> </html> --------------25706E7DA74EADA6AEACA0EE--Article: 28637
erika_uk@my-deja.com wrote: > > hello, > > which provides better performance CMOS or TTL based devices? > I believe that CMOS gives better performance, and it's the CMOS based > devices which are more expensive...but my friend told me the inverse ? > > but what let the better to be better ? > are all fpga based CMOS devise ? > > any input ? The one recent FPGA that I know of that wasn't CMOS was the Dynachip DL5000 series, which was produced in a biCMOS process at IBM - 0.8 um - as usual, if I remember correctly to this whole note. The modules were power-switched and took on the order of 50mW per module; configuration memory was CMOS. Dynachip is now gone and I think Xilinx bought up their intellectual property. Bipolar devices for digital stuff is still used sometimes, but not very often, with biCMOS devices used on interfaces (high impedance when powered off, line drivers/receivers). Some of the newer CMOS devices are now tolerant to I/O voltages higher than the logic supply and are high impedance with power removed (cold sparing) or are capable of hot insertion. I remember "fast" TTL buffer chips taking 0.500 watt each, just idling, with pin to pin delays of like 8 ns! Ouch! ---------------------------------------------------------------------- rk How the hell do I know? I'm just a stellar engineering, ltd. common, ordinary, simple savior of stellare@erols.com.NOSPAM America's destiny. Hi-Rel Digital Systems Design -- Pat PaulsenArticle: 28638
rk wrote: > The one recent FPGA that I know of that wasn't CMOS was the Dynachip > DL5000 series, which was produced in a biCMOS process at IBM - 0.8 um - > as usual, if I remember correctly to this whole note. The modules were > power-switched and took on the order of 50mW per module; configuration > memory was CMOS. > > Dynachip is now gone and I think Xilinx bought up their intellectual > property. > And more importantly, we got their experienced designers, who are now giving us super-fast and versatile I/O designs. Everybody came out a winner: They, we, and you, our Virtex-II customers. Peter Alfke, Xilinx ApplicationsArticle: 28639
> Better yet, let the clock run freely, and use the FPGA to create a > one-clock-period Enable signal when you want to single step. Driven by a simple > state machine in less than one CLB, this is the solution that will give you the > least trouble ( none at all) The disadvantage that I see with a traditional Enable signal is that you have to route it all over the place and the enable logic is often very handy for other things. Here is a suggestion that might avoid that. Start with a 2x clock. Generate the working clock with a FF. Put the enable on that FF. You can do the same thing with a 1x clock and appropriate gates but that depends upon prop times so you will have to work a bit to get it right and convince yourself it is correct. -- These are my opinions, not necessarily my employers. I hate spam.Article: 28640
Hi chris, You dont mention the FPGA vendor for your project. If it was Xilinx, think about the dual-clock FIFO that is available free of charge (CoreLib). It has totaly independent clocks for both sides. ManfredArticle: 28641
Hi folks, has anybody expieriences with the dynamic reconfiguration of Atmel FPGAs ? We have signed a NDA, but information is difficult to get. So does somebody have any C / ASSEMBLER - ROUTINES for MODE 4 Reconfiguration ? Or some hints how to start that ? Any Comments... regards Georg Heinrich Sent via Deja.com http://www.deja.com/Article: 28642
: I am looking at building a small number 10-20 pcbs that will use = one of : Xilinx's FPGAs. The logic required is small but may be expanded = later. : Essentially it is a FPDP i/f feeding some fifos that are feeding a = D/A. :=20 : I am looking initially at a Spartan II for a fifo or DPRAM to hold = some : data for the D/A. : I like the idea of using the block ram for the small DPRAM or fifo. = Speed is : slow by most people's standards on this group. D/A will be run at = 120KSa/s : or so but I am doing : 8 channels + on each FPGA. :=20 You may want to try the Atmel AT40K FPGA family. They have "distribued" 10 ns SRAM suitable for FIFOs. There is a 32 x 4 DPRAM for every 16 macrocell, and they are hardwired, do not use configuration RAM. The AT94Kxx FPSLIC has 12kB of SRAM useable for the FPGA on top of the distributed SRAM.=20 They are pin compatible with the XC4000 series Tools are for free at Atmels homepage. The FPSLIC demoboard will set you back $500 for a 4 months license but then you get really good tools. Mentor Modelsim, Leonardo,Seamless. --=20 Best Regards Ulf at atmel dot com These comment are intended to be my own personal view and may or may not be shared by my Employer Atmel Sweden.Article: 28643
On Thu, 18 Jan 2001 18:35:12 -0800, Peter Alfke <peter.alfke@xilinx.com> wrote: >> Dynachip is now gone and I think Xilinx bought up their intellectual >> property. >> > >And more importantly, we got their experienced designers, who are now >giving us super-fast and versatile I/O designs. >Everybody came out a winner: They, we, and you, our Virtex-II customers. Everyone except DynaChip's customers, possibly. :-( I had a DY8000 design done, ready for fab and poof! ---- KeithArticle: 28644
Hello. I have a problem with programming Virtex (XVC200PQ240) via JTAG Parallel Cable III Model DLC5 and Programmer 3.3.06i. from one of my PC. I receive message: "Communication with the cable could not be established". I have tried with all settings of Parallel Port (lpt 1). On the other computer everything is OK (There is older version of Foundation). On both PC is Windows 98 SE so I think the Parallel Cable is OK. If someone knows what's wrong just write to me. TomaszArticle: 28645
<eml@riverside-machines.com.NOSPAM> wrote in message news:3a675bb8.45182544@news.dial.pipex.com... > On Thu, 18 Jan 2001 11:50:44 -0500, "Jamie Sanderson" > <jamie@nortelnetworks.com> wrote: > > >WinCVS can also you a flat view of the project. > > I haven't found this (I'm on 1.1b16) - can you tell me how do it? I'm using beta 17, but I don't recall if this was a new feature or not. Under the "View" menu, there is an item called "Flat Mode". Selecting that will show you every file in the project in a single listing. > I've never used it - email notification seems a very clunky way to > find out what's going on. It's nice to able to run up the GUI and > immediately see who's doing what. I agree, but it doesn't have to be email. You can execute any command and pass the user name as an argument. All sorts of interesting solutions come to mind, but they are admittedly more work than something built-in to the tool. On the other hand, the fact that you can choose your method of notification is also nice. One could easily send messages to a newsgroup, instead of mail, or even update a web page or database. > >Isn't this what "cvs admin -l" does? > > Maybe admin -l is actually rcs -l, the rcs lock. It all seems very > kludgey - the CVS docs say you're on your own if you use it. Kludgey is the word that comes to everyone's mind. I personally haven't had to find out because I've been able to live without reserved checkouts. For the most part, the admin commands are there for when the proper process fails (like people wanting to correct log messages/descriptions, or deleting revisions). > To each his own. Absolutely! My only goal in replying to the group(s) was to clear up any inaccuracies on what CVS/WinCVS can do, not to say that it's better. Cheers, JamieArticle: 28646
Hi,
got Xilinx Alliance 2.1i running on Solaris.
I'd like to use the CORE Generator, but when i start 'coregen',
no cores are listed in the dirs. Not a single core cell is listed
under the categories "Basic Elements", etc. But the resources.lib
file is full of core refs, i also fetched the latest update from the
Xilinx site.
Read through the User Guide, sec. troubleshooting, but no hint about
this. But when i start coregen with the -d debug flag, i get the
following msgs:
Debug: reading preference file /opt6/xilinx/alliance2.1i/coregen/preferences/coregen_lr.prf
Debug: i18N resource file not found for basename message, defaulting to english text
Debug: Load LibraryManager resources from /opt6/xilinx/alliance2.1i/coregen/ip/resources.lib
Debug: Changing File mode to world write: /opt6/xilinx/alliance2.1i/coregen/preferences/known.prj
Debug: Loaded known Project file /opt6/xilinx/alliance2.1i/coregen/preferences/known.prj
Debug: Parsing Plug-in file: /opt6/xilinx/alliance2.1i/coregen/lib/com/xilinx/encore/util/plugin/fixed.cgd
...[more of this]...
Debug: Parsing Plug-in file: /opt6/xilinx/alliance2.1i/coregen/lib/com/xilinx/encore/util/plugin/sim.eld
Debug: i18N resource file not found for basename gui, defaulting to english text
Debug: Loaded Project file /home/lr/tmp/coregen/coregen.prj
Debug: Loading IP library /opt6/xilinx/alliance2.1i/coregen/ip/xilinx/varmult_v1_0/com/xilinx/ip
Debug: Loading IP library /opt6/xilinx/alliance2.1i/coregen/ip/xilinx/catalog_v1_0/com/xilinx/ip
...[more of this]...
Debug: Loading IP library /opt6/xilinx/alliance2.1i/coregen/ip/xilinx/sincos_v1_0/com/xilinx/ip
Set current Project to /home/lr/tmp/coregen
So the tool loads the resources.lib file and all the IP libraries! But
they don't show up in the GUI. Puuhh, what's goin' on here?
Any help welcome!
Lars
--
Address: University of Mannheim; B6, 26; 68159 Mannheim, Germany
Tel: +(49) 621 181-2716, Fax: -2713
email: larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/
Article: 28647This is a multi-part message in MIME format. --------------5334DB3F45F5CD39B92C0BD0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi all! Does anyone know about a good book or article to understand JTAG and boundary scan? What I've found so far is not really clear... Thanks Attn. Juan --------------5334DB3F45F5CD39B92C0BD0 Content-Type: text/x-vcard; charset=us-ascii; name="jmrivas.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Juan M. Rivas Content-Disposition: attachment; filename="jmrivas.vcf" begin:vcard n:Rivas;Juan M. tel;home:(617)255-1268 tel;work:(617) 253-5097 x-mozilla-html:FALSE org:Media Lab, M.I.T.;Object Based Media version:2.1 email;internet:jmrivas@media.mit.edu title:Research Assistant adr;quoted-printable:;;20 Ames Street=0D=0A;Cambridge;Massachusetts;02139;U.S.A. fn:Juan M. Rivas end:vcard --------------5334DB3F45F5CD39B92C0BD0--Article: 28648
Hi, What FPGAs do support a partial reconfiguration? What FPGAs can be reconfigured "on-the-fly"? Is this possible to use this feature with a tool? Thank you, Pawel Sent via Deja.com http://www.deja.com/Article: 28649
Andy, We have IBIS models. See the web page. For those real power users who want to use DCI at 65 ohms, or 35 ohms, we have IBIS models for those as well. Since the IBIS models for DCI's at any impedance is just silly, we picked about 6 different system impedances to cover the cases. If you are concerned about 68 ohms, and we have a model for 65 ohms, then I think you need to seriously consider going to an SI class (to learn what is important, and what is not). If you need impedances for systems other than 50 ohms, contact your FAE to obtain the IBIS models. We may also place these on the web if there is a lot of demand for them. It really is a tremendous amount of work that we had to do to get ready for this release. I hope someone somewhere appreciates that we thought of these things. By the way, good catch. Thought you had us, didn't you? We are not perfect (!!!! especially me), so if we do miss something, tell us right away, On a practical note, making impedances higher than 50 ohms is almost impossible today (lines too skinny to fab), and lower than 50 ohms takes up too much room. The ULVDS specification just got changed from 60 ohms to 50 ohms because of that. Austin Andy Peters wrote: > Austin Lesea wrote: > > > > Bob, > > > > The impedance updates are asynchronous, and are done in such a manner that > > the updates trim values are all extremely small. The resultant dR/dt is > > undetectable in the signal integrity of the output. > > How will you handle the variable impedances in the IBIS models? > > Please tell me you'll have IBIS models ... > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u > > "It is better to be silent and thought a fool, > than to send an e-mail to the entire company > and remove all doubt."
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