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Smith wrote: > Hello all > > I need to run an old firmware for a Siemens SAB 80C537 microcontroller > unit (MCU). The MCU is now obsolete (it's from the late 1980s). Perhaps a brief explanation of why might have been useful. Need to make some more old units, need to upgrade for a newer product? > The firmware is compiled from several thousand rows of assembly language. > It would take a long time to understand the code and re-program it in C. One application I did many years ago was all hand-coded 6800 machine code. About 4k of it. This was input to the system by the switch and step method. So in an actual assembler, this should not be too much of a hassle even if the code is 2 or 3 times that size. > So I'm thinking of using an 8051 IP-core for a FPGA and run the firmware > code without any changes to the code. Others have indicated that the parts are available from at least one stockist. Unless you need special certification of the parts that would seem to be the way to go to make more of an old product. On the other hand, if this is an update of the product-line then it would be much wiser to bite the bullet and select a more recent part offering that gives you the facilities you need. Then set to and understand the assembly code listing so that you can re-work the system and improve it as you go. -- ******************************************************************** Paul E. Bennett...............<email://Paul_E.Bennett@topmail.co.uk> Forth based HIDECS Consultancy Mob: +44 (0)7811-639972 Tel: +44 (0)1235-510979 Going Forth Safely ..... EBA. www.electric-boat-association.org.uk.. ********************************************************************Article: 147226
On 4/19/2010 11:48 AM, Rumpelstiltskin wrote: > > "Smith" <smith@donotwantmail.com> wrote in message > news:4bcc6082$0$45179$afc38c87@read01.usenet4all.se... >> Hello all >> I need to run an old firmware for a Siemens SAB 80C537 microcontroller >> unit (MCU). The MCU is now obsolete (it's from the late 1980s). >> >> The firmware is compiled from several thousand rows of assembly >> language. It would take a long time to understand the code and >> re-program it in C. >> >> So I'm thinking of using an 8051 IP-core for a FPGA and run the >> firmware code without any changes to the code. >> >> Any one here had any luck with this kind of problem? > > I'd try tweaking firmware first. Looks like this one is not standard > 8051 deriviative. > Has 32bit math MDU and 8 DPTR registers. > > First thing I'd do is see if these odd features are being used. > If not, it would be easy to port to another 8051 derivative. > If so, porting challenge could range from a minor hassle to impossible. > Then C port might be way to go. > > I'd get a good firmware engineer to evaluate code before moving forward. > > From the Keil web site: The Infineon SAB 80C537 is an 8051 based CMOS controller with 21ch PWM, 8 DPTRs, WDT, 12ch ADC/8, Mul./Div Unit, 68 I/O lines, 4 Timers/Counters, 14 Interrupts/4 priority levels ROM-less, 256 Bytes On-chip RAM. Talk about job security !!! ;-) hamiltonArticle: 147227
wert wrote: > hi all > I have a strange problem during FPGA working.PROM files can be dowmloaded > to Configuration flash XCF32P successfully,level of Dedicated > configuration pins DONE and INIT_B is both high,FPGA works normally. > But after a time FPGA can not works,level of pin DONE changes to be low!! > level of pin INIT_B changes to be also low sometimes. I am at a loss. About the only way this can happen is if the PROG line changes state, or the power supply drops below the minimum level. So, check the stability of the power supply and whether you have PROG maintained in the inactive logic level at all times. JonArticle: 147228
In message <4bcc6082$0$45179$afc38c87@read01.usenet4all.se>, Smith <smith@donotwantmail.com> writes >Hello all >I need to run an old firmware for a Siemens SAB 80C537 microcontroller unit >(MCU). The MCU is now obsolete (it's from the late 1980s). I know I have some here... >The firmware is compiled from several thousand rows of assembly language. It >would take a long time to understand the code and re-program it in C. But that may be the cheaper option. Yes, I have done it before. >So I'm thinking of using an 8051 IP-core for a FPGA and run the firmware >code without any changes to the code. You can't do it. Simple as that. There are some 50+ 8051 cores. All different. From the standard 12 to 1 cycle systems. On top of that they had different peripherals. So once you get your core, tune it to be the same as the one Siemens used you then have to get all the peripherals and get them to be have exactly as Siemens did. Then bolt them together. The faster and cheaper option by far is to reverse engineer the code. Why do you need to run this firmware? If you need to do 100-200 units to do the same thing go and get a cheap modern core with the same peripheral set. And start again. This will be faster, more reliable and cheaper. -- \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ \/\/\/\/\ Chris Hills Staffs England /\/\/\/\/ \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/Article: 147229
On Apr 19, 1:03=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Apr 19, 9:49=A0am, chrisdekoh <chrisde...@gmail.com> wrote: > > > Hi, > > > does anyone know if there is such a thing as clock IO for Xilinx > > FPGA?? If i were to design my own PCB board with an FPGA on it, do i > > necessarily have to route the clock from the on-board oscillator > > directly only to the clock IO pins? > > > din consider this before, but thought i get some opinions to be sure > > > thanks > > Chris > > Yes, certain pins are defined as clock pins. =A0You need to read the > "Package and Pinout User Guide" for the specific family that you are > using for more information. > > Ed McGettigan > -- > Xilinx Inc. You really need to read the clocking section of the main user guide for your FPGA family. This describes the types of clock pins and any routing considerations. Many newer FPGA families have regional as well as global clock resources. Also many have pins that are labeled as global clock, but can only be used as the negative half of a differential clock pair. Furthermore some FPGA's have limitations routing clocks from the same edge due to limited buffer resources. This is one case where it really helps to try to build a design before locking down the pinout of your board. Regards, Gabor PS - Any pin of a Xilinx FPGA can be a clock source if you are willing to use non-dedicated routing from the pin to the clock buffer. This sort of connection should be used only as a last resort as the non-dedicated route has a large delay component that depends on voltage temperature and process. That being said, if your clock is just an oscillator that goes nowhere else in the system (i.e. you have no signals that are phase related to the clock coming into your FPGA) you can use any pin.Article: 147230
On Apr 19, 7:18=A0pm, Andy <jonesa...@comcast.net> wrote:
> On Apr 14, 3:23=A0pm, Jan Decaluwe <j...@jandecaluwe.com> wrote:
>
> > Seriously, that's why conversion to VHDL/Verilog gets so much
> > attention. It allows you to view MyHDL simply as a more effective
> > or fun way to create your trusted VHDL/Verilog design.
>
> > Therefore, no need to ask nor tell anyone. If you're intrigued,
> > just do it, and do it as a good engineer: start with a simple
> > but relevant module, not with a whole design. After conversion,
> > few will be able to tell (you may even get praise for the
> > code quality :-)).
>
> And do what? Be forced into a design/coding paradigm that is the least
> common denominator of verilog and vhdl?
Not necessarily, because conversion happens after elaboration
by the Python interpreter, and because MyHDL's type system
for RTL is at a more abstract level.
> No thanks, I don't need or want another code generator.
Sure, don't bother if it doesn't solve a real problem
for you. Just let it be an informed decision.
Please: don't call it code generation. It's essentially a
powerful HDL with strong conversion capabilities.
Also, last time I forgot to mention that there actually is
commercial support (though it may not be expensive enough
to impress you :-))
http://www.myhdl.org/doku.php/support
> Code conversion is only applicable if you never have to read it or
> maintain it in its converted form. I can't rely on myhdl in order to
> maintain the source.
I wouldn't know why not. You can even maintain equivalent VHDL and
Verilog simultanuously. What other technology can do that?
Jan
Article: 147231On Apr 20, 1:53=A0am, "Smith" <sm...@donotwantmail.com> wrote: > Hello all > > I need to run an old firmware for a Siemens SAB 80C537 microcontroller un= it > (MCU). The MCU is now obsolete (it's from the late 1980s). > > The firmware is compiled from several thousand rows of assembly language.= It > would take a long time to understand the code and re-program it in C. > > So I'm thinking of using an 8051 IP-core for a FPGA and run the firmware > code without any changes to the code. > > Any one here had any luck with this kind of problem? First, I'd try and source the real silicon. An FPGA will lack the peripherals, and lacks the Analog options, so a precise clone will be _very_ difficult. Failing getting the silicon, there are other, newer, parts with similar resources, including newer Infineon parts. Do you have the ASM source ? How much code space, and is a move to on-chip code ok ? -jgArticle: 147232
Hi, Can anyone tell me whether the Xilinx Pipelined FFT arch uses R2SDF or R2^2SDF? Regards, Onkar --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147233
All the abstraction is gone when you convert to VHDL/Verilog, rather than trying to represent the abstraction intact as much as possible in the copnverted code (significant in VHDL, not so much in Verilog). Without a proven, supported tool chain I cannot depend on maintaining code in the MyHDL domain. Therefore, I have to use it only as a code generator, and be able to maintain the generated VHDL/Verilog code in case said tool goes away (with all the limitations inherent in the converted code). If I started out in VHDL, the VHDL would be much more maintainable. I'll look into the support link you provided, but until a major synthesis tool supports it directly, I can't say that it would make any difference. Your definition of maintaining equivalent VHDL and Verilog is only through the as-yet-unsupported language. That's not maintenance in my book. It may work for commercial products that are here and gone in a year or two, but in my business, support is measured in decades. All this said, I am attracted to MyHDL as an academic exercise (even though I hate some of the syntactic baggage, especially ".next"), not as a useable tool in my professional environment. At least not yet... AndyArticle: 147234
On Apr 12, 8:24=A0pm, luudee <rudolf.usselm...@gmail.com> wrote: > On Apr 1, 12:04=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > On Mar 31, 1:51=A0am, luudee <rudolf.usselm...@gmail.com> wrote: > > > > Does anybody else, besides xilinx, make FMC boards for ml605 & sp605 = ? > > > > HW-FMC-XM105-G =A0FMC XM105 DEBUG CARD > > > HW-FMC-XM104-G =A0FMC CONNECTIVITY MEZZANINE CARD > > > > Buying Xilinx products now means going through Avnet, which is a > > > nightmare and HUGE lead times ... > > > > Thanks, > > > rudi > > > While the XM104 is listed with a 8 week lead time on the Avnet site, I > > know that we have these available in inventory and they will ship > > promptly after the order is placed. =A0The XM105 is listed with a 2 wee= k > > lead time. > > > There are a number of other companies releasing FMC cards, just be > > sure that the cards support a VADJ of 2.5V and there shouldn't be a > > problem. > > > 4DSP recently announced a FMC familyhttp://www.przoom.com/news/66794/ > > > Curtiss-Wright also has a number of boards.http://www.cwcembedded.com/0= /62/651.html > > > And Xilinx has a number of other boards in pipeline to be released > > next quarter.http://www.xilinx.com/fmc > > > Ed McGettigan > > -- > > Xilinx Inc. > > Ed, > > just an update ... > > I ordered the above two boards through Avnet on April 1st. > > As of today (April 12th), they are still listed as on "back order" > with 2 & 8 week lead times. > > Is there an alternative way to buy these boards ? We are an > alliance partner if makes any difference ... > > Thanks, > rudi@i_hate_avnet.suck UPDATE 2 today I got an email that the XM105 shipped (alone). I SPECIFICALLY checked that the boards be shipped together. The board is $159 USD, shipping is $55 USD. No word when the XM104 will ship. Another AVnet disaster .... rudiArticle: 147235
Eric, I would also recommend the following resources: 1) Read the PCI Express specification, if you can get access to it: http://www.pcisig.com/specifications/pciexpress/specifications/ 2) Intel Press has a very good book on PCI Express: http://www.intel.com/intelpress/sum_pciexpress.htm Hakan Linera - http://www.linera.com.trArticle: 147236
max wrote: > Hello, hi, > what i need for programming,reading etc a XILINX XC2018 44PLCC ?What > is the good tool? > I need a toll for repairing old boards that have the XC2018 on board, Someone here (not me) is selling his "legacy tools" : http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=290426137491 it is rather worthless, unless one has an IC museum, OR if someone is in your position : in fact that's the best solution. Just get it, it makes business sense (unless you're asked to repair old boards for free) Note : get an old PC (like, 486 or Pentium) to run this, and install the usual MS-DOS environment. > Thanks good luck and don't forget to bid, yg -- http://ygdes.com / http://yasep.orgArticle: 147237
Hello, what i need for programming,reading etc a XILINX XC2018 44PLCC ?What is the good tool? I need a toll for repairing old boards that have the XC2018 on board, ThanksArticle: 147238
You need a VERY OLD xilinx tools from the 90s. Xilinx M1 probably works. None of the new ISE versions support 2000 series, some older ones (4.2 and older) supporter 4000 series, but nothing as old as xc2018. --- frmsrcurl: http://compgroups.net/comp.arch.fpga/Developin-tool-for-Xilinx-XC2018Article: 147239
In addition to what others have suggested you might also be able to use a PLCC adaptor and use that to piggyback a modern FPGA. Companies like Enterpoint and OHO Electronik might be able to make one of these modules for you. http://www.enterpoint.co.uk/component_replacements/craignell.html http://www.oho-elektronik.de/index.php?c=1&s=product1 Hans www.ht-lab.com "max" <ciulandro@yahoo.com> wrote in message news:1d4a4320-7e52-4598-af30-99de67b254c8@a9g2000vbb.googlegroups.com... > Hello, > > what i need for programming,reading etc a XILINX XC2018 44PLCC ?What > is the good tool? > I need a toll for repairing old boards that have the XC2018 on board, > > > ThanksArticle: 147240
Altera clearly mentions that their pipelined FFT core uses R2^2SDF architecture. But I could not find any such info about Xilinx -- can anyone help? Onkar >Hi, > >Can anyone tell me whether the Xilinx Pipelined FFT arch uses R2SDF or >R2^2SDF? > >Regards, >Onkar > > > >--------------------------------------- >Posted through http://www.FPGARelated.com > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147241
Hi All, I've recently published a paper exploring how to implement memories with multiple read and write ports on existing FPGAs. I figured it might be of interest to some. Summary, paper, slides, and example code are here: http://www.eecg.utoronto.ca/~laforest/multiport/index.html There are no patents or other additional IP encumbrances on the code. If you have any comments or other feedback, I'd like to hear it. Eric LaForest PhD student, ECE Dept. University of Toronto http://www.eecg.utoronto.ca/~laforest/Article: 147242
On Apr 20, 4:44=A0am, max <ciulan...@yahoo.com> wrote: > Hello, > > what i need for programming,reading etc a XILINX =A0XC2018 44PLCC =A0?Wha= t > is the good tool? > I need a toll for repairing old boards that have the XC2018 on board, > > Thanks If you are -repairing- boards, you do not need a programmer or reader. What you need is a supply of parts (and good luck with that). If you are -modifying- boards, your best bet (ref HT-LAB) is to replace the 2018 with something that you can actually use. It could probably be replaced with a modern CPLD. RKArticle: 147243
We have the Raggedstone2 in test now and expect to start shipping this board shortly. Picture of complete board is now on http://www.enterpoint.co.uk/raggedstone/raggedstone2.html. There should be some more support materials appearing over the next 1-2 weeks. John Adair Enterpoint Ltd.Article: 147244
I guess Xilinx also uses R2^2SDF --- because they have scaling for every pair of radix 2 butterflies. > >Altera clearly mentions that their pipelined FFT core uses R2^2SDF >architecture. >But I could not find any such info about Xilinx -- can anyone help? > >Onkar > >>Hi, >> >>Can anyone tell me whether the Xilinx Pipelined FFT arch uses R2SDF or >>R2^2SDF? >> >>Regards, >>Onkar >> >> >> >>--------------------------------------- >>Posted through http://www.FPGARelated.com >> > >--------------------------------------- >Posted through http://www.FPGARelated.com > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147245
On Apr 17, 7:17=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > In comp.arch.fpga rickman <gnu...@gmail.com> wrote: > (snip on test benches) > > >> I suppose so, but consider it the other way around. > >> If your test bench is good enough then it will catch all static > >> timing failures (eventually). ?With static timing analysis, there > >> are many things that you don't need to check with the test bench. > > I don't follow what you are saying. =A0This first sentence seems to be > > saying that a timing simulation *is* a good place to find timing > > problems, or are you talking about real world test benches? =A0The poin= t > > is that static timing is enough to catch all timing failures given > > that your timing constraints cover the design properly... and I agree > > that is a big given. =A0Your second sentence seems to be agreeing with > > my previous statement. > > Yes, I was describing real world (hardware) test benches. > > Depending on how close you are to a setup/hold violation, > it may take a long time for a failure to actually occur. That is the point. Finding timing violations in a simulation is hard, finding them in physical hardware is not possible to do with any certainty. A timing violation depends on the actual delays on a chip and that will vary with temperature, power supply voltage and process variations between chips. I had to work on a problem design once because the timing analyzer did not work or the constraints did not cover (I firmly believe it was the tools, not the constraints since it failed on a number of different designs). We tried finding the chip that failed at the lowest temperature and then used that at an elevated temperature for our "final" timing verification. Even with that, I had little confidence that the design would never have a problem from timing. Of course on top of that the chip was being used at 90% capacity. This design is the reason I don't work for that company anymore. The section head knew about all of these problems before he assigned the task and then expected us to work 70 hour work weeks. At least we got them to buy us $100 worth of dinner each evening! The point is that if you don't do static timing analysis (or have an analyzer that is broken) timing verification is nearly impossible. > >> Also, you can't do static timing analysis on the implemented logic. > >> (That is, given an actual built circuit and a logic analyzer.) > > So? > >> Now, setup and hold violations are easy to test with static > >> analysis, but much harder to check in actual logic. ?Among others, > >> you would want to check all possible clock skew failures, which is > >> normally not possible. ?With the right test bench and logic > >> implementation (including programmable delays on each FF clock) > >> it might be possible, though. > > In twenty years of designing with FPGAs I have never found a clock > > skew problem. =A0I always write my code to allow the clock trees to > > deliver the clocks and I believe the tools guaranty that there will > > not be a skew problem. =A0Static timing actually does cover clock skew, > > at least the tools I use. > > Yes, I was trying to cover the case of not using static timing > analysis but only testing actual hardware. =A0For ASICs, it is > usually necessary to test the actual chips, though they should > have already passed static timing. =A0 If you find a timing bug in the ASIC chip, isn't that a little too late? Do you test at elevated temperature? Do you generate special test vectors? How is this different from just testing the logic? > > BTW, how do you design a "right test bench"? =A0Static timing analysis > > will at least give you the coverage level although one of my > > complaints is that they don't provide any tools for analyzing if your > > constraints are correct. =A0But I have no idea how to verify that my > > test bench is testing the timing adequately. > > If you only have one clock, it isn't so hard. =A0As you add more, > with different frequencies and/or phases, it gets much harder, > I agree. =A0It would be nice to get as much help as possible > from the tools. The number of clocks is irrelevant. I don't consider timing issues of crossing clock domains to be "timing" problems. There you can only solve the problem with proper logic design, so it is a logic problem. RickArticle: 147246
On Apr 16, 4:38=A0am, David Brown <da...@westcontrol.removethisbit.com> wrote: > The old joke about Ada is that when you get your code to compile, it's > ready to ship. =A0I certainly wouldn't go that far, but testing is > something you do in cooperation with static checking, not as an alternati= ve. GOOD static checking tools are great (and IMHO part of a testbench). I certainly hope you're not trying to imply that the typechecking built into VHDL is a substitute for a good model checker! Regards, PatArticle: 147247
On Apr 10, 8:21=A0pm, Jan Decaluwe <jandecal...@gmail.com> wrote: > On Apr 9, 6:53=A0pm, Patrick Maupin <pmau...@gmail.com> wrote: > > > > > On Apr 9, 9:07=A0am, rickman <gnu...@gmail.com> wrote: > > > > I think I have about had it with VHDL. =A0I've been using the > > > numeric_std library and eventually learned how to get around the > > > issues created by strong typing although it can be very arcane at > > > times. =A0I have read about a few suggestions people are making to he= lp > > > with some aspects of the language, like a selection operator like > > > Verilog has. =A0But it just seems like I am always fighting some aspe= ct > > > of the VHDL language. > > > > I guess part of my frustration is that I have yet to see where strong > > > typing has made a real difference in my work... at least an > > > improvement. =A0My customer uses Verilog and has mentioned several ti= mes > > > how he had tried using VHDL and found it too arcane to bother with. > > > He works on a much more practical level than I often do and it seems > > > to work well for him. > > > > One of my goals over the summer is to teach myself Verilog so that I > > > can use it as well as I currently use VHDL. =A0Then I can make a full= y > > > informed decision about which I will continue to use. =A0I'd apprecia= te > > > pointers on good references, web or printed. > > > > Without starting a major argument, anyone care to share their feeling= s > > > on the differences in the two languages? > > > > Rick > > > The best online references are the Sutherland Verilog references. > > There is an online HTML reference for Verilog 95 (excellent), and a > > PDF for Verilog 2001 (good): > > >http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.h...= ... > > > Cliff Cummings has a lot of good papers on Verilog at his site: > > >http://sunburst-design.com/papers/ > > > In particular, if you read and carefully grok his paper about non- > > blocking vs. blocking assignments, you will be well on your way to > > being a Verilog wizard: > > >http://sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf > > The infamous Guideline #5 bans variable semantics from always blocks > with sequential logic. It must be the Worst Guideline ever for RTL > designers. > The result is not wizardry but ignorance. > > How are we supposed to "raise the abstraction level" if Verilog RTL > designers > can't even use variables? I didn't notice this post until today. I think you are completely misreading the guidelines if you think they mean "Verilog RTL designers can't even use variables" Regards, PatArticle: 147248
In comp.arch.fpga rickman <gnuarm@gmail.com> wrote: > On Apr 17, 7:17?pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: (snip on test benches) >> Yes, I was describing real world (hardware) test benches. >> Depending on how close you are to a setup/hold violation, >> it may take a long time for a failure to actually occur. > That is the point. Finding timing violations in a simulation is hard, > finding them in physical hardware is not possible to do with any > certainty. A timing violation depends on the actual delays on a chip > and that will vary with temperature, power supply voltage and process > variations between chips. But they have to be done for ASICs, and all other chips as part of the fabrication process. For FPGAs you mostly don't have to do such, relying on the specifications and that the chips were tested appropriately in the factory. > I had to work on a problem design once > because the timing analyzer did not work or the constraints did not > cover (I firmly believe it was the tools, not the constraints since it > failed on a number of different designs). We tried finding the chip > that failed at the lowest temperature and then used that at an > elevated temperature for our "final" timing verification. Even with > that, I had little confidence that the design would never have a > problem from timing. Of course on top of that the chip was being used > at 90% capacity. This design is the reason I don't work for that > company anymore. The section head knew about all of these problems > before he assigned the task and then expected us to work 70 hour work > weeks. At least we got them to buy us $100 worth of dinner each > evening! One that I worked with, though not at all at that level, was a programmable ASIC (for a systolic array processor). For some reason that I never knew the timing was just a little bit off regarding to writes to the internal RAM. The solution was to use two successive writes, which seemed to work. In the usual operation mode, the RAM was initialized once, so the extra cycle wasn't much of a problem. There were also some modes where the RAM had to be written while processing data, such that the extra cycle meant that the processor ran that much slower. > The point is that if you don't do static timing analysis (or have an > analyzer that is broken) timing verification is nearly impossible. And even if you do, the device might still have timing problems. (snip) >> Yes, I was trying to cover the case of not using static timing >> analysis but only testing actual hardware. ?For ASICs, it is >> usually necessary to test the actual chips, though they should >> have already passed static timing. ? > If you find a timing bug in the ASIC chip, isn't that a little too > late? Do you test at elevated temperature? Do you generate special > test vectors? How is this different from just testing the logic? It might be that it works at a lower clock rate, or other workarounds can be used. Yes, it is part of testing the logic. (snip) >> If you only have one clock, it isn't so hard. ?As you add more, >> with different frequencies and/or phases, it gets much harder, >> I agree. ?It would be nice to get as much help as possible >> from the tools. > The number of clocks is irrelevant. I don't consider timing issues of > crossing clock domains to be "timing" problems. There you can only > solve the problem with proper logic design, so it is a logic > problem. Yes, there is nothing to do about asynchronous clocks. It just has to work in all cases. But in the case of supposedly related clocks, you have to verify it. There are designs that have one clock a multiple of the other clock frequency, or multiple phases with specified timing relationship. Or even single clocks with specified duty cycle. (I still remember the 8086 with its 33% duty cycle clock.) With one clock you can run combinations of voltage, temperature, and clock rate, not so hard but still a lot of combinations. With related clocks, you have to verify that the timing between the clocks works. -- glenArticle: 147249
On Apr 20, 11:46=A0pm, Patrick Maupin <pmau...@gmail.com> wrote: > On Apr 10, 8:21=A0pm, Jan Decaluwe <jandecal...@gmail.com> wrote: > > > > > On Apr 9, 6:53=A0pm, Patrick Maupin <pmau...@gmail.com> wrote: > > > > On Apr 9, 9:07=A0am, rickman <gnu...@gmail.com> wrote: > > > > > I think I have about had it with VHDL. =A0I've been using the > > > > numeric_std library and eventually learned how to get around the > > > > issues created by strong typing although it can be very arcane at > > > > times. =A0I have read about a few suggestions people are making to = help > > > > with some aspects of the language, like a selection operator like > > > > Verilog has. =A0But it just seems like I am always fighting some as= pect > > > > of the VHDL language. > > > > > I guess part of my frustration is that I have yet to see where stro= ng > > > > typing has made a real difference in my work... at least an > > > > improvement. =A0My customer uses Verilog and has mentioned several = times > > > > how he had tried using VHDL and found it too arcane to bother with. > > > > He works on a much more practical level than I often do and it seem= s > > > > to work well for him. > > > > > One of my goals over the summer is to teach myself Verilog so that = I > > > > can use it as well as I currently use VHDL. =A0Then I can make a fu= lly > > > > informed decision about which I will continue to use. =A0I'd apprec= iate > > > > pointers on good references, web or printed. > > > > > Without starting a major argument, anyone care to share their feeli= ngs > > > > on the differences in the two languages? > > > > > Rick > > > > The best online references are the Sutherland Verilog references. > > > There is an online HTML reference for Verilog 95 (excellent), and a > > > PDF for Verilog 2001 (good): > > > >http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.h.= ..... > > > > Cliff Cummings has a lot of good papers on Verilog at his site: > > > >http://sunburst-design.com/papers/ > > > > In particular, if you read and carefully grok his paper about non- > > > blocking vs. blocking assignments, you will be well on your way to > > > being a Verilog wizard: > > > >http://sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf > > > The infamous Guideline #5 bans variable semantics from always blocks > > with sequential logic. It must be the Worst Guideline ever for RTL > > designers. > > The result is not wizardry but ignorance. > > > How are we supposed to "raise the abstraction level" if Verilog RTL > > designers > > can't even use variables? > > I didn't notice this post until today. =A0I think you are completely > misreading the guidelines if you think they mean "Verilog RTL > designers can't even use variables" I use that line as a shorthand for "Guideline #5 combined with Guideline #1, if taken seriously, forbids the use of traditional variable semantics provided by blocking assignments, in the context of a clocked always block". No matter how absurd I hope this sounds to you, that's really what it says. Jan
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