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Messages from 157775

Article: 157775
Subject: Re: Multicycle paths using clock enable (in Synplify Pro)
From: "kaz" <37480@embeddedrelated>
Date: Fri, 13 Mar 2015 08:46:45 -0500
Links: << >>  << T >>  << A >>

I don't know about Synplify but this is an altera timequest example
(timequest resource 
center)

set_multicycle_path 2 -to [get_fanouts [get_pins enable_reg|q*] 
-through [get_pins -hierarchical *|*ena*]] -end -setup

set_multicycle_path 1 -to [get_fanouts [get_pins enable_reg|q*] 
-through [get_pins -hierarchical *|*ena*]] -end –hold


Kaz	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 157776
Subject: Re: code c of HM5883
From: Tim Wescott <seemywebsite@myfooter.really>
Date: Fri, 13 Mar 2015 13:15:48 -0500
Links: << >>  << T >>  << A >>
On Thu, 12 Mar 2015 08:43:01 -0500, didaSofi wrote:

> good morning I want a  code  C for reading and writing of i2c  for the
> HM5883 sensor.
> best regards
> 					
> ---------------------------------------
> Posted through http://www.FPGARelated.com

I doubt you'll get a good answer on this, for several reasons:

1: This is an FPGA group, and yours is an embedded programming question --
   at least, doing it in 'C' implies that you'll be running the thing
   on a processor.

2: Code like that is highly specific to the processor and the peripheral,
   so you'd need to luck out with someone who's done it and can share --
   and you didn't say what your processor is.

3: Code like that is also highly specific to the problem to be solved,
   unless someone really went all out to make generic code.

4: If you know what you're doing, it usually takes less time to write code
   like that than it takes to use someone else's.  If you don't know what
   you're doing, then someone else's code won't help you.

This sounds harsh, but I think you need to either learn how to do the work 
yourself, or you need to hire someone to do it for you -- and if you hire, 
given the level of competence implied by your question, you probably want 
to hire someone to do the WHOLE project, for reason 4 stated above.

The only halfway point that I can see in this is if you own a business and 
want to hire someone to both do the work and teach you, or if you're a 
trusted employee and your boss is willing to hire someone to do the work 
and teach you (which will cost him more the one time, and less in the 
future if you're trainable and loyal).

If you DO decide to do the work, and want help doing it, then try posting 
a question on comp.arch.embedded (which you can do via 
embeddedrelated.com).  Give it a title like "Interfacing to an I2C 
Sensor", and a first line like "I need to interface an XXX processor to a 
HM5883 YYY (gyro, accel, temperature -- whatever it is) sensor from ZZZ 
(i.e. -- what company?).  I've never done I2C before and I'm lost".  Don't 
expect someone to do your work for you -- expect people to helpfully point 
your way.  If you're polite and humble, someone will help you.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Article: 157777
Subject: Re: New invention: Systematic method of coding wave pipelined
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Fri, 13 Mar 2015 22:48:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Tuesday, February 24, 2015 at 10:14:20 AM UTC-8, Weng Tianxiang wrote:
> Hi Jim, glen, JK, rickman, Mike, Andy,=20
>=20
> I have filed a provisional patent application: "Systematic method of codi=
ng wave pipelined circuits in HDL". If it is proved correct, the patent wil=
l introduce 1 keyword, 3 permanent constants, 1 concurrent statement and fo=
ur source code modules for a new library in HDL and thoroughly resolve a pe=
nding problem so that every digital designer can code wave-pipelined circui=
ts in HDL.=20
>=20
> Here is the abstract of the invention:=20
>=20
>     The present invention classifies all critical paths into two basic ty=
pes: a series critical path and a feedback critical path, and divides each =
of wave-pipelined circuits into two components: a static logic part, called=
 critical path component (CPC), and a dynamic logic part, formalized into f=
our wave-pipelining components (WPC) shared by all wave-pipelined circuits.=
 Each wave-pipelining ready code in HDL comprises two components: a WPC ins=
tantiation and a CPC instantiation wire-connected and linked by a new link =
statement. Each WPC has new wave constants which play the same role as gene=
ric constants do, but whose initial values are determined and assigned by a=
 synthesizer after code analysis, so designers can use after-synthesization=
 information in their code before synthesization for wave-pipelining techno=
logy. The responsibility of analyzing and manipulating wave-pipelining read=
y code, generating and implementing wave-pipelined circuits on a design-wid=
e or chip-wide scale in HDL is shifted from designers to synthesizers.=20
>=20
> Anyone who are interested in its content is welcome to send a email reque=
st to the following email address: wtx wtx @ gmail . com with title "System=
atic" and he will receive the full documents: one specification, 9 drawings=
 and one text file in VHDL.=20
>=20
> If one reviews the files and feels that it would be a good thing to recom=
mend the application to his company to buy it, the first person to do it af=
ter his recommended company does so will receive $10,000 commission fee.=20
>=20
> All people who are interested in the topics are better to refer the same =
topics in VHDL group, because its example source code is in VHDL and it can=
not not be implemented in any FPGA chip.
>=20
> https://groups.google.com/forum/#!forum/comp.lang.vhdl
>=20
> Thank you.=20
>=20
> Weng

The invention is really a good example of showing how a complicated problem=
 is resolved by creative ideas.

Weng

Article: 157778
Subject: Re: DDS
From: "mnentwig" <24789@embeddedrelated>
Date: Sat, 14 Mar 2015 16:39:06 -0500
Links: << >>  << T >>  << A >>
Hi Rick,

when the critical path of an operation is x cycles long, you have a choice
that includes the options of 
a) utilizing your hardware 1 cycle out of x cycles, effectively wasting
(x-1) cycles
and 
b) pipelining x independent operations and utilizing the hardware x cycles
out of x.

For higher-order polynomial interpolation, x is relatively high (say, 20
cycles), that's where pipelining comes in in the context of this thread
(multi-channel DDS).

With regard to the equation, if you can't disentangle it, please start a
new thread. It is an example describing an arbitrary chirp function, which
is off-topic for this discussion, other than pointing out the line where to
put your desired function into my matlab script.
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 157779
Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL
From: "kaz" <37480@embeddedrelated>
Date: Sun, 15 Mar 2015 04:00:40 -0500
Links: << >>  << T >>  << A >>
If I understood you:
wave pipelining (for fabric section of fpga) depends on weird recoding as
well as fitter 
taking care of minimum and maximum delays.

at i/o it is already done regularly when one or more clocks are allowed for
capture.

How do you direct fitter to care for minimum delays?

Kaz	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 157780
Subject: Re: Handel-C to VHDL
From: princesse91 <safsoufa.msk@gmail.com>
Date: Mon, 16 Mar 2015 20:58:35 -0500
Links: << >>  << T >>  << A >>
Hi Ahmed,
Can you tell me how did you generate VHDL from Handel-C?? I'm working on the conversion from c++ to vhdl with handel-c but i didn't know how to do it..
Thanks



Article: 157781
Subject: Re: Multicycle paths using clock enable (in Synplify Pro)
From: karl-heinz.rossmann@liebherr.com
Date: Tue, 17 Mar 2015 05:29:50 -0700 (PDT)
Links: << >>  << T >>  << A >>
Am Freitag, 13. M=E4rz 2015 14:46:51 UTC+1 schrieb kaz:
> I don't know about Synplify but this is an altera timequest example
> (timequest resource=20
> center)
>=20
> set_multicycle_path 2 -to [get_fanouts [get_pins enable_reg|q*]=20
> -through [get_pins -hierarchical *|*ena*]] -end -setup
>=20
> set_multicycle_path 1 -to [get_fanouts [get_pins enable_reg|q*]=20
> -through [get_pins -hierarchical *|*ena*]] -end -hold
>=20
>=20
> Kaz	  =20
> 				=09
> ---------------------------------------	=09
> Posted through http://www.FPGARelated.com

Hello Kaz,
thank you for your example. Unfortunately the command "get_fanouts" is not =
available within Synplify. In the meantime I have developed a semi-automati=
c approach by using the TCL command "expand". I am generating a list of seq=
uential modules which are enabled by specific clock enable signal:
expand -hier -from {n:*CE*} -seq
With the help of a few editor macros I am building the timing contraints fi=
le. And it works!

Article: 157782
Subject: Re: DDS
From: rickman <gnuarm@gmail.com>
Date: Fri, 20 Mar 2015 13:01:48 -0400
Links: << >>  << T >>  << A >>
On 3/14/2015 5:39 PM, mnentwig wrote:
> Hi Rick,
>
> when the critical path of an operation is x cycles long, you have a choice
> that includes the options of
> a) utilizing your hardware 1 cycle out of x cycles, effectively wasting
> (x-1) cycles
> and
> b) pipelining x independent operations and utilizing the hardware x cycles
> out of x.

Where did these cycles come from?  Logic takes some amount of time to 
process.  I can make my clock cycles match my logic if I choose.  I'm 
not sure where you are going with this.  I believe we all understand 
pipelining.


> For higher-order polynomial interpolation, x is relatively high (say, 20
> cycles), that's where pipelining comes in in the context of this thread
> (multi-channel DDS).

But that depends on many things such as the relative timing of your 
clock and your logic.  You seem to be supposing that each calculation in 
your algorithm requires a register, a clock cycle and a pipeline stage. 
  The logic *can* be linear without registers.  It depends on the 
application.


> With regard to the equation, if you can't disentangle it, please start a
> new thread. It is an example describing an arbitrary chirp function, which
> is off-topic for this discussion, other than pointing out the line where to
> put your desired function into my matlab script.

I think I asked you to explain your script rather than my learning 
Matlab.  Any chance of using a more conventional notation?

-- 

Rick

Article: 157783
Subject: Re: Parametrized, synthesizable FFT engine
From: wzab01@gmail.com
Date: Tue, 24 Mar 2015 14:30:19 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

I have just updated my parametrized FFT engine published on OpenCores:
http://opencores.org/project,versatile_fft
I have added a new much faster implementation, which uses one butterfly block
in each stage of the radix-2 FFT.

With best regards,
Wojtek


Article: 157784
Subject: Intel in Talks to buy Altera
From: "" <1@FPGARelated>
Date: Fri, 27 Mar 2015 14:50:23 -0500
Links: << >>  << T >>  << A >>
http://www.wsj.com/articles/intel-in-talks-to-buy-altera-1427485172
---------------------------------------
Posted through http://www.FPGARelated.com

Article: 157785
Subject: Re: Intel in Talks to buy Altera
From: "" <1@FPGARelated>
Date: Fri, 27 Mar 2015 15:01:52 -0500
Links: << >>  << T >>  << A >>
>http://www.wsj.com/articles/intel-in-talks-to-buy-altera-1427485172
>---------------------------------------
>Posted through http://www.FPGARelated.com

Oups, here's another link about the same news that doesn't require to log
in:
http://www.cnbc.com/id/102508247
---------------------------------------
Posted through http://www.FPGARelated.com

Article: 157786
Subject: Re: Intel in Talks to buy Altera
From: Tim Wescott <seemywebsite@myfooter.really>
Date: Fri, 27 Mar 2015 16:28:14 -0500
Links: << >>  << T >>  << A >>
On Fri, 27 Mar 2015 14:50:23 -0500, "" wrote:

> http://www.wsj.com/articles/intel-in-talks-to-buy-altera-1427485172
> ---------------------------------------
> Posted through http://www.FPGARelated.com

Hmm.  While I have tons of respect for Intel as a company that makes stuff 
that people will buy, I'm old enough to have seen more than one generation 
of Intel embedded processors go by the wayside when the PC market picked 
up.

So I don't trust Intel's attention span vis-a-vis whatever they happen to 
think their core business is.  If they kept Altera as an easily-spun-off 
business unit, and kept it supported, then I could see them spinning it 
off again when the PC market did pick up, or by some miracle they managed 
to make cell phone processors that actually worked, or something.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Article: 157787
Subject: Interpret a VHDL statement within a serial to paralell port
From: nobody <cydrollinger@gmail.com>
Date: Fri, 27 Mar 2015 15:14:37 -0700 (PDT)
Links: << >>  << T >>  << A >>
First, thank you for taking the time to consider the questions I have not a=
nswered.=20
I am working on a 32 bit serial to 32 bit parallel port which reads from an=
 ADC. Currently looking to find a better solution, and I searched for prede=
fined vhdl module with little success. I stumbled upon Macros, SR16CE, whic=
h utilize primitives but they seem to be schematic oriented and not availab=
le inside the ISE 8.2i, windows xp os.=20

Question: Do common VHDL constructs exist in some library within the Xilinx=
 folder file structure?

Stumbling onto some help files within Xilinx website,http://www.csit-sun.pu=
b.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/do=
csan/xilinx4/data/docs/xst/hdlcode8.html, I found what I think I was lookin=
g for, however I need some help interpreting the VHDL statement that does e=
verything, [line 13]:

8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and Parallel=
 Out
Note For this example XST will infer SRL16.

1.library ieee;=20
2.use ieee.std_logic_1164.all;=20
=20
3.entity shift is =20
4. port(C, SI : in  std_logic;=20
5.        PO : out std_logic_vector(7 downto 0));=20
6.end shift;=20
7.architecture archi of shift is=20
8.  signal tmp: std_logic_vector(7 downto 0);=20
9.  begin=20
10.    process (C)=20
11.      begin =20
12.        if (C'event and C=3D'1') then =20
13.         tmp <=3D tmp(6 downto 0)& SI;=20
14.        end if;=20
15.    end process;=20
16.    PO <=3D tmp;=20
17.end archi;=20

Question:How does line 13 seem to do so much?


Article: 157788
Subject: Re: Interpret a VHDL statement within a serial to paralell port
From: darol.klawetter@gmail.com
Date: Fri, 27 Mar 2015 16:22:31 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Friday, March 27, 2015 at 5:14:44 PM UTC-5, nobody wrote:
> First, thank you for taking the time to consider the questions I have not=
 answered.=20
> I am working on a 32 bit serial to 32 bit parallel port which reads from =
an ADC. Currently looking to find a better solution, and I searched for pre=
defined vhdl module with little success. I stumbled upon Macros, SR16CE, wh=
ich utilize primitives but they seem to be schematic oriented and not avail=
able inside the ISE 8.2i, windows xp os.=20
>=20
> Question: Do common VHDL constructs exist in some library within the Xili=
nx folder file structure?
>=20
> Stumbling onto some help files within Xilinx website,http://www.csit-sun.=
pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/=
docsan/xilinx4/data/docs/xst/hdlcode8.html, I found what I think I was look=
ing for, however I need some help interpreting the VHDL statement that does=
 everything, [line 13]:
>=20
> 8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and Parall=
el Out
> Note For this example XST will infer SRL16.
>=20
> 1.library ieee;=20
> 2.use ieee.std_logic_1164.all;=20
> =20
> 3.entity shift is =20
> 4. port(C, SI : in  std_logic;=20
> 5.        PO : out std_logic_vector(7 downto 0));=20
> 6.end shift;=20
> 7.architecture archi of shift is=20
> 8.  signal tmp: std_logic_vector(7 downto 0);=20
> 9.  begin=20
> 10.    process (C)=20
> 11.      begin =20
> 12.        if (C'event and C=3D'1') then =20
> 13.         tmp <=3D tmp(6 downto 0)& SI;=20
> 14.        end if;=20
> 15.    end process;=20
> 16.    PO <=3D tmp;=20
> 17.end archi;=20
>=20
> Question:How does line 13 seem to do so much?

The "&" symbol in Line 13 is the concatenation operator. Line 13 performs t=
he shift by concatenating the lower 7 bits of the shift register with the s=
erial input, SI. This results in SI becoming bit 0 of tmp and bit 7 of tmp =
being discarded. Hope this helps.

Darol Klawetter

Article: 157789
Subject: Re: Interpret a VHDL statement within a serial to paralell port
From: rickman <gnuarm@gmail.com>
Date: Fri, 27 Mar 2015 22:23:51 -0400
Links: << >>  << T >>  << A >>
On 3/27/2015 7:22 PM, darol.klawetter@gmail.com wrote:
> On Friday, March 27, 2015 at 5:14:44 PM UTC-5, nobody wrote:
>> First, thank you for taking the time to consider the questions I have not answered.
>> I am working on a 32 bit serial to 32 bit parallel port which reads from an ADC. Currently looking to find a better solution, and I searched for predefined vhdl module with little success. I stumbled upon Macros, SR16CE, which utilize primitives but they seem to be schematic oriented and not available inside the ISE 8.2i, windows xp os.
>>
>> Question: Do common VHDL constructs exist in some library within the Xilinx folder file structure?
>>
>> Stumbling onto some help files within Xilinx website,http://www.csit-sun.pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode8.html, I found what I think I was looking for, however I need some help interpreting the VHDL statement that does everything, [line 13]:
>>
>> 8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and Parallel Out
>> Note For this example XST will infer SRL16.
>>
>> 1.library ieee;
>> 2.use ieee.std_logic_1164.all;
>>
>> 3.entity shift is
>> 4. port(C, SI : in  std_logic;
>> 5.        PO : out std_logic_vector(7 downto 0));
>> 6.end shift;
>> 7.architecture archi of shift is
>> 8.  signal tmp: std_logic_vector(7 downto 0);
>> 9.  begin
>> 10.    process (C)
>> 11.      begin
>> 12.        if (C'event and C='1') then
>> 13.         tmp <= tmp(6 downto 0)& SI;
>> 14.        end if;
>> 15.    end process;
>> 16.    PO <= tmp;
>> 17.end archi;
>>
>> Question:How does line 13 seem to do so much?
>
> The "&" symbol in Line 13 is the concatenation operator. Line 13 performs the shift by concatenating the lower 7 bits of the shift register with the serial input, SI. This results in SI becoming bit 0 of tmp and bit 7 of tmp being discarded. Hope this helps.

Yes, that is a fairly straightforward expression of the shift function. 
  The question is whether your tool will be able to infer the use of two 
SRL16s.  Actually, I don't think an SRL16 is at all appropriate for a 
serial to parallel converter since it doesn't have a parallel output. 
The SRL16 is serial buffer, 1 bit in and 1 bit out.

If you look at the various sections on this page they list examples some 
of which say they *will* infer SRL16s and some say they *will not* infer 
SRL16s.  I think they made a mistake and left out the *not* for the 
section showing this code.  This is *not* Xilinx vetted info.  It is a 
third party source with unknown credentials.  I believe any of the code 
shown involving parallel input or output will not be inferred using SRL16s.

Look at this app note and I think you will see the limitation of the 
SRL16s.

http://www.xilinx.com/support/documentation/application_notes/xapp465.pdf

So the above code will work just fine.  It just won't, and in fact, 
*can't* use an SRL16.

Someone please correct me if I am wrong.

-- 

Rick

Article: 157790
Subject: Re: Intel in Talks to buy Altera
From: Rob Doyle <radioengr@gmail.com>
Date: Fri, 27 Mar 2015 22:38:57 -0700
Links: << >>  << T >>  << A >>
On 3/27/2015 2:28 PM, Tim Wescott wrote:
> On Fri, 27 Mar 2015 14:50:23 -0500, "" wrote:
>
>> http://www.wsj.com/articles/intel-in-talks-to-buy-altera-1427485172
>> ---------------------------------------
>> Posted through http://www.FPGARelated.com
>
> Hmm.  While I have tons of respect for Intel as a company that makes stuff
> that people will buy, I'm old enough to have seen more than one generation
> of Intel embedded processors go by the wayside when the PC market picked
> up.
>
> So I don't trust Intel's attention span vis-a-vis whatever they happen to
> think their core business is.  If they kept Altera as an easily-spun-off
> business unit, and kept it supported, then I could see them spinning it
> off again when the PC market did pick up, or by some miracle they managed
> to make cell phone processors that actually worked, or something.
>

Not just embedded processors...

It wouldn't be the first time Intel was in the programmable logic business.

http://www.dataman.com/media/datasheet/Intel/5C090.pdf
http://www.dataman.com/media/datasheet/Intel/5C060.pdf
https://docs.google.com/file/d/0B9rh9tVI0J5mSzhDNUVpeVcyNDA/edit

Didn't Altera buy Intel's PLD business back in the '90s???

Sorry.   I don't see how this could be a good thing for Altera.

Rob.


Article: 157791
Subject: Re: Intel in Talks to buy Altera
From: rickman <gnuarm@gmail.com>
Date: Sat, 28 Mar 2015 03:54:07 -0400
Links: << >>  << T >>  << A >>
On 3/28/2015 1:38 AM, Rob Doyle wrote:
> On 3/27/2015 2:28 PM, Tim Wescott wrote:
>> On Fri, 27 Mar 2015 14:50:23 -0500, "" wrote:
>>
>>> http://www.wsj.com/articles/intel-in-talks-to-buy-altera-1427485172
>>> ---------------------------------------
>>> Posted through http://www.FPGARelated.com
>>
>> Hmm.  While I have tons of respect for Intel as a company that makes
>> stuff
>> that people will buy, I'm old enough to have seen more than one
>> generation
>> of Intel embedded processors go by the wayside when the PC market picked
>> up.
>>
>> So I don't trust Intel's attention span vis-a-vis whatever they happen to
>> think their core business is.  If they kept Altera as an easily-spun-off
>> business unit, and kept it supported, then I could see them spinning it
>> off again when the PC market did pick up, or by some miracle they managed
>> to make cell phone processors that actually worked, or something.
>>
>
> Not just embedded processors...
>
> It wouldn't be the first time Intel was in the programmable logic business.
>
> http://www.dataman.com/media/datasheet/Intel/5C090.pdf
> http://www.dataman.com/media/datasheet/Intel/5C060.pdf
> https://docs.google.com/file/d/0B9rh9tVI0J5mSzhDNUVpeVcyNDA/edit
>
> Didn't Altera buy Intel's PLD business back in the '90s???
>
> Sorry.   I don't see how this could be a good thing for Altera.

Yeah, I'm concerned too.  I'm hoping that Altera is big enough that 
Intel won't want to mess with them and destroy the company.

I think those data sheets are from the days when dinosaurs roamed the 
FPGA earth and was Intel's own attempt to enter the market.  I have no 
idea why they actually bailed.  I can only assume the competition was 
stiff then with a number of startups including Neocad providing the 
place and route software for a number of these companies.  Xilinx has 
said they spend more on software development than they do developing the 
hardware.  Several of these companies dropped their in house software 
development due to the huge cost.  Maybe Intel dropped the product line 
because of it.  But much more recently they were working with a company 
to produce some much more advanced product which I believe may still be 
operating using Intel's fab technology, or has it also gone belly up?  I 
don't recall the name.

Looks like Intel likes the Altera approach and want to keep it, literally.

-- 

Rick

Article: 157792
Subject: Re: Intel in Talks to buy Altera
From: Jan Coombs <Jan-54 <jenfhaomndgfwutc@murmic.plus.com>>
Date: Sat, 28 Mar 2015 08:45:59 +0000
Links: << >>  << T >>  << A >>
On Sat, 28 Mar 2015 03:54:07 -0400
rickman <gnuarm@gmail.com> wrote:

> I think those data sheets are from the days when dinosaurs roamed the 
> FPGA earth and was Intel's own attempt to enter the market.  I have no 
> idea why they actually bailed.  I can only assume the competition was 
> stiff then with a number of startups including Neocad providing the 
> place and route software for a number of these companies.  Xilinx has 
> said they spend more on software development than they do developing the 
> hardware.  Several of these companies dropped their in house software 
> development due to the huge cost.  Maybe Intel dropped the product line 
> because of it.  But much more recently they were working with a company 
> to produce some much more advanced product which I believe may still be 
> operating using Intel's fab technology, or has it also gone belly up?  I 
> don't recall the name.

Yes, more advanced - ten times faster and/or lower power.  Asynchronous, 
so no clock tree, but hard to get technical detail: 

http://www.achronix.com/   

Jan Coombs
-- 
email valid, else fix dots and hyphen
jan4clf2014@murrayhyphenmicroftdotcodotuk



Article: 157793
Subject: Re: Intel in Talks to buy Altera
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Sat, 28 Mar 2015 14:22:58 +0000 (UTC)
Links: << >>  << T >>  << A >>
On Fri, 27 Mar 2015 14:50:23 -0500, "" wrote:

> http://www.wsj.com/articles/intel-in-talks-to-buy-altera-1427485172
> ---------------------------------------
> Posted through http://www.FPGARelated.com

Well, Intel were Altera's 'second source' (back when that mattered) and 
(if I'm not mistaken) their original fab back in about 1983 - which is 
where the "Intel FPGAs" mentioned in another post came from. 

So there's quite a long association there.

-- Brian

Article: 157794
Subject: Re: processor core validation
From: "" <93490@FPGARelated>
Date: Sat, 28 Mar 2015 12:11:19 -0500
Links: << >>  << T >>  << A >>
>Hi everyone,
>
>I was wondering if anyone can point me to some formal method to validate 
>a soft processor core. 
>
>We have the source code (vhdl) and a simulation environment to load 
>programs and execute them, but I'm not sure in this case code coeverage 
>will be sufficient. What about cases like interrupt handling?
>
>I can run Dhrystone or CoreMark, but will it be sufficient?
>
>Any idea/pointer/comment is appreciated,
>
>Al
>
>-- 
>A: Because it messes up the order in which people normally read text.
>Q: Why is top-posting such a bad thing?
>A: Top-posting.
>Q: What is the most annoying thing on usenet and in e-mail?

------------------
You may find this page useful:
"In this document I show how to generate code for ARM processor and use it
in VHDL or VERILOG simulation.
The flow is from C code or assembly into VERILOG READMEMHEX format.
First you need to write a program in C or assembly. ..."
http://bknpk.ddns.net/my_web/AHB_MON/ARM_assembly/top.html

---------------------------------------
Posted through http://www.FPGARelated.com

Article: 157795
Subject: Re: Topics for Projects on FPGA+Computer Archtecture
From: "" <93490@FPGARelated>
Date: Sat, 28 Mar 2015 12:14:27 -0500
Links: << >>  << T >>  << A >>
>Hi,
>
> I have to work on a project related to FPGA (Altera DEI or Altera DEII)
and computer architecture. Can anyone suggest good topics that I can work
on individually (say for 3-4 months).
>Thank you in advance.

----------------------
Please take a look at:
"This project implements the lower layers of a standard TCP/IP stack based
on a free code from University of Queensland: IP stack
My first steps to understand the project, after reading the documents
are:..."
http://bknpk.ddns.net/my_web/IP_STACK/start_1.html

Another one may be:
" This project implements an IP TTL filter in hardware. If an IPV4 packet
is identified, the machine checks its TTL field. Based on previous values
of TTL data collected and analyzed from former packets, the machine decides
if the packet is spoofed or not...."
http://bknpk.ddns.net/my_web/SDIO/ip_ttl_filter_main.html

SD slave with Samsung flash (k9f1208) read burst
http://bknpk.ddns.net/my_web/SDIO/SD_flash_read_burst.html
---------------------------------------
Posted through http://www.FPGARelated.com

Article: 157796
Subject: Re: Parallel execution of Systemc code
From: "" <93490@FPGARelated>
Date: Sat, 28 Mar 2015 12:20:21 -0500
Links: << >>  << T >>  << A >>
>// Testbench
>rst=true; wait(10, SC_MS);
>rstúlse; in1=8; in2=2; in3=3; in4=6; sel=2;
>wait(50, SC_MS);
>cout << "selected data:" << out << " " << endl; rst=true; sel = 0;
>wait(50, SC_MS);
>cout << "selected data:" << out << " " << endl;
>
>
>I am used to VHDL which runs in parallel, but I finding it difficult to
understand/if Systemc code run in parallel like the example above.

---------------------
Can I suggest some simple examples of systemc:
My First systemC program
systemC debug with SC_TIME Tip
Simple multiplier and a test-bench in systemC
ETHERNET packet scv RANDOMIZATION in systemC
http://bknpk.ddns.net/my_web/MiscellaneousHW/MiscellaneousHW.html

---------------------------------------
Posted through http://www.FPGARelated.com

Article: 157797
Subject: Re: looking for systemC/TLM 2.0 courses
From: "" <93490@FPGARelated>
Date: Sat, 28 Mar 2015 12:23:22 -0500
Links: << >>  << T >>  << A >>
>Hi everyone,
>
>I apologize if this is maybe not the best audience for these kind of 
>enquiries but I'll try anyhow.
>
>I'm looking for a good SystemC/TLM 2.0 training course which is not too 
>basic and can give me a head start for a real life project.
>
>I'm not a black belt on C++ but I'm familiar with most of its concepts 
>on top of C (which I use quite often instead). Since we have a budget 
>for training in our company I'd like to make something useful out of it 
>and given the current issues we are facing in architecting systems of 
>increasingly complex features set, I believe that modeling would add 
>value to our products and avoid many issues due to a wrong architecture.
>
>Any ideas/suggestions?
>
>p.s.: I've no problems to start some reading/testing by myself in order 
>to fill the gap before attending the course.
>
>-- 
>A: Because it messes up the order in which people normally read text.
>Q: Why is top-posting such a bad thing?
>A: Top-posting.
>Q: What is the most annoying thing on usenet and in e-mail?

-------------------------------------------------
You may want to take a look on these simple systemc examples:
My First systemC program
systemC debug with SC_TIME Tip
Simple multiplier and a test-bench in systemC
ETHERNET packet scv RANDOMIZATION in systemC
http://bknpk.ddns.net/my_web/MiscellaneousHW/MiscellaneousHW.html


---------------------------------------
Posted through http://www.FPGARelated.com

Article: 157798
Subject: Re: Intel in Talks to buy Altera
From: Mike Butts <mbuttspdx@gmail.com>
Date: Sat, 28 Mar 2015 17:28:58 -0700 (PDT)
Links: << >>  << T >>  << A >>
FCCM predicted this in 2011...
http://fccm.org/2015/previous.html#past

  --Mike

Article: 157799
Subject: Re: Lattice MachXO3L - new "F"sub-subfamily...
From: Tim <tim@bugblat.invalid>
Date: Sun, 29 Mar 2015 21:12:16 +0100
Links: << >>  << T >>  << A >>
On 11/03/2015 01:27, Brane2 wrote:
> Lattice has shipped new version of their Diamond tool v 3.4.1. for FPGA design.
>
> Changelog lists support for new MachXO3LF devices, which I can't find anywhere,.
>

The XO3 Programming Guide says:
The MachXO3™ is an SRAM-based Programmable Logic Device that includes an 
internal Non-Volatile Configuration Memory (NVCM) in the MachXO3L 
version and On-Chip Flash in the MachXO3LF version.




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