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Xilinx OrCAD base development system (APR version 3.30-EL) for sale,
including original disks, manuals, download cable, demo board and dongle. I
payed $1000 for this new in '94, but you can make real money with this
system even today, so make an offer.
- Development system for Xilinx EPLD and FPGA devices up to XC3142A
- Works with OrCAD SDT IV and SDT 386+ (not included- I'm also selling OrCAD
SDT IV (see post in sci.electronics.cad), which I bought for $500, so
you can make an offer on that as well if you want).
- Dongle has problems with fast parallel ports on fast machines (needs an
ISA bus parallel port and definitely not a Pentium PRO- I've been using it
on a 486 DX4/100 with no problems).
- Maybe a cheap way for you to get valuable experience with Xilinx FPGAs
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 7401
> int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
> +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
> ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
C'mon, Joe. What the hell does this mean? I hate to take it public, but
you post it over and over. Is it funny, or somehow worth trying to
interpret? or is it just cute? is there a contest that the first person
to figure it out will win? Or are you just trying to drive all of us who
know C CRAZY? ARGHHHHHHHHHHHHHHHHHHHH!!!!!!!!!!!
Article: 7402
Joseph H Allen wrote:
> - Development system for Xilinx EPLD and FPGA devices up to XC3142A
> /* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
> int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
> +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
> ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
ARGHHHHHHHHHHHHHHHHHHHHHHHHHHH!!!!!!!!!!!!!!!!!!
Article: 7403Hi all, I know this groups is pretty much devoted to digital IC stuff, but it was the closest I could find to analog IC... I'm looking for ideas for a "nifty little" *analog* IC project. Part of one of my fourth year EE electives involves designing and fabricating a semi-custom (bipolar) analog IC. The only requirements for the project are that it be simple and "demoable" (i.e., can be used with external components to do something interesting such as produce sound or light in response to some input). Re-inventing the wheel is ok because the idea is more to be exposed to the chip design process than it is to design a charge pump PLL or RF headend. Any ideas would be appreciated. Please respond by email... Thanks, Chris Samwald 5th Year EE at Simon Fraser University (P.S., Assuming I get the project to work properly, I can send the person whose idea I use a sample of the chip... If that would be desired, that is.)Article: 7404
In article <34122EB3.1159@imxtech.com>, Bill Ewing <bewing@imxtech.com> wrote:
>>int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
>>+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
>>]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
> C'mon, Joe. What the hell does this mean? I hate to take it public,
>but you post it over and over. Is it funny, or somehow worth trying to
>interpret? or is it just cute? is there a contest that the first person to
>figure it out will win? Or are you just trying to drive all of us who know
>C CRAZY? ARGHHHHHHHHHHHHHHHHHHHH!!!!!!!!!!!
So are you saying I need to change my signature or that I'm USENET addict?
Sheesh, all you have to do is compile and run it to find out what it does.
You claim to know C, but if you _really_ knew C, you'd be able to figure it
out at a mere glance.
Joe's .sig challenge: my .sig can be made even smaller. I don't do this
because I like that it exactly fills three lines. Can you make it smaller
with no loss in functionality?
Joe's second challenge: write a three line (or less) decompression program
including data in C, so that when run, you get an expanded signature which
is at least three lines full of english text, but preferably really long and
annoying, maybe with an ASCII art sword or starship enterprise or something.
So you don't know C and you don't have a C compiler? Press space:
It prints a randomly generated maze (maze routing get it?, very appropriate
for an FPGA newsgroup don't you think?):
###############################################################################
# # # # ### # # # # # # # # # # # # # #
# # # # ##### ### # ##### ### ##### ### ##### # # # ### # ##### # # # # # # # #
# # # # # # # # # # # # # # # # # #
####### ### ### # ### ##### # ### # # ### ##### ####### # ########### # # ### #
# # # # # # # # # # # # # # # # # # # #
# ### # ### # ### ### ####### ### # # # # ### # ### ##### # ### ##### # # # # #
# # # # # # # # # # # # # # # # # # # # # #
# ####### ####### # # ### # ### ##### ##### ### ######### # ##### ##### ##### #
# # # # # # # # # # # # # # # # #
# ####### # # # ### # ####### ### # # # # ####### # # # ### ##### ####### #####
# # # # # # # # # # # # # # # # # # # # #
##### # ############# # ####### ### ####### ### ####### ### # ### # ##### ### #
# # # # # # # # # ### # # # # # # # # # #
# ### ### # ### ### ##### ### ### ####### # ### ### ##### # ### # ### ####### #
# # # # # # # # # # # # # # # # # # # # #
# ### # # # ##### ### ### # ### # # # # ######### # ####### ### ##### ####### #
# # # # # # # # # # # # # # # # #
# ### ########### # ### # ##### ### ### ### ##### ##### ########### # ### # # #
# # # # # # # # # # # # # # # # #
# # # ##### ### ### ### ### ### # ### ### # # # ##### ##### ######### # ### ###
# # # ### # # # # # # # # ##### #
###############################################################################
You would be amazed at how many people ask me where the entrance and exit
are. It's a surprisingly high number really. Well there aren't any, and
there is no stated goal for getting out of or going through the maze.
However, you _are_ stuck in the maze, somewhere, and there _is_ a
restroom... somewhere. But don't worry, you have lots of time.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 7405- Expect a smoother experience if you start from a synthesizable design. - Conversion of an FPGA netlist to a standard-cell netlist is painful and non efficient. > Did the expected cost savings materialize Cost savings on what? BDipert wrote in article <19970905173101.NAA06995@ladder01.news.aol.com>... >I'm interested in hearing from any of you who have considered or even >'taken the plunge' and completed a FPGA-to-ASIC design conversion. Did it >go as you expected it would, was it easier or more difficult? What company >or companies did you work with? Did the expected cost savings materialize, >and if not, why not? Thanks in advance for sharing your experiencesArticle: 7406
The Xilinx XC3030A comes in 44- and 68-"pin" PLCC packages and in 64-oin VQFP ( and many others ). It has plenty of flip-flops ( over 200 !) Look it up at www.xilinx.com Peter Alfke, Xilinx ApplicationsArticle: 7407
Go to: www.xilinx.com and browse and download the information you are after, data book, app note etc. Peter Alfke, XilinxArticle: 7408
The past year has seen a dramatic reduction in the cost of term life insurance from many quality companies. The San Fransisco Chronicle reported, "Price War Creates Consumer Bargains in Term Life Insurance," and the New York Times, "Premiums have fallen to record lows." You may not be aware that your life insurance company could now be charging new policyholders less than you are now paying for the same coverage. Your traditional life insurance agent has access to a small number of life insurance companies. Through the internet, you can compare rates to every other policy available. Our free price comparison service gives you access to over 550 term policies from over 175 life insurance companies. For a free comparison please go to: http://www.2plan.com/quote.htmArticle: 7409
Austin Franklin wrote in article <01bcb7a4$227517f0$35a8b8cd@drt1>... ><snip> >Intel (who was a major player in the creation of the PCI spec) violates the >spec. all the time. Yes. As a matter of fact, Intel has just licensed a PCI core from Virtual Chips - Phoenix Technologies. >Many PCI cards on the market violate the spec, yet they still 'appear' to >work. Working is not a very good test of PCI compliance. Yes again. Therefore, beware of cheap and freely downloadable PCI code from FPGA vendors. It will 'work' but every Nth card sold will be owned by an unhappy customer. > >Austin Franklin >darkroom@ix.netcom.com >Article: 7410
Hi, my names Phillip and I'm going to be starting a final year university project involving the Xilinx FPGA within the next few months. I don't have much knowledge of FPGA's at the moment, would someone take the time to either copy some information to this newgroup, or point me to a site on the web please? Thanks in advance, Phil RenfieldArticle: 7411
i have a report on reconfigurable logic could you send me any reference, site , paper, to help me in this work Thanks a lotArticle: 7412
Hi, there Why don't you try Lattice's ispLSI1024 which has 144 Registers(including 48 IO register) and 48 I/O. Or ispLSI1032 which has 192 register and 64 I/O. You may find more info about Lattice deivice from http://www.latticesemi.com . Bulent UNALMIS <unalmis@club-internet.fr> wrote in article <3410DCB4.4E6C@club-internet.fr>... > Hello, > I am looking 48 or 64 pin FPGA, but this fpga must be have MINUMUM 96 > register. > > For example : Lattice ispLSI2096 has 96 Flipflop, but has 128 pin. !!! > > > Best Reagrds. >Article: 7413
Keil has freeware intel hex converters. Check http://www.keil.com oder maybe better ftp://ftp.keil.com Mat In article <3410AEC0.35DB@eng.efi.com>, gbaron@eng.efi.com says... > >Hi guys and gals. > >Sorry It's been along time since I accessed newsgroups but I've moved. >Not just around the corner but to a new country. The US of A! > >Anyway I was wondering if any of you kind people might help. > >I'm after a file converter or source which will convert a raw binary >file into Intel Hex format. I have a IHEX deconstructor but not a >constructor. > >Please Email me with any info. or source code. > >Many thanks. > >Gareth Baron. >Direct Tel: 415 286 7943 > >Electronics For Imaging. 2855 Campus Drive, San Mateo, CA 94403 >Tel: 415 286 8600 Fax: 415286 8545Article: 7414
BDipert wrote: > > I'm interested in hearing from any of you who have considered or even > 'taken the plunge' and completed a FPGA-to-ASIC design conversion. Did it > go as you expected it would, was it easier or more difficult? What company > or companies did you work with? Did the expected cost savings materialize, > and if not, why not? Thanks in advance for sharing your experiences If you use a Hardware Description Language such as VHDL and good design principles then the migration should be straight forward. If you want the edge on performance though, you may have to tweek some bits manually in the FPGA implementation. IakovosArticle: 7415
If the following sounds like advertising,that is not intentional. What you call a synchronous FIFO, is really the epitomy of an asynchronous FIFO: Read and write clock are totally independent and asynchronous. A high-performance version of such a design requires a dual-port RAM, and you can read a detailed description in the Xilinx ( I don't work for Altera ) web site ( www.xilinx.com ), click on the applications book and look for XAPP051. If both clock rates are slow, there is a way to control a single-port RAM, but it may get pretty hairy. It depends on the required access time, and whether you can tolerate a BUSY, or whether you prefer a staging register, or even two. I prefer a dual-port RAM. Not surprisingly, Xilinx offers that feature in XC4000E and XC4000XL. Peter Alfke, Xilinx ApplicationsArticle: 7416
> In article <3410DCB4.4E6C@club-internet.fr>, > Bulent UNALMIS <unalmis@club-internet.fr> wrote: <snip> > >I am looking 48 or 64 pin FPGA, but this fpga must be have MINUMUM 96 > >register. > > <snip> you can use the actel a1020b in either 44 or 68 pin. 2,000 gate fpga, 547 modules ( 2 mods per edge trigerred f-f, 1 mod per latch). the a1010b has 147 max f-f's which will work if you don't have much other stuff in there. at&t data book shows att3030 in either 44 or 68 pin and 3,000 gates and 100 clb's. each clb has two f-f's according to the picture and f-f's in the i/o blocks also which are real handy either directly or by unused pins. i'm sure if i get this wrong we'll hear from our good friend across the pond! the quicklogic ql12x16 is in 68 pin package. data book says 2,000 gates, 192 f-f's. that's all i got handy, hope it helps, rk (vendors arranged in alphabetical order from lower to higher - next one will be reverse order :-)Article: 7417
What are the list prices for FPGA tools (say, Verilog sim & synthesis for Xilinx chips)? The requirements: Windows NT (or Linux) on x86, and can work on more than just Xilinx chips (please list the cost for other chips). (I was disappointed that www.optimagic.com didn't list prices....) Danny Kumamoto mailto:dnk@pobox.com http://www.pobox.com/~dnk/ TEL: +1 512-918-3640 Postal: 13492 Research Blvd., Suite 120-295, Austin, TX 78750-2254, U.S.A.Article: 7418
Bulent, QuickLogic makes a couple of parts that fit your description. One is the QL8x12B in a 68 PLCC or 44 PLCC package. (96 flip flops) The other is the QL12x16B in the 68 pin PLCC package. (192 flip-flops) Contact the QuickLogic Web Site (www.quicklogic.com) and click on 'Sales' to find a local Sales representative. - Brian Small QuickLogic Customer Engineering Bulent UNALMIS wrote in article <3410DCB4.4E6C@club-internet.fr>... >Hello, > >Help please for choising FPGA. > >I am new for fpga, I am using (know) only lattice isplsi 2032. This IC >has has 44 pin and 32 registers. > >I used three 2032 at my project but i want to use only one fpga. (96 >register) >[Becouse I want simplified printed circuit board.] > > >I am looking 48 or 64 pin FPGA, but this fpga must be have MINUMUM 96 >register. > >For example : Lattice ispLSI2096 has 96 Flipflop, but has 128 pin. !!! > >Therfore, I dont like from this IC. > >Do you know any FPGA for this purpose ? (From any company) > >Best Reagrds.Article: 7419
I'm trying to implement a synchronous FIFO on an Altera FLEX10K device that uses independent read and write clocks. All the information I have seen shows the simple "cycle-shared" example, where a single clock is used for reading and writing. Since I am using the FIFO as a staging area between what goes on inside the FPGA and a local external bus, the internal write clock must be independent of the exteral read clock. This is the implementation most COTS FIFO chips implement. I want to avoid using an external FIFO chip, so I'm looking for a design that describes the control logic for generating empty, full, and inhibit logic for both the read and write sides. If anybody has information about where I might find a good description of the internal workings of FIFO control logic, such as books or a web site, I'd appreciate it. Actually, a schematic would be nice, but I'm not going to hold my breath for that one. Thanks in advance. -- Bryn Wolfe - Robotics Engineer Metrica TRAC LabsArticle: 7420
Bryn Wolfe wrote: > > I'm trying to implement a synchronous FIFO on an Altera FLEX10K device > that uses independent read and write clocks. All the information I have > seen shows the simple "cycle-shared" example, where a single clock is > used for reading and writing. Since I am using the FIFO as a staging > area between what goes on inside the FPGA and a local external bus, the > internal write clock must be independent of the exteral read clock. The lack of a dual port RAM makes your task harder. If you were using, say a Xilinx 4KE series part, you can set the CLBs up as a dual port ram with the read and write clocks independent. In that case, the only challenging part of the design is dealing with the full and empty flag generation (this logic needs to work across the clock domains). In the case of the Altera 10K, the internal RAM is not a dual ported device. This means the read and write clocks need to have a known relationship to make it work. To do what you are describing, the write data (or the read data) has to be translated to (from) the clock domain of the RAM using register(s) and some form of semaphores. The easiest way I know of doing this is to run the RAM clock domain at a frequency several times higher than the unmatched clock domain, and in the case of the write being the unmatched one, set a flag each time the write clock fills the input register. A state machine senses the flag set and transfers the value from the write register to the RAM using the RAM's clock. The interface between the clock domains is thereby reduced to the flag logic. I normally do that part by toggling a flop on each write. The toggle output is input to a 4 state grey encoded state machine to generate the write pulse. (only one flop affected at any one time by the write toggle). Hope that helps you come up with a way to proceed. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka @ ids.net http://users.ids.net/~randrakaArticle: 7421
Bulent UNALMIS <unalmis@club-internet.fr> wrote in article <3410DCB4.4E6C@club-internet.fr>... > I am looking 48 or 64 pin FPGA, but this fpga must be have MINUMUM 96 > register. > > For example : Lattice ispLSI2096 has 96 Flipflop, but has 128 pin. !!! You can try Lattice ispLSI1024 which has 96 FFs (+ 48 I/O FFs = 144 FFs) and it is available in 68-pin PLCC package. Regards, Mankit WongArticle: 7422
Maybe standard terminology is lacking, but I would be interested how a "non-clocked FIFO" could possibly work. Something has to tell the device to accept data, and something else has to tell it to spit out the next word. I call those signals clocks. You can call them "handshake". Just semantics. Peter Alfke, XilinxArticle: 7423
Actually, the last part of you message is approaching a commercial, but I don't mind. As far as asynchronous and synchronous FIFOs, I was distinguishing between the two by their need for a clock or not. An asynchronous FIFO does not require a clock, whereas a synchronous one does, irrespective of whether the clocks are shared or not. The industry's language is obviously not clear on this point. At any rate, I saw the XAPP051 shortly after I posted my request, and it is fairly thorough about how to do this... on a Xilinx device with dual port RAM. The Altera device has dual port data (separate in and out) but the addressing is a single port. Kinda wierd. With respect to access times and tolerance of BUSY, I can tolerate a BUSY on the write side because it is a slower, steady process compared to the bursty requests from the reader. I agree with the staging register idea, as suggested by Ray Andraka's reply (see other thread to original posting). I just need to figure out the logic to latch the write request, process the message, and then negate the write request until the next one comes through. Hmmm... -- Bryn Wolfe - Robotics Engineer Metrica TRAC LabsArticle: 7424
-- When I served a booth at EuroDac '96, across from us there was a small European FPGA company that was touting a 20x30mm FPGA die. I would like a contact if anyone knows who I am talking about. Anyone knowing of an alternative largish source would be greatly appreciated as well. Many thanks. Mike --- Michael Seningen EVSX, Inc. 5725 HWY 290 West Suite 200 Austin, Texas 78735 512/436-2802 Fax:512/436-2843 ---
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z