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On Sep 21, 11:39=A0am, Andy <jonesa...@comcast.net> wrote: > Back when we used PALs with only 4 or 8 registers (16R4 & 16R8 PALs), > separately synchronizing an input to a state machine was not always an > option from a resource point of view. > > As has been said above, there are methods* of making a state machine > tolerant of asynchronous inputs. But these methods are exceedingly > difficult to verify and/or review, especially when compared to the use > of an explicit synchronizer. Furthermore, these methods are often > thwarted by optimizations that are commonplace in FPGA synthesis > tools. Finally, given the abundance of registers in FPGAs, there is > very rarely an acceptable excuse to not use an explicit synchronizer. > > * the rules for these methods are: > > 1. All transitions of the state machine in response to an asyncrhonous > reset, including any registered outputs, must result in the > possibility of only one bit changing. > > 1A. A state may have conditional destinations of itself and an > adjacent (on a K-map) state > > 1B. A state may have two separate destination states that are adjacent > to each other, but then staying in the current state is not allowed. > > 1C. A state may change a single-bit registered output based on the > async input, but it cannot also transition out of that state at the > same time. An old trick to effectively "re-use" a synchronizing > register was to set a flag while in the state based on the async > input, then transition out of the state based on the flag a clock > later. The same flag could be used in multiple states, for multiple > different async inputs. > > The hoops we jumped through to get things done in 8 flops or less... > > Andy Ah the good old PAL days, where you could use PALASM and get exactly what you coded - no need to check the "technology schematic". Most of my state machine code in those days was carefully coded so that the state variables WERE the desired outputs of the machine, with possibly one or two "nodes" when the outputs were not sufficient to define all of the required states. Every signal was visible on an oscilloscope / logic analyzer - no buried state. Even back then I ran into cases of state logic failure from asynchronous inputs and usually managed to solve it by making sure only one macrocell used the async input directly. In FPGA's where flip-flops are virtually free, it's a no-brainer to just add one more to synchronize your inputs unless you are very highly concerned about latency. On the topic of metastability, you don't necessarily need to use two flip-flops to reduce the metastability failure rate to near zero. Generally the tools allow you to define a slack requirement for the path from the output of the synchronizing flop to any flops further down the pipe. If you can meet the slack requirement without adding a pipeline stage, you save one flop and one cycle of latency. Regards, GaborArticle: 149026
Very good point, metastability on outputs driving non-causal inputs can easily be handled with a little extra settling time (a couple of extra ns can buy centuries of MTBF in many FPGAs). Only if the output is driving a causal input (e.g. clock or async reset input) do you need the second flop (what we call a metastable rejecter flop). AndyArticle: 149027
On 09/21/2010 10:16 AM, Darol Klawetter wrote: > Concise summary of this thread: > > While it's possible to build a state machine that safely handles > asynchronous inputs, there's seldom any justification for it. Failure > to synchronize inputs invites trouble and violates decades of solid > design practice. > And, the best answer to this is to see if a different architecture that makes the state machine immune to these asynch inputs fixes your problem. JonArticle: 149028
Hi again, Tha problem was the .mss file. There was there something mixed between the two MicroBlazes. I modified the .mss file and the Xilkernel is compiling correctly on both processors, but when I try to change some settings in "Software Platform Settings" and press OK, the SDK suddenly stops with Eclipse message : "JVM terminated. Exit code=1". This problem does not appear when I use the same design but without FSL connection. I can't manage to find if is it a bug or a problem in my design. Can someone give me an ideea ? Many thanks, Iulian --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149029
On Sep 21, 3:48=A0pm, Jon Elson <jmel...@wustl.edu> wrote: > On 09/21/2010 10:16 AM, Darol Klawetter wrote: > > > Concise summary of this thread: > > > While it's possible to build a state machine that safely handles > > asynchronous inputs, there's seldom any justification for it. Failure > > to synchronize inputs invites trouble and violates decades of solid > > design practice. > > And, the best answer to this is to see if a different architecture that > makes the state machine immune to these asynch inputs fixes your problem. > > Jon Actually, you can build an asynchronous state machine that will respond to each input as it changes rather than wait for a clock. But that would likely require synchronization on the outputs of the state machine and may not meet all the requirements of the design if other elements linked to it are synchronous. RickArticle: 149030
http://www.xilinx.com/support/documentation/customer_notices/xcn10028.pdfArticle: 149031
On Sep 22, 2:03=A0pm, Dave <dhsch...@gmail.com> wrote: > http://www.xilinx.com/support/documentation/customer_notices/xcn10028... Wow..that sucks!Article: 149032
On 21 Sep., 18:19, d_s_klein <d_s_kl...@yahoo.com> wrote: > If, and only if your gray code is implemented with a gray counter. Wrong. > Otherwise, it's just another state coding, and the idea that only one > bit changes at a time is false. Why do you insist on this? There definitely are state machines that are more complex than a counter but where there are no transitions that change more than one bit. This is what the other posters are talking about. Signal skew is not an issue in these desings. To go to the extreme: There are complete microprocessors on the market that work without a clock signal. Asynchronous design has a couple of advantages, especially with regard to power consumption. It therefore has been thoroughly explored by academia and some companies for decades now. However, there are a lot of pitfals, so the general conclusion seems to be that the biggest problem in IC design is correctness and designer productivity and both clearly are better for synchronous designs. KoljaArticle: 149033
>"Dave Pollum" <vze24h5m@verizon.net> wrote in message >news:0119143e-38d6-433e-bd74-14def9f70d4e@a19g2000vbi.googlegroups.com... >On Sep 22, 2:03 pm, Dave <dhsch...@gmail.com> wrote: >> http://www.xilinx.com/support/documentation/customer_notices/xcn10028... > >Wow..that sucks! I agree, ISIM is OKish but no comparison to Modelsim which is light-years ahead IMHO. This announcement doesn't come as a surprise, the rumours have been circulating for months...... http://www.sigasi.com/forum/xilinx-slowly-dumping-modelsim Lets hope Mentor comes up with a good deal to upgrade to PE or better DE! Hans www.ht-lab.comArticle: 149034
During my last consulting project I had to implement quite a few Microblaze PLB peripherals, each with lots of software-accessible registers (up to 60). I found the process of implementing those registers quite tedious and also error-prone because information is duplicated in different files (e.g. register addresses in the VHDL module and in the C driver). That's why I decided to automate the whole thing by creating a (free) tool called IPICRegs. The idea is that you describe the software-accessible registers corresponding to your peripheral in a XML-file, and the tool generates a VHDL registers module for you containing all the register read/write logic. You just need to instantiate the generated module into your user-logic, and the bitfields of all the registers become available through ports of that module. And while I was at it, I thought I could as well generate a few other goodies from the same XML input file: - an instantiation template for the generated VHDL module - a VHDL testbench, which checks that every single register field can be accessed - a VHDL package, containing the register address offsets as well as a bitmask for every bitfield - ISim simulation scripts - a C header containing all the register address offsets, bitmasks and read/write functions - C self-test which checks that every single bitfield is accessible from the processor - an HTML documentation containing all the information about the registers and bitfields IPICRegs has saved me and my client a lot of time. I hope you'll find it useful too. You can download the current (beta) version from: http://www.ingenieurbuero-eschemann.de/ipicregs.html I'm also very open to suggestions for improving the tool. Feel free to contact me if you experience any issues. Cheers, -- Guy Eschemann Ingenieurb=FCro ESCHEMANN Gartenstr. 30-32 76133 Karlsruhe, Germany Guy.Eschemann@gmail.com http://www.ingenieurbuero-eschemann.de http://www.fpga-news.deArticle: 149035
On Sep 23, 2:50=A0am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > On 21 Sep., 18:19, d_s_klein <d_s_kl...@yahoo.com> wrote: > > > If, and only if your gray code is implemented with a gray counter. > > Wrong. > > > Otherwise, it's just another state coding, and the idea that only one > > bit changes at a time is false. > > Why do you insist on this? > There definitely are state machines that are more complex than a > counter but where > there are no transitions that change more than one bit. This is what > the other posters are talking about. > Signal skew is not an issue in these desings. > > To go to the extreme: There are complete microprocessors on the market > that > work without a clock signal. > > Asynchronous design has a couple of advantages, especially with regard > to power consumption. > It therefore has been thoroughly explored by academia and some > companies for decades now. > However, there are a lot of pitfals, so the general conclusion seems > to be that the biggest problem > in IC design is correctness and designer productivity and both clearly > are better for synchronous designs. > > Kolja Well, another point in this thread is that for FPGA design tools, a synchronous design is presumed by the tools and therefore all the necessary robustness required to check asynchronous state changes must be done by hand or via some very expensive third-party tools. It's not even clear that asynchronous design has a big power advantage in an FPGA due to the structure of the fabric. Global clock routing has been optimized and takes much less power per load than general routing, for example.Article: 149036
On Sep 23, 3:55=A0am, "HT-Lab" <han...@ht-lab.com> wrote: > >"Dave Pollum" <vze24...@verizon.net> wrote in message > >news:0119143e-38d6-433e-bd74-14def9f70d4e@a19g2000vbi.googlegroups.com..= . > >On Sep 22, 2:03 pm, Dave <dhsch...@gmail.com> wrote: > >>http://www.xilinx.com/support/documentation/customer_notices/xcn10028..= . > > >Wow..that sucks! > > I agree, ISIM is OKish but no comparison to Modelsim which is light-years= ahead > IMHO. > > This announcement doesn't come as a surprise, the rumours have been circu= lating > for months...... > > http://www.sigasi.com/forum/xilinx-slowly-dumping-modelsim > > Lets hope Mentor comes up with a good deal to upgrade to PE or better DE! > > Hanswww.ht-lab.com It is my understanding that Xilinx is planning some major improvements to ISIM. I hope that they continue to support ModelSim as an integrated piece of the environment even if you need to purchase it separately. It would be a mess if you needed to compile the libraries without script support, for example. -- GaborArticle: 149037
Hi, I'm considering buying Virtex5 FXT70 minimodule board which has many I/Os. But I' confused whether MGT signals (JXx_MGTRXx_P and JXx_MGTRXx_N) on EXP connector can be configured as 2.5V standard LVDS signals? If yes please explain me how to do that. Link to boards documentation: http://www.em.avnet.com/evk/home/0,1707,RID%253D0%2526CID%253D55729%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526PRT%253D0%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html Regards, BartekArticle: 149038
On Sep 23, 6:20=A0am, Gabor <ga...@alacron.com> wrote: > On Sep 23, 3:55=A0am, "HT-Lab" <han...@ht-lab.com> wrote: > > > > > >"Dave Pollum" <vze24...@verizon.net> wrote in message > > >news:0119143e-38d6-433e-bd74-14def9f70d4e@a19g2000vbi.googlegroups.com= ... > > >On Sep 22, 2:03 pm, Dave <dhsch...@gmail.com> wrote: > > >>http://www.xilinx.com/support/documentation/customer_notices/xcn10028= ... > > > >Wow..that sucks! > > > I agree, ISIM is OKish but no comparison to Modelsim which is light-yea= rs ahead > > IMHO. > > > This announcement doesn't come as a surprise, the rumours have been cir= culating > > for months...... > > >http://www.sigasi.com/forum/xilinx-slowly-dumping-modelsim > > > Lets hope Mentor comes up with a good deal to upgrade to PE or better D= E! > > > Hanswww.ht-lab.com > > It is my understanding that Xilinx is planning some major improvements > to ISIM. =A0I > hope that they continue to support ModelSim as an integrated piece of > the > environment even if you need to purchase it separately. =A0It would be a > mess > if you needed to compile the libraries without script support, for > example. > > -- Gabor I've been using Veritak to do my (Verilog) FPGA sims for quite a while now.I'm quite happy with it and the developer is quite responsive to bug reports & suggestions. The price is extremely reasonable. John ProvidenzaArticle: 149039
On Sep 23, 6:47=A0am, Bartek <misi...@onet.eu> wrote: > Hi, > > I'm considering buying Virtex5 FXT70 minimodule board which has many I/Os= . > But I' confused whether MGT signals (JXx_MGTRXx_P and JXx_MGTRXx_N) on > EXP connector can be configured =A0as 2.5V standard LVDS signals? > > If yes please explain me how to do that. > > Link to boards documentation:http://www.em.avnet.com/evk/home/0,1707,RID%= 253D0%2526CID%253D55729%2... > > Regards, > Bartek No you cannot do this. The MGT IO pins are dedicated resources. Ed McGettigan -- Xilinx Inc.Article: 149040
Hi, i received a quote for a Virtex6 XC6VLX75T of 200USD for unit: is it possible or is it an error? ThanksArticle: 149041
fasf <silusilusilu@gmail.com> wrote: > Hi, > i received a quote for a Virtex6 XC6VLX75T of 200USD for unit: is it > possible or is it an error? > Thanks findchips.com let one assume it's an error or fake... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 149042
On Sep 23, 9:12=A0am, fasf <silusilus...@gmail.com> wrote: > Hi, > i received a quote for a Virtex6 XC6VLX75T of 200USD for unit: is it > possible or is it an error? > Thanks Did you get the quote from an authorized distributor?Article: 149043
On 23 Set, 18:19, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > fasf <silusilus...@gmail.com> wrote: > > Hi, > > i received a quote for a Virtex6 XC6VLX75T of 200USD for unit: is it > > possible or is it an error? > > Thanks > > findchips.com let one assume it's an error or fake... I dind't know that site: but seems it not work very well....for example, if i find XC6VLX75T, from digikey i have no results....Article: 149044
Andy Peters <google@latke.net> wrote: > On Sep 23, 9:12 am, fasf <silusilus...@gmail.com> wrote: > > Hi, > > i received a quote for a Virtex6 XC6VLX75T of 200USD for unit: is it > > possible or is it an error? > > Thanks > Did you get the quote from an authorized distributor? Xilinix is still in the roll-out phase of Virtex6 and Spartan 6. Only few parts are available by simple ordering them at a catalogue distributor. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 149045
On Sep 22, 8:03=A0pm, Dave <dhsch...@gmail.com> wrote: > http://www.xilinx.com/support/documentation/customer_notices/xcn10028... Xilinx drops Modelsim XE and at about the same time Altera drops Quartus ISIM leaving Modelsim AE as the only supported optin for low- cost simulation. WOW! X&A twins don't follow steps of each other. Doesn't happen very often.Article: 149046
On Thu, 23 Sep 2010 12:32:22 -0700 (PDT), fasf <silusilusilu@gmail.com> wrote: >On 23 Set, 18:19, Uwe Bonnes <b...@elektron.ikp.physik.tu- >darmstadt.de> wrote: >> fasf <silusilus...@gmail.com> wrote: >> > Hi, >> > i received a quote for a Virtex6 XC6VLX75T of 200USD for unit: is it >> > possible or is it an error? >> > Thanks >> >> findchips.com let one assume it's an error or fake... > >I dind't know that site: but seems it not work very well....for >example, if i find XC6VLX75T, from digikey i have no results.... At digikey the least expensive (not in stock) xc6vlx75 is $764 for one unit. Avnet has very small numbers of these chips and the price seems to be around $600 for one unit. The price you're given is not a reasonable number. Obviously it's not from Avnet which is the only authorized distributor for Xilinx at this point. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 149047
Hi, I'm looking for a Virtex5 XC5VLX50T-1FFG1136C devboard with small dimension, low cost and these features 1. LVDS output (15channels) 2. Ethernet port 3. USB port or 2USB ports....any help?Article: 149048
I'm not sure you will find anything like this as a standard item but we could offer it as a custom. John Adair Enterpoint Ltd. On 24 Sep, 12:26, eryer <idkfaidkfaid...@gmail.com> wrote: > Hi, > I'm looking for a Virtex5 XC5VLX50T-1FFG1136C devboard with small > dimension, low cost and these features > 1. LVDS output (15channels) > 2. Ethernet port > 3. USB port > or 2USB ports....any help?Article: 149049
>On Sep 19, 8:58=A0pm, "jt_eaton" ><z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: >> Is it my imagination of did all the spam on this newsgroup suddenly >> disappear? >> I checked google groups and the last piece I saw was dated 10 Aug. I was >> sure that there were some more recent stuff. >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >I think that there are a number of people using Google Groups that are >now reporting posts as SPAM. In another thread someone has posted >that it takes about 40 total abuse reports from at least two different >IP addresses for the Google routines to punt a post. > >So if everyone does a little community service and clicks the "Report >spam" link 5-10 times each time these show up they will disappear >quickly. Sometimes I only get 2 or 3 clicks and the post is gone so I >know there are others out there doing the same. > >Ed McGettigan >-- >Xilinx Inc. > That could work if we had enough users to make it happen. What I've seen today is spam shows up and I click 10 or more times and maybe a few hours later it will disappear. I am not going to sit here like a trained monkey clicking away on spam because google refuses to address the problem. They know dammed well that this crap is spam and they still dump it on us. I'm sad because I really like it when some newbie asks a question that I can help them with but I have had it with google groups. They really are evil. I am out of here. Usenet. You are dead to me. Goodbye John Eaton --------------------------------------- Posted through http://www.FPGARelated.com
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