Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Nov 25, 3:22=A0pm, whygee <y...@yg.yg> wrote: > hello, > > I woud like to design a 32,768 Hz stable input for > calibrated real-time operation of a FPGA-centric system, > as power-of-two frequencies make digital computations > very easy, using shifts instead of divides for motion equations. > > =A0 * I "could" use a multiple of this frequency as my > main clock but I find no suitable canned oscillator > (a 3.3V 5x7mm one is preferred, cheaper is better) > > examples : > =A0 - 18.423MHz / 32768 =3D 562.5 =3D> almost there... > =A0 so I would have to divide it by 5*5*5*3*3 > =A0 =A0to get a power-of-two frequency, but only 16KHz. > =A0 - 24.576MHz (close to my target 25MHz) =3D 2*3*5*5*5 * 32768 > =A0 =A0so I get a nice 65536Hz after 4 small prescalers > =A0 =A0but my other 25MHz circuits won't be happy by 1.7%. > And I have already bought the 25MHz oscillators :-/ > > =A0 * I "could" make a custom oscillator with a cheap&tiny "wristwatch" > cristal but the power consumption, stability and acuracy > would not be optimised. > > =A0 * My target is the Actel A3P250 in TQFP100 package. > I "could" use his Fusion sibling (that has an integrated > and separately powered RTC oscillator) but the price > difference is ... not enchanting. And the package is different. > And I have the A3P250 already :-/ > > =A0 * I "could" use a common external I2C clock/calendar > but i'd prefer SPI and the cheap chips don't (rarely ?) provide > the 32KHz output (that I reuse to sequence stuff). > > So... what's left ? > > yg > --http://ygdes.com/http://yasep.org I think you've covered all the bases given your apparently conflicting requirements. Often engineering is a matter of determining an optimal combination of all requirements, but sometimes it is a matter of trading off one against the other so that neither is optimal, but both are adequate. So if you *must* use 25 MHz, then you need a 25 MHz oscillator, not 24.576. That means you have to provide another clock. If using a 32.576 kHz oscillator is too power consuming, how do you expect to get this second clock? I don't see how a clock chip would be any better than a 32.576 kHz oscillator. The clock chip still uses a crystal. RickArticle: 144301
On Nov 26, 9:22=A0am, whygee <y...@yg.yg> wrote: > hello, > > I would like to design a 32,768 Hz stable input <snip> > And I have already bought the 25MHz oscillators :-/ > > So... what's left ? A different approach... How stable ? - If you have 25Mhz Osc, then divide by 762/763 in a ratio basis, gets you to within 5.2ppm of 32.768 on average, and gives just 40ns of period jitter. Tolerable? 1-((2*(762/25e6)+29*(763/25e6))/31)*32768 ans =3D 5.20258064516129032e-6 Is your 25MHz better than 5ppm ;) -jgArticle: 144302
-jg wrote: > On Nov 26, 9:22 am, whygee <y...@yg.yg> wrote: >> So... what's left ? > It's not clear exactly what you are asking ? I'm asking for more ideas or methods :-) > Epson, EM Microelectronic et al, have 32Khz osc > modules, that include the crystal. all I have seen up to now at my usual sources is the small crystals. Maybe I should dig more. However, I'm looking at cheap lots of 50pc from second hand/refurbishers etc. > Maxim have one that is TCXO as well, and > if precision matters, then you will need txco. The precision that I need is crystal-like, but I fear that if I do my own circuit, I can't tune it to reach it. Compensation capacitors, track parasites etc. can spoil the circuit unnecessarily. So a canned osc sounds best. > NXP PCF2129 is another candidate, but less stocked. Never heard about this part... I'll have to google it :-/ > MicroCrystal.com also have a range. hmmm yet another new name for me :-) <click> wow, it looks expensive :-) > Some tcxo's are fixes in time, not frequency, so > watch the details ;) I'll watch them but what do you mean exactly ? thanks, > -jg yg -- http://ygdes.com / http://yasep.orgArticle: 144303
webpack crashed whilst synthesising my design. This is the first time that I have had this. I have managed to get the design to synthesise properly and do a p&r netlist. I didn't change the design. The things that are missing are mainly cosmetic but I would like to reinstate them. The snapshot list is blank. I can see a snapshot directory and there are files inside it. How do I get webpack to re-create the snapshot area? When I do a synthesis run I don't get an errors/warnings report. Yes I can look at the synthesis log. It would be good to get the list of errors and warnings on the design summary page. Any ideas/pointers. Thanks in advance AndyArticle: 144304
On Nov 26, 9:22=A0am, whygee <y...@yg.yg> wrote: > hello, > > I woud like to design a 32,768 Hz stable input for > calibrated real-time operation of a FPGA-centric system, > as power-of-two frequencies make digital computations > very easy, using shifts instead of divides for motion equations. If this is for motion control, it's likely the 40ns jitter and 5ppm of my earlier example is fine... .. but in case it is not, if you are going to x4 the 25MHz anyway in a PLL, then this can apply : 1-((1*(3051/100e6)+3*(3052/100e6))/4)*32768 ans =3D 2.56e-6 ie from 100MHz, you get 2.56ppm, and 10ns jitter, and any binary time under 32768/4, has no jitter at all. -jgArticle: 144305
malcolm wrote:
> If this is for motion control,
> it's likely the 40ns jitter and 5ppm of
> my earlier example is fine...
By "motion control" I mean something similar to
Microchip's AN964 : "Software PID Control of an Inverted Pendulum Using the PIC16F684 "
http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1824&appnote=en021807
So I think the jitter is not critical, but overall stability is desirable.
Commercial temperature range is OK.
But a cheap, long-term stable, pre-tuned oscillator for clocks/calendars
would have been good : it could keep track of time/date AND provide real-time signals :-)
> .. but in case it is not, if you are going to x4 the 25MHz anyway in a
> PLL, then this can apply :
I've thought about this, since I target operation 100MHz in the digital domain.
> 1-((1*(3051/100e6)+3*(3052/100e6))/4)*32768
> ans = 2.56e-6
That's a complex computation, the PLL's dividers
are too small for division by 3051...
> ie from 100MHz, you get 2.56ppm, and 10ns jitter,
> and any binary time under 32768/4, has no jitter
> at all.
My last thought is that the 25MHz is not so critical.
I have other frequency requirements so other frequencies
are needed anyway. Power being proportional to frequency,
and serial communications (UART/RS232) are potential too,
I found that a 12.288MHz canned osc is a good compromise :
- 2x less toggles on the pins compared to 25MHz so (locally) lower draw
- I get 98.308MHz in the digital domain after 8x in the PLL
(it could even be dynamically changed from the PLL configuration register),
which is only 2% below the target (not a real loss).
- I get a stable 48KHz time base for sound (x256 for delta/sigma chips)
- and a good 32.768KHz base after division by 3*5*5*5.
- RS232 @ 38400 bps is OK, faster if some %err is possible
(a x3 in the PLL gets me to 230400bps)
- Some displays require 24.5454 in NTSC mode,
which is very close to 12.288*2=24.576MHz
For the 25MHz, I'll try to hook a pin of a nearby ENC28J60 module.
However it is risky (it will disturb the oscillator's stability
if i connect a wire to the crystal) and since I'm missing my digital
frequency target by only 2%, it's not a big issue.
Now, I'll have to find cheap lots of >50pc 5x7 oscillators from my usual
brokers. Too bad I have already found the 25MHz ones :-/
Yes, I try to cut costs in any reasonable way ;-)
regards,
> -jg
jg != malcolm ?
yg
--
http://ygdes.com / http://yasep.org
Article: 144306On Nov 26, 11:27=A0am, whygee <y...@yg.yg> wrote: > -jg wrote: > The precision that I need is crystal-like, > but I fear that if I do my own circuit, > I can't tune it to reach it. > Compensation capacitors, track parasites etc. > can spoil the circuit unnecessarily. > So a canned osc sounds best. Digikey shows 69 items for Oscillator[32.768Khz] and 41 for stocked. > > Some tcxo's are fixes in time, not frequency, so > > watch the details ;) > > I'll watch them but what do you mean exactly ? The DS32Khz TCXO, is probably your best choice, if you don't want to use the 25Mhz (or need more precision). (or the NXP ones, have more modern Vcc ranges, but not as easy to get..) These trim via a Cap on the Crystal, so the fix is in the frequency domain. Some RTCs that trim, somewhat 'cheat' and vary the dividers, so that the average time-of-day is corrected, but NOT the 32Khz frequency. For their intended use that's fine.. but probably not for using alongside a FPGA. -jgArticle: 144307
Hi Rick ! rickman wrote: > I think you've covered all the bases given your apparently conflicting > requirements. Often engineering is a matter of determining an optimal > combination of all requirements, but sometimes it is a matter of > trading off one against the other so that neither is optimal, but both > are adequate. Yeah, I remember reading a Usenet poster's signature along these lines on comp.arch or something like that :-) > So if you *must* use 25 MHz, then you need a 25 MHz > oscillator, not 24.576. right. I realised that the "stable" 25MHz is required by the 10BaseT interface, which already has its own crystal. For the rest, as written in my last post, the -%2 compromise on digital speed is compensated by a better match in most other interfaces so I won't complain. Well, except about availability at very low prices ;-) > That means you have to provide another > clock. If using a 32.576 kHz oscillator is too power consuming, at least if I do it myself, because I'm not sure to do it right. I have no atomic clock at home to help calibrate the capacitors :-) > how do you expect to get this second clock? I don't see how a clock chip > would be any better than a 32.576 kHz oscillator. The clock chip > still uses a crystal. I first thought about using an integrated external clock/calendar but I don't know one that outputs its internal Xtal's output :-/ Using a 12.288MHz as a main and single clock looks like the best idea yet but availability is an issue. I mean : outside of the "usual suspects"'s distribution prices. I'll have to go harrass the brokers again :-D _o/ > Rick yg -- http://ygdes.com / http://yasep.orgArticle: 144308
On Nov 26, 12:17=A0pm, whygee <y...@yg.yg> wrote: > malcolm wrote: > > If this is for motion control, > > it's likely the 40ns jitter and 5ppm of > > my earlier example is fine... > > By "motion control" I mean something similar to > Microchip's AN964 : "Software PID Control of an Inverted Pendulum Using t= he PIC16F684 "http://www.microchip.com/stellent/idcplg?IdcService=3DSS_GET_= PAGE&nodeI... > > So I think the jitter is not critical, but overall stability is desirable= . > Commercial temperature range is OK. > But a cheap, long-term stable, pre-tuned oscillator for clocks/calendars > would have been good : it could keep track of time/date AND provide real-= time signals :-) If those last few ppm matter, you will pay for them... > > 1-((1*(3051/100e6)+3*(3052/100e6))/4)*32768 > > ans =3D 2.56e-6 > > That's a complex computation, the PLL's dividers > are too small for division by 3051... Not complex : You divide 100MHz by 3051 one out of 4 times, and 3 out of 4 times, you divide by 3052. So that's just 12FF for the 3051/3052 counter, and 2FF for the 'which of 4? counter' > -jg > > jg !=3D malcolm ? ;) My son grabs his gmail, and I don't always notice.... -jgArticle: 144309
On Nov 25, 5:33=A0pm, Andy Botterill <a...@plymouth2.demon.co.uk> wrote: > webpack crashed whilst synthesising my design. This is the first time > that I have had this. I have managed to get the design to synthesise > properly and do a p&r netlist. I didn't change the design. > > The things that are missing are mainly cosmetic but I would like to > reinstate them. The snapshot list is blank. I can see a snapshot > directory and there are files inside it. How do I get webpack to > re-create the snapshot area? When I do a synthesis run I don't get an > errors/warnings report. Yes I can look at the synthesis log. It would be > good to get the list of errors and warnings on the design summary page. > > Any ideas/pointers. Thanks in advance Andy Whenever ISE/Webpack does something strange, clicking on the Project Tab, and then Cleanup Project Files often helps. I don't know if this will solve your problem or not. HTH -Dave PollumArticle: 144310
-jg wrote: > On Nov 26, 12:17 pm, whygee <y...@yg.yg> wrote: >> So I think the jitter is not critical, but overall stability is desirable. >> Commercial temperature range is OK. >> But a cheap, long-term stable, pre-tuned oscillator for clocks/calendars >> would have been good : it could keep track of time/date AND provide real-time signals :-) > If those last few ppm matter, you will pay for them... sure... i'll go for the price first ;-) I have searched a couple of well known stores and the best (and cheapest) I could find is 3x5 at about $2/pc. If I want 50pc, my "pocket money" won't be enough :-) >>> 1-((1*(3051/100e6)+3*(3052/100e6))/4)*32768 >>> ans = 2.56e-6 >> That's a complex computation, the PLL's dividers >> are too small for division by 3051... > Not complex : You divide 100MHz by 3051 one out of 4 times, and 3 out > of 4 times, you divide by 3052. So that's just 12FF for the 3051/3052 > counter, and 2FF for the 'which of 4? counter' It seems that it's too demanding, the FF are not the whole story. At 100MHz, I can only count on a depth of 5 or 6 gates with 3-inputs (the target is A3P250), I would have liked a predivider at least... A 12.288MHz main clock seems much easier, though software delays will be impacted by the 1.7% decrease... What other trouble could occur when the clock is slowed down a bit ? For the slow & precise measurements, I am fine with the internal power-of-two timer, but what fast operations could go wrong or simply be affected or impacted ? I/O timings are mostly specified with a "minimum delay" so non-polled peripherals should be fine, communication protocols are handshaked... No, I don't see what impact a reduction from 100MHz to 98MHz could have on good software. Particularly if it is meant for a CPU that could have an adjustable main clock. The only effect is on ego (or marketing) because 100MHz is a "sweet spot" and 98 looks more like a miss, even though static timing analysis reports better than that. But who said that marketing was compatible with engineering ? >>> -jg >> jg != malcolm ? > ;) My son grabs his gmail, and I don't always notice.... erf :-) > -jg yg -- http://ygdes.com / http://yasep.orgArticle: 144311
On Nov 25, 4:24=A0pm, Philip Pemberton <usene...@philpem.me.uk> wrote: > Sorted it... > > So I started looking for gated clocks in the separator -- turns out the > Data Window flip-flop is wired to toggle (i.e. divide its clock by two; > not-Q wired to D), and is clocked from the most significant bit of the > DPLL shift register... > You're going about this all wrong, internal generated clocks do not (repeat that 50 times) in FPGA designs. There is an inherent clock skew that you can not control and will eventually doom your design. This skew is not unique to FPGAs, it happens if you design it with discrete parts, the difference is that inside the FPGA there is nothing you can do to compensate for it. Ias Nial suggested, the way to do this is to use one (count them...one) clock and generate clock enable signals. In your case, take the 40 MHz into a PLL to generate 80 MHz. The entire design runs off of the 80 MHz. One set of things that will run off of the 80 MHz will be a set of clock enable generators: - Count 0 to 4 to generate 16 MHz clock enable - Count 0 to 9 to generate 8 MHz clock enable - Count 0 to 19 to generate 4 MHz clock enable (Bonus points for noticing that a single counter from 0 to 19 can be used to generate all three clock enables) Your stated requirement of "..a 50% duty cycle (for a data separator/ slicer)." seem suspicious. All these timing errors that Quartus is (validly) complaining about are for internal signals. Internal to the device there will not be a requirement for any particular duty cycle. If you data separator/slicer does have such a requirement, then it needs to be redesigned to work in an FPGA environment. > > So now the output is clocked from the master clock, thus making most of > the data separator synchronous (the only exception I can see is the first > input synchronisation FF, U2A), and eliminating the timing issue. > See? Not that hard. > But now I'm wondering if there's a better way to do this... I've got a > design for a state machine based data separator from a Western Digital > application note[1], but it suffers from a similar issue -- a DQ f/f > wired to toggle, clocked from the MSB output of the state machine PROM. > There are all sorts of ASIC design technique that are not usable in FPGAs. They are different environments with different design constraints. Kevin JenningsArticle: 144312
On Nov 26, 2:25=A0pm, whygee <y...@yg.yg> wrote: > It seems that it's too demanding, the FF are not the whole story. > At 100MHz, I can only count on a depth of 5 or 6 gates with 3-inputs > (the target is A3P250), I would have liked a predivider at least... > There are other solutions: My original one, from 25Mhz, has a 31 modulo swallow : with /762 /763 counter 1-((2*(762/25e6)+29*(763/25e6))/31)*32768 ans =3D 5.20258064516129032e-6 and there is a solution at 50MHz 1-((1*(1525/50e6)+7*(1526/50e6))/8)*32768 ans =3D 2.56e-6 - interesting this is also 2.56ppm, but with a modulo 8 swallow. Can you get a 11 bit preloadable counter, at 50Mhz ? Or, this can be done as fixed /25; /61, and a single width CE pulse, to swallow one clock, to get /1526 > The only effect is on ego (or marketing) because 100MHz is a "sweet spot" > and 98 looks more like a miss, even though static timing analysis > reports better than that. But who said that marketing was compatible > with engineering ? Marketing would call a 98Mhz point a "100Mhz system" anyway ;) -jgArticle: 144313
On Nov 26, 5:11=A0pm, -jg <jim.granvi...@gmail.com> wrote: > > and there is a solution at 50MHz > > 1-((1*(1525/50e6)+7*(1526/50e6))/8)*32768 > ans =3D 2.56e-6 and 100Mhz/3 is better than I expected, A 10 bit + modulo-4 swallow fits here 1-((3*(1017/(100e6/3))+1*(1018/(100e6/3)))/4)*32768 ans =3D 2.56ppm (1017 =3D 9*113) and at 100Mhz/6, 9 bit + modulo-8 1-((3*(508/(100e6/6))+5*(509/(100e6/6)))/8)*32768 ans =3D 2.56ppm A 9 bit, 16Mhz counter should be viable ? -jgArticle: 144314
-jg wrote: > There are other solutions: > > My original one, from 25Mhz, has a 31 modulo > swallow : with /762 /763 counter > 1-((2*(762/25e6)+29*(763/25e6))/31)*32768 > ans = 5.20258064516129032e-6 > > and there is a solution at 50MHz > 1-((1*(1525/50e6)+7*(1526/50e6))/8)*32768 > ans = 2.56e-6 is the barrell of aspirine also provided ? :-) > - interesting this is also 2.56ppm, but with > a modulo 8 swallow. > Can you get a 11 bit preloadable counter, at 50Mhz ? it should do, but that's looking overengineered :-/ > Or, this can be done as fixed /25; /61, and a single width CE pulse, > to swallow one clock, to get /1526 a proper crystal frequency sounds better :-/ >> The only effect is on ego (or marketing) because 100MHz is a "sweet spot" >> and 98 looks more like a miss, even though static timing analysis >> reports better than that. But who said that marketing was compatible >> with engineering ? > Marketing would call a 98Mhz point a "100Mhz system" anyway ;) My CPU is memory-synchronous so it is limited by the external asynch SRAM's speed anyway... The fastest ones I could find are 8ns so I'm not sure that a 10ns cycle is realistic. I have synchronous RAMs that are faster but they introduce delays... ... I just looked at the datasheets and the ENC28J60 provides a "clock out" that is configured as 25/4=6.25MHz after power-on reset. This pin is also available on the module's output \o/ I looked further and Microchip was careful : the oscillator is not disabled when the chip sleeps, only when the clock control register is set so. So no dirty business with getting around stupid system interlocks during sleep :-) I could switch the integrated CPU clock source to the 25MHz when booted. However, the 10BasetT module is optional, and I have only one PLL so frequency multiplication is possible on only one main clock... The question of price is very important : I could get a bunch of suitable crystals for a good price, but canned oscillators are not as available, and not for the desired frequency. So I'm looking at how I can safely drive the crystal without adding too many analog parts. In fact, a cheap PIC12F could do the trick and the remaining pins could replace the voltage supervisors. The space eaten by the HC49S can is compensated by some removed SOT23s ... The price of the crystal + cheap PIC is lower than a smaller oscillator :-/ > -jg yg -- http://ygdes.com / http://yasep.orgArticle: 144315
-jg wrote: > A 9 bit, 16Mhz counter should be viable ? did anyone tell you that you're obsessed ? :-D > -jg yg -- http://ygdes.com / http://yasep.orgArticle: 144316
-jg wrote: > I thought 'standard values' and price were important? I go for 12.288MHz as main clock, I can divide easily by simple integers to get RS232, 32.768KHz and some audio frequencies. I can also PLL up to 98MHz wich is close enough to 100MHz. I can reuse the 25MHz oscillators later. I'm now looking around for better deals than the usual/mainstream distributors. I have found crystals but driving them properly opens a new can of worms... like price, surface, complexity, calibration... > -jg yg -- http://ygdes.com / http://yasep.orgArticle: 144317
On Nov 26, 6:25=A0pm, whygee <y...@yg.yg> wrote: > > Can you get a 11 bit preloadable counter, at 50Mhz ? > > it should do, but that's looking overengineered :-/ > > > Or, this can be done as fixed /25; /61, and a single width CE pulse, > > to swallow one clock, to get /1526 > > a proper crystal frequency sounds better :-/ ? but a lot more expensive, than < 20FF in a FPGA. I thought 'standard values' and price were important? -jgArticle: 144318
Dave Pollum wrote: > On Nov 25, 5:33 pm, Andy Botterill <a...@plymouth2.demon.co.uk> wrote: >> webpack crashed whilst synthesising my design. This is the first time >> that I have had this. I have managed to get the design to synthesise >> properly and do a p&r netlist. I didn't change the design. >> >> The things that are missing are mainly cosmetic but I would like to >> reinstate them. The snapshot list is blank. I can see a snapshot >> directory and there are files inside it. How do I get webpack to >> re-create the snapshot area? When I do a synthesis run I don't get an >> errors/warnings report. Yes I can look at the synthesis log. It would be >> good to get the list of errors and warnings on the design summary page. >> >> Any ideas/pointers. Thanks in advance Andy > > Whenever ISE/Webpack does something strange, clicking on the Project > Tab, and then Cleanup Project Files often helps. I don't know if this > will solve your problem or not. I tried that first thing. It didn't report any files to tidy up. I've set the correct fpga family, added the root module and updated a few of the synthesis settings. If I do a project clean up will I lose these changes? Andy > HTH > -Dave PollumArticle: 144319
Is not there anyone defending the Spartan6 PCIe endpoint? I would really like to use it as it means removing an extra component from the BOM. This design is supposed to be supported for many years to come, and relying on the long term GN4124 availability may not be such a good bet. Any advice is more than welcome! pablo On Nov 23, 11:58=A0am, palvarez <pabloalvarezsanc...@gmail.com> wrote: > Hi! > > I am designing a system that needs PCIe and multiboot operation. I > would like to be able to reprogram the application FPGA =A0at any > moment. The safest option would be using a GN4124 and any FPGA. That > would be clean and simple. But if you think of PCIe and multiboot then > using a single Spartan6 comes out as the cheap and flexible option. I > still have some doubts... > > What is the behaviour of the Spartan6 PCIe endpoint during a > multiboot? > Is it possible to use partial reconfiguration in such a way that the > PCIe bus does not notice that the FPGA has been reprogrammed? > > Ok, let us assume that the PCIe end point is reset after an FPGA > reconfiguration. Will the PCIe bus manager be able to handle it? > > Best Regards > > PabloArticle: 144320
On Wed, 25 Nov 2009 19:19:45 -0800, KJ wrote:
> Your stated requirement of "..a 50% duty cycle (for a data separator/
> slicer)." seem suspicious. All these timing errors that Quartus is
> (validly) complaining about are for internal signals. Internal to the
> device there will not be a requirement for any particular duty cycle. If
> you data separator/slicer does have such a requirement, then it needs to
> be redesigned to work in an FPGA environment.
OK, I think I need to do a bit more of an explanation, but you're going
to need the circuit diagram for the original version of the circuit for
it to make much sense. This is on http://www.analog-innovations.com/SED/
FloppyDataExtractor.pdf.
What the circuit does is take an MFM encoded stream from a floppy disc,
then produce a Data Window signal from that. If a READ_DATA pulse is
detected within the data window, a '1' is clocked into a 16-bit shift
register elsewhere in the circuit. If no transition is detected, then a
'0' is clocked in.
The goal is to have a signal that looks like this when a data pulse
occurs:
----+ +-----
DWIN |______|
-------++-------
DATA ||
The three flip-flops on the left synchronise the read-data signal against
the master clock and shape it -- SHAPED_DATA is READ_DATA, but processed
so that it's low for exactly two MASTER_CLK cycles.
Now back to the data separator. This consists of an 8-bit shift register
which is wired to count up and down in a sequence of n=16 (that is, 16
possible states) -- I can't remember the exact sequence off hand, but
running the SR+inverter for about 16 clock cycles with CLEAR wired
inactive should be sufficient to list them.
The sequence is basically a triangle-wave -- the SR outputs count up from
00 to FF, then down to 00 again. The Q7 (MSB) output from the SR is used
to clock a DQ flip-flop (which is wired to toggle) and change the state
of DWIN.
When a RD_DATA pulse is detected, the shift register is cleared back to
0. Depending on where the pulse occurs, the DWIN edge is advanced or
delayed by the value of the counter. This has the effect of compensating
for any shift in the input (RD_DATA) signal that is caused by the speed
of the disc drive motor varying over time.
I doubt the DWIN flip-flop won't be affected if it's wired "as
presented" (CLK=shiftreg[7], CLKE=1), but with the alterations
(CLKE=shiftreg[7], CLK=MASTERCLK) I'm not so sure...
Thanks,
--
Phil.
usenet09@philpem.me.uk
http://www.philpem.me.uk/
Article: 144321On Nov 26, 8:51=A0am, whygee <y...@yg.yg> wrote: > -jg wrote: > > I thought 'standard values' and price were important? > > I go for 12.288MHz as main clock, > I can divide easily by simple integers to get RS232, 32.768KHz > and some audio frequencies. I can also PLL up to 98MHz wich > is close enough to 100MHz. I can reuse the 25MHz oscillators later. > > I'm now looking around for better deals > than the usual/mainstream distributors. > I have found crystals but driving them > properly opens a new can of worms... > like price, surface, complexity, calibration... > > > -jg > > yg > > --http://ygdes.com/http://yasep.org you cant get it all. getting GOOD smd oscillators at 0.50$ at low qty in A3P250 you do have the PLL for free but it has its lower frequency so if you use 32khz you cant use the PLL and can not have any frequency highere then 32KHz at all, unless you run own ring- oscillator with dynamic calibration AnttiArticle: 144322
> OK, I think I need to do a bit more of an explanation, but you're going > to need the circuit diagram for the original version of the circuit for > it to make much sense. This is on http://www.analog-innovations.com/SED/ > FloppyDataExtractor.pdf. Phil, You need to forget the original circuit apart from working out what it does. Then go and read up on synchronous FPGA design. YOU DO NOT WANT TO GENERATE AND USE RIPPLE CLOCKS IN AN FPGA. The tools aren't designed to handle/analyse them. Nial.Article: 144323
Try to build a new project and copy - ONLY - your source files. ( ISE have some "artificial intelligence" issues ;) ) By experience; do your self your personal backups/snapshots using a script or copy your working folders to a backup location. If you use Windows, a WinZIP command line batch file is a good and simple option, you have options on Linux also. Walter. Andy Botterill escribió: > Dave Pollum wrote: >> On Nov 25, 5:33 pm, Andy Botterill <a...@plymouth2.demon.co.uk> wrote: >>> webpack crashed whilst synthesising my design. This is the first time >>> that I have had this. I have managed to get the design to synthesise >>> properly and do a p&r netlist. I didn't change the design. >>> >>> The things that are missing are mainly cosmetic but I would like to >>> reinstate them. The snapshot list is blank. I can see a snapshot >>> directory and there are files inside it. How do I get webpack to >>> re-create the snapshot area? When I do a synthesis run I don't get an >>> errors/warnings report. Yes I can look at the synthesis log. It would be >>> good to get the list of errors and warnings on the design summary page. >>> >>> Any ideas/pointers. Thanks in advance Andy >> >> Whenever ISE/Webpack does something strange, clicking on the Project >> Tab, and then Cleanup Project Files often helps. I don't know if this >> will solve your problem or not. > > I tried that first thing. It didn't report any files to tidy up. > > I've set the correct fpga family, added the root module and updated a > few of the synthesis settings. > > If I do a project clean up will I lose these changes? Andy >> HTH >> -Dave PollumArticle: 144324
Hi Antti ! I can't reach you by email :-( Antti wrote: > you cant get it all. > getting GOOD smd oscillators at 0.50$ at low qty I believe you but I don't know where/how. > in A3P250 you do have the PLL for free but it has its lower frequency the PLL input is minimum 1.5MHz. > so if you use 32khz you cant use the PLL and can not have any > frequency highere then 32KHz at all, unless you run own ring- > oscillator with dynamic calibration I don't understand. What kind of trick do you want to use ? > Antti yg -- http://ygdes.com / http://yasep.org
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z