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Messages from 131775

Article: 131775
Subject: Re: Old FPGA question
From: Duane Clark <user@domaininvalid.com>
Date: Thu, 01 May 2008 15:25:03 -0700
Links: << >>  << T >>  << A >>
whygee wrote:
> Thanks for the encouraging and very fast answers !
> 
> Duane Clark wrote:
>>> And today, in my favorite broker's "trash bin", i find
>>> a pair of unused Xilinx parts that may also serve me,
>>> but past experiences with unmounted FPGA chips make me cautious :
>>> I have already found XC3000 parts, some in PGA packages...
>>> Even an IKOS emulator http://ygdes.com/ikos/ with hundreds
>>> of FPGAs, but that are not supported anymore :-(
>>
>> By the way, Xilinx is pretty good about making available old versions 
>> of their software to use on older parts. And while some of the older 
>> software is not available in Linux versions, most of it ran quite well 
>> under Wine.
> 
> Let's see in my oldienosaur collection :
> 4x Xilinx XC4010-5  PG191C (191-pin ceramic PGA)
> 2x XC3195A-4 PP175C (175-pin plastic grid array)
> A year ago, i was not able to find any support for them :-/

It would be here:
http://www.xilinx.com/ise/logic_design_prod/classics.htm
However, I would not bother spending time on either of those parts ;)

> 
> The Xilinx parts in the IKOS Pegasus emulator are all BGA,
> and they are ok as they are soldered, but i have no idea
> of the PCB interconnexion .... so despite finding some basic
> documentation about them, they are desperately useless too :-(
> (see http://ygdes.com/ikos/boards.jpg )
> In fact the only way to use it would be to find
> all the SW and schematics of the original manufacturer,
> which AFAIK has been bought (swallowed, assimilated and crushed)
> a loooong time ago by Mentor... what should I do ?
> (I have no use for the 1000A 3,3V power supply as is)

Yea, I took a look at those pictures. Interesting, but probably more 
trouble than it is worth to do anything with it.

> 
> Just for the information : one of my applications for FPGA
> is to implement http://yasep.org/,
> and I also want to develop some crude digital camera processing
> similar to the CMUcam.
> So unlike with F-CPU, I don't need extreme speed and densities,
> just something that works and can interface with 5V or 3,3V parts
> borrowed from other electronic stuffs (SRAM, SDRAM, microcontrollers,
> ISA buses, ...)

The XCV (Virtex) parts should be just fine for those kinds of purposes.

Article: 131776
Subject: Re: FLASH vs SRAM (was Re: Old FPGA question)
From: Duane Clark <user@domaininvalid.com>
Date: Thu, 01 May 2008 15:29:06 -0700
Links: << >>  << T >>  << A >>
whygee wrote:
> well, a long time ago, I had a lot of fun with ... antifuse parts :-)
> there were Actel A1020 dev tools at my engineers' school and I was fond
> of this architecture, not to mention the Mentor Graphics GUI !
> (on oooooold HP Apollo workstations, oh God..... now, THAT was slow
> even by that day's standards.)

Hey, at the time, I thought those HP workstations were pretty good. I 
after getting used to it, I thought the Mentor Graphics mouse "strokes" 
were kind of handy. And I definitely liked the plain text project 
mapping files (I forget what they were called), something I wish all 
engineering tools had.

Article: 131777
Subject: Re: sobel in vhdl
From: Jim Lewis <jim@synthworks.com>
Date: Thu, 01 May 2008 15:59:08 -0700
Links: << >>  << T >>  << A >>
Rossalbi
Check out Peter Ashenden's new book on Digital Design.

Jim

>>
>> Hi people...
>>
>> I am trying to find a vhdl code for 3x3 sobel algorithm to implement
>> on a Spartan 3, FPGA.
>>
>> I have found many papers on the subject but they are all from a high
>> level of abstraction and none include any actual code.
>>
>> Any help would be greatly appreciated.
>>
>> Ross Albi
> The greatest challenge probably isn't the Sobel computer itself but the 
> memory management.  If the image/video frame is too large to fit in the 
> FPGA, you'll have to have an external memory controller and line 
> buffers, etc.  -Kevin

Article: 131778
Subject: Re: FLASH vs SRAM (was Re: Old FPGA question)
From: whygee <whygee@yg.yg>
Date: Fri, 02 May 2008 01:55:49 +0200
Links: << >>  << T >>  << A >>
Sorry in advance if this discussion is not interesting for this group :-)

Duane Clark wrote:
> whygee wrote:
>> well, a long time ago, I had a lot of fun with ... antifuse parts :-)
>> there were Actel A1020 dev tools at my engineers' school and I was fond
>> of this architecture, not to mention the Mentor Graphics GUI !
>> (on oooooold HP Apollo workstations, oh God..... now, THAT was slow
>> even by that day's standards.)
> 
> Hey, at the time, I thought those HP workstations were pretty good.

It was in 1996-1997, at
http://www.iut-cachan.u-psud.fr/fr/iut_cachan/departements/departement_geii2.html
The workstations were obviously "end of life" but needed by the SW for the course.
In the administration, when it works, it's not changed :-)
The teacher was very passionated (he's now retired), and I loved to spend
time in the CAD room with the huge CRTs... It was definitely more exciting
than the math courses of the rest of the day ! But when the poor HP workstations
started to swap (there was no local disk), things got ugly...
particularly because of the slow token-ring network :-/

> I after getting used to it, I thought the Mentor Graphics mouse "strokes" 
> were kind of handy. And I definitely liked the plain text project 
> mapping files (I forget what they were called), something I wish all 
> engineering tools had.

I've not seen project mapping files, or I don't remember.
I was more interested by the cool X-based GUI
and the minimisation of my project's circuit :-)
My personal experience with low-level computing at that time
allowed me to shrink the system to a level almost suitable
for the target chip :-) (all the precedent students
were 10x too large, using unefficient methods)

Since then, my focus has shifted. I have to get
things myself, and secure them so they can be accessed
to whoever wants in the future. In the FPGA world,
where things go faster than ever, it's not easy
so I stayed away until now :-(


Oh, and thanks again for the comments in the other posts.

YG, happy

Article: 131779
Subject: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
From: Bob <rsg.uClinux@gmail.com>
Date: Thu, 1 May 2008 19:26:06 -0700 (PDT)
Links: << >>  << T >>  << A >>
I'm trying to get the .xsvf player in XAPP058 to work, but I haven't
been able to do so.  I have been able to do port.c, and I see signals
that seem quite reasonable.  But the FPGA DONE bit never gets
asserted.

If I enable debugging output, and "play"  a  simple GetIdCode .xsvf
file, I see the chip (Xilinx Spartan-3) responding with the correct
value (0x01434093), so it seems things are more or less okay.

I can play my .xsvf files (which are generated by the svf2xsvf utility
from the app note, downloaded yesterday) in iMPACT, and they work just
fine.

When I Googled it, I found one thread titled "Configuration via JTAG
using an Embedded Controller" from December, but there was not
resolution.  The one responder suggested that if DONE doesn't go high,
then there's a problem; they also guessed that a "post-amble" is
missing, and to re-read the documentation, but I'm not sure what
documentation is being referred to!  I haven't been able to find any
mention of it in XAPP058 nor XAPP503!

Okay, but I'm not sure where to look for this!  I've played the file
using iMPACT, and it works - so it would seem iMPACT adds such a "post-
amble" automagically?  How do I get this into my svf (and hence, xsvf)
files?

Thanks!
-Bob

Article: 131780
Subject: Re: Functional Simulation of Virtex-4 Block Memory
From: Jeff Cunningham <jcc@sover.net>
Date: Thu, 01 May 2008 22:26:27 -0400
Links: << >>  << T >>  << A >>
Is it still true that BRAM arrays with different width ports cannot be 
inferred?

Also, are the BRAM parity bits usable with inference, i.e. can you infer 
a 36 bit wide memory into a single BRAM?

Coregen left a bad taste in my mouth last time I tried to use it for 
BRAM. Instead I find directly instantiating BRAM instances with use of 
the VHDL generate statement to be fairly powerful and flexible.

-Jeff

Article: 131781
Subject: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
From: "MM" <mbmsv@yahoo.com>
Date: Thu, 1 May 2008 22:44:06 -0400
Links: << >>  << T >>  << A >>
"Bob" <rsg.uClinux@gmail.com> wrote in message 
news:294e5ba1-814c-4e98-a4fd-d331ec15ab7e@w74g2000hsh.googlegroups.com...
>
> Okay, but I'm not sure where to look for this!  I've played the file
> using iMPACT, and it works - so it would seem iMPACT adds such a "post-
> amble" automagically?  How do I get this into my svf (and hence, xsvf)
> files?

Bob,

Try creating xsvf directly from iMPACT. Simply choose XSVF file in the 
output menu. When finished writing go to the same menu and choose Finish 
Writing. This works for me...

/Mikhail 



Article: 131782
Subject: Re: Functional Simulation of Virtex-4 Block Memory
From: Duane Clark <user@domaininvalid.com>
Date: Fri, 02 May 2008 03:00:12 GMT
Links: << >>  << T >>  << A >>
Jeff Cunningham wrote:
> Is it still true that BRAM arrays with different width ports cannot be 
> inferred?

That is true, as far as I know. But in that case I like to infer 
multiple BRAMs, and then wire them up (with multiplexers) to handle the 
different port widths.

> Also, are the BRAM parity bits usable with inference, i.e. can you infer 
> a 36 bit wide memory into a single BRAM?

I don't know for sure, but I would be surprised if the synthesis tools 
did that incorrectly.

> Coregen left a bad taste in my mouth last time I tried to use it for 
> BRAM. Instead I find directly instantiating BRAM instances with use of 
> the VHDL generate statement to be fairly powerful and flexible.

That is how I did it for several years, but once I made that change to 
inferring memory, I'll never go back.

Article: 131783
Subject: Re: Functional Simulation of Virtex-4 Block Memory
From: Jeff Cunningham <jcc@sover.net>
Date: Thu, 01 May 2008 23:12:53 -0400
Links: << >>  << T >>  << A >>
Duane Clark wrote:
> Jeff Cunningham wrote:
>> Is it still true that BRAM arrays with different width ports cannot be 
>> inferred?
> 
> That is true, as far as I know. But in that case I like to infer 
> multiple BRAMs, and then wire them up (with multiplexers) to handle the 
> different port widths.

I guess if the performance and resource hit of the external muxes is not 
too bad that could be appealing.

Do you know if giving the bram initial values is handled properly when 
inferring?

-Jeff

Article: 131784
Subject: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
From: Bob <rsg.uClinux@gmail.com>
Date: Thu, 1 May 2008 20:13:10 -0700 (PDT)
Links: << >>  << T >>  << A >>
> Bob,
>
> Try creating xsvf directly from iMPACT. Simply choose XSVF file in the
> output menu. When finished writing go to the same menu and choose Finish
> Writing. This works for me...

Mikhail,

Thanks for the idea, and I just tried it, but sadly, no joy - it still
doesn't work!

Any other ideas, anyone?

Thanks,
Bob


Article: 131785
Subject: Re: Functional Simulation of Virtex-4 Block Memory
From: Mike Treseler <mike_treseler@comcast.net>
Date: Thu, 01 May 2008 20:48:21 -0700
Links: << >>  << T >>  << A >>
Jeff Cunningham wrote:
> Duane Clark wrote:
>> Jeff Cunningham wrote:
>>> Is it still true that BRAM arrays with different width ports cannot 
>>> be inferred?
>>
>> That is true, as far as I know. But in that case I like to infer 
>> multiple BRAMs, and then wire them up (with multiplexers) to handle 
>> the different port widths.

Try it and see.
I have had good luck varying the generics on this example:
  http://mysite.verizon.net/miketreseler/block_ram.vhd

        -- Mike Treseler

Article: 131786
Subject: Re: NIOS II CFI interface
From: "bjzhangwn@gmail.com" <bjzhangwn@gmail.com>
Date: Thu, 1 May 2008 20:59:52 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 5=D4=C21=C8=D5, =CF=C2=CE=E711=CA=B140=B7=D6, ghel...@lycos.com wrote:
> On May 1, 2:27 am, "bjzhan...@gmail.com" <bjzhan...@gmail.com> wrote:
>
> > Hi,everybody,I am a fresher of NIOSII,and in the passed days ,I have
> > been familar with the nios II system,also write some test program
> > about the gpio,timer,uart and can work properly,today I add the flash
> > controoler(CFI),but it doesn't work.And I use the signal tap to watch
> > the wave and the address bus is active but the read,write and cs is
> > always '1',I don't know why,can someone give me some advice and debug
> > methods.
>
> Here are two helpful links:
> <http://www.google.com/search?q=3Ddebug+nios>
> <http://www.google.com/search?q=3Dsimulate+nios>
>
> Here's something to read while you're trying to figure out how to use
> google's search feature:
> <http://www.altera.com/literature/an/an351.pdf>
>
> You really should learn about Google's search feature; it works pretty
> well.  And it's free for google-mail users (such as yourself), and the
> rest of the internet.
>
> Cheers,
> G.
Thanks,I have tried all what you say 2 days before and I have no idear
so I refer to google group for help.Now I know why,Firstly,the flash
chip I use is not support CFI.but the nios II only support CFI
compliant flash.Secondly,because the jtag uart also use jtag ,so if I
use printf function and from the signal tap the singal I watch is
always '1',I  remove the printf function and then the singal is active
in the signal tap.

Article: 131787
Subject: Re: asic gate count
From: Thomas Stanka <usenet_nospam_valid@stanka-web.de>
Date: Thu, 1 May 2008 22:24:34 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 1 Mai, 21:54, "vijayant.rutg...@gmail.com"
<vijayant.rutg...@gmail.com> wrote:
> Ok. I have my design finalized. The fir length would be 64 operating
> on 32 bit wide word. Now could you please hint me on estimating gate
> count ?

Is it serial or parallel? Using RAM or FF? Which ASIC technology?
With tight timing constraints or relaxed timing?

My guess would be 65x32 for storage of input and result and two adders
size 32 bit.

ASIC gate count is a value gained by guess of numbers multiplied with
e^n with n being a marketing factor (technical oriented people assume
n=random(unconstrained) as you can't understand calculation of n if
you'r not member of a marketing department)

bye Thomas




Article: 131788
Subject: Virtex4 Output Pins during Configuration
From: Nemesis <gnemesis2001@gmail.com>
Date: Fri, 2 May 2008 01:27:39 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi all,
I have a problem with a Virtex4 FPGA, I'm using it to control a
motor ... but during the configuration output pins goes high and the
motor moves.
Is there any way to solve the problem without modifying the hardware?
If not ... are pulldown resistors a possible solution? What I mean
is ... even if I put a pulldown resistor if the pin is pulled high by
the FPGA then the pulldown is not useful.

Thank you.

Article: 131789
Subject: Re: PCI Express Switch
From: Kolja Sulimma <ksulimma@googlemail.com>
Date: Fri, 2 May 2008 02:48:52 -0700 (PDT)
Links: << >>  << T >>  << A >>
There is a development board from PLX where a passive PCIe board
connects the PCIe lanes to coax connectors that interface to an
external board with some PLX parts.
This is out of spec but works even at 5gbps (PCIe 2.0)

Kolja Sulimma

On 30 Apr., 15:03, shakith.ferna...@gmail.com wrote:
> Hi all,
>
> Wanted to verify a idea.
> Is is possible use Xilinx PCI express core in FPGA to use SMA ports
> for the physical layers rather than the normal PCI express slots?
> probably some parameters needs to be modified.
>
> Thanks
>
> Shakith


Article: 131790
Subject: Re: asic gate count
From: "RCIngham" <robert.ingham@gmail.com>
Date: Fri, 02 May 2008 05:02:48 -0500
Links: << >>  << T >>  << A >>
"Back in the day", ASIC gate counts were mostly estimated by extrapolating
from previous ASIC designs. If you don't have any such information, your
guess will be as bad as mine. 

Do as Dilbert does, and just make up the numbers ;-) After all, it's only
the shareholders' money, and what have they ever done for you?



Article: 131791
Subject: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
From: Gabor <gabor@alacron.com>
Date: Fri, 2 May 2008 05:30:38 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 1, 11:13 pm, Bob <rsg.uCli...@gmail.com> wrote:
> > Bob,
>
> > Try creating xsvf directly from iMPACT. Simply choose XSVF file in the
> > output menu. When finished writing go to the same menu and choose Finish
> > Writing. This works for me...
>
> Mikhail,
>
> Thanks for the idea, and I just tried it, but sadly, no joy - it still
> doesn't work!
>
> Any other ideas, anyone?
>
> Thanks,
> Bob

When you use iMpact instead of your xsvf player, do you see a warning
about changing the startup clock?  Make sure that the startup clock is
set to JTAG in the configuration settings when you build the bit file.
Also check the startup options to check how many clocks you need at
the end of configuration to set the DONE output.  This may be the
"postamble" mentioned in the other thread.  Theoretically just
adding a few more cycles of TCK at the end of the configuration
process should fix this unless your startup clock is incorrectly
configured to use the CCLK pin instead.

HTH,
Gabor

Article: 131792
Subject: Re: XCF02S not seen in the JTAG chain
From: AugustoEinsfeldt <aee@terra.com.br>
Date: Fri, 2 May 2008 05:44:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi all,
Just to close this subject, I have found two pins on JTAG chain with
bad soldering. The people who assembled the board have assured it was
100% ok. But when all possible logic causes went out then the
impossible one must fit... The pins were perfect for a regular visual
check but they did not resist to a mechanical stress with a small
twezer.
So, problem solved. Sorry taking your time on this. It is a shame I
did not double checked the assembly before asking for help here.
Best regards,
Augusto



Article: 131793
Subject: Re: Chirp generator / CORDIC algo ?
From: XSterna <XSterna@gmail.com>
Date: Fri, 2 May 2008 05:46:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 1, 8:55 pm, "MM" <mb...@yahoo.com> wrote:
> "XSterna" <XSte...@gmail.com> wrote in message
>
> news:6e540612-5af3-4031-851e-ed4a27d20bc8@m3g2000hsc.googlegroups.com...
>
>
>
> > I will work on all ideas because I'm a beginner in all that, so I need
> > time to understand everything :)
>
> Basically your supervisor told you that the FPGA will be used to store an
> arbitrary waveform and to send it to the DAC. No math is supposed to be done
> in it. You are supposed to use MATLAB to design the waveform and then upload
> (or is it download? :)) it to the memory in the FPGA. The FPGA will then
> simply read it back with the DAC sample rate... If you don't need to change
> your waveform quickly and/or you need to be able to "play back" some other
> waveforms then it is the way to go. Otherwise you could drop the MATLAB part
> and design your own hardware chirp generator as Kevin described.
>
> /Mikhail

The Matlab could be (and maybe will be) the best solution but in fact
we will have different chirps to generate. This solution is dependent
to a computer. I will explore the DDS idea and see if I can do it and
if we can meet all the requirements.

Xavier

Article: 131794
Subject: Quartus v7.x fitting bug
From: ian.barnes@renishaw.com
Date: Fri, 2 May 2008 06:00:30 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello,

Just trying this group as a bit of a last resort. I am currently
working on a design that has identified a bug in Quartus v7.x (I have
tried all versions up to 7.2sp3) on a Cyclone based design.

Naturally I was at first very skeptical that the bug was with Quartus,
but after extensive use of signal probe I can see that a shift
register is injecting spurious data. The design isn't particularly
fast and is in one clock domain. What is very strange is that the back
annotated simulation also exhibits the same bug - so I am sure the
problem is with the fitting - not a signal integrity issue with our
board. Looking at the technology map viewer, the LE elements appear to
be as you would expect for a shift register.

We went through some time with mysupport, and Altera finally accepted
that it was a bug. But since then dialog has broken down, we have
heard basically nothing from them about a fix or when it might be
available. Our distributor has also been in direct contact with the
Altera UK & Ireland Channel Manager - but that has also been
unsuccessful.

The support request was opened on the 14 Feb, and the last we heard
any feedback was on the 18th March which is 2.5 months ago (seems
pretty poor if you ask me).

I am not sure what avenue to try next, but hopefully there is someone
reading this at Altera that could get in touch with the possibility of
investigating this problem.

Kind regards,
Ian Barnes.

Article: 131795
Subject: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
From: Bob <rsg.uClinux@gmail.com>
Date: Fri, 2 May 2008 06:40:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 2, 8:30 am, Gabor <ga...@alacron.com> wrote:
> When you use iMpact instead of your xsvf player, do you see a warning
> about changing the startup clock?  Make sure that the startup clock is
> set to JTAG in the configuration settings when you build the bit file.
> Also check the startup options to check how many clocks you need at
> the end of configuration to set the DONE output.  This may be the
> "postamble" mentioned in the other thread.  Theoretically just
> adding a few more cycles of TCK at the end of the configuration
> process should fix this unless your startup clock is incorrectly
> configured to use the CCLK pin instead.

Hi Gabor,

Yes, I do see that warning, at least sometimes.  I've always been a
little confused about that message, but given that it has always
"worked" before, meaning that iMPACT seemed happy to make things
work.  Seems this could well be it.

Looking at the Properties dialog for the "Generate Programming File"
process, I see "FPGA Start-Up Clock" under "Startup Options" , which
is indeed set to CCLK - seems this is the default setting, is that
true?  So you are suggesting I change this to "JTAG Clock", right?
I'm asking this detail because I won't be able to try this until
Sunday, and I don't want to miss something stupid on my part!

And just in case, where do I "check the startup options to check how
many clocks you need"?  Is this in the data sheet?

Thanks, Gabor, I'll let everyone know how it goes!
-Bob

Article: 131796
Subject: Re: Quartus v7.x fitting bug
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 02 May 2008 06:56:30 -0700
Links: << >>  << T >>  << A >>
ian.barnes@renishaw.com wrote:

> Just trying this group as a bit of a last resort. I am currently
> working on a design that has identified a bug in Quartus v7.x (I have
> tried all versions up to 7.2sp3) on a Cyclone based design.
> 
> Naturally I was at first very skeptical that the bug was with Quartus,
> but after extensive use of signal probe I can see that a shift
> register is injecting spurious data. The design isn't particularly
> fast and is in one clock domain. What is very strange is that the back
> annotated simulation also exhibits the same bug - so I am sure the
> problem is with the fitting - not a signal integrity issue with our
> board. Looking at the technology map viewer, the LE elements appear to
> be as you would expect for a shift register.

1. Make sure that your one clock got assigned to a global
clock line. When a clock is routed through the fabric,
even for a short excursion, hold violations will occur and shifters
don't always shift right. What is the worst slack time on your
STA report?  Make sure to use the newer of two static
timers. Any odd or complicated constraints? Are all paths
being covered?

2. Double check your design rules.
Are all processes synchronous using
a standard template? Is the reset pulse
synchronized to the clock on deassertion?
Any odd IP or generated code or netlists?

3. Check your functional sims for coverage
and add some edge cases.

4. Zero in on the problem area by slicing
out pieces of the design. Make a simple entity
that demonstrates the problem.

5. Find out who your local FAE is and call him every day.

Good luck.

             -- Mike Treseler


Article: 131797
Subject: xilinx remote platform flash program
From: bishopg12@gmail.com
Date: Fri, 2 May 2008 07:17:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
We are trying to develop a system that utilizes a Xilinx XC4VFX12 chip
and platform flash.  One of our main goals is to be able to remotely
upgrade the bitfiles in the platform flash through ethernet and
rs232.  Is it possible to program the platform flash from the fpga/
powerpc core using the jtag chain?  My idea was to have the powerpc
get the bitfile from whatever source, store it in ram, then send it to
the platform flash using some type of jtag interface (soft core or
software on the powerpc).  Many of the examples I have seen involve
using cplds and other external logic, not this way.

Article: 131798
Subject: Re: Quartus v7.x fitting bug
From: KJ <kkjennings@sbcglobal.net>
Date: Fri, 2 May 2008 07:23:15 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 2, 9:00=A0am, ian.bar...@renishaw.com wrote:
>
> I am not sure what avenue to try next, but hopefully there is someone
> reading this at Altera that could get in touch with the possibility of
> investigating this problem.
>

1. Keep pestering on mySupport for an update on when a fix or work
around will be available.

2. As Mike suggested, keep pestering the local FAE to get a fix or
work around.

3. If the problem can be described fairly easily without getting into
all the nuances of your entire design, then post your code, the
problem description and maybe someone here can come up with a work
around.

Good luck

Kevin Jennings.

Article: 131799
Subject: Re: Virtex4 Output Pins during Configuration
From: austin <austin@xilinx.com>
Date: Fri, 02 May 2008 07:39:22 -0700
Links: << >>  << T >>  << A >>


Nemesis,

How is the HSWAP_EN pin connected?  This enables/disables the internal
weak pullups while configuring.

If the weak pullup is not enabled, then the pin is tristate while
powering ON.

http://www.xilinx.com/support/documentation/user_guides/ug071.pdf

Table 1.1, note 2 page 14; and Table 1.2 page 15.

In any case, the IO pins always have their intrinsic diodes internally:

gnd-------->|--------IO pin------>|------Vcco

So, the pin voltage can not be much less than ground, and not much more
than Vcco, as then these diodes are forward biased, and the pin is
clamped +/- diode drop from ground (for negative voltages) and Vcco (for
voltages greater than Vcco).

Since you seem to have the problem that the pin is going high while
configuring, it is not anything to do with the diodes.

A pulldown resistor, once the IOs are set to be tristate while
configuring, is the probably answer.  The IO pin leakage worst case is
10uA, so if there is no other leakage, the pulldown could be something
like 10K or 100K ohms, and be sufficient.

Even a very weak LVCMOS IO standard should be able to pull up 10K to the
Vcco rail.

Austin



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