Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Thanks for Your answer, Matthew But, I am not shure that I understood You well. How did You mean to combine input and output signal? I need one pin that in one moment sends high voltage on the output, and in the time that follows it reads the input from the same wire. I never used this method so I am very confused. Thanks again for Your answer Zoran Matthew Hicks wrote: > If this is for a half-duplex bus application, I think it is prefered to have > two signals, one input and one output and to combine them at the top level > with the appropriate buffers, instead of a single input/output signal. That > way, it is clear what is being sent out and that is being brought in. If > the inout is just so you can read a value that you are outputting, then it > is best to use an internal signal that holds the value to output. This means > that you can both drive a value on the line and read the value at the same > time. > > > ---Matthew Hicks > > > > Hi, > > I start work on some project involving FPGA and I have to define port > > as bidirectional (inut-output). > > I know that in VHDL there is keyword "inout" when defining port, but I > > don't know what detirminats that this kind defined port would be input > > or output. > > Thanks for any kind of help > > ZoranArticle: 122751
On 6 Aug., 10:06, jitendra <jitendrakumarpoth...@gmail.com> wrote: > hi all, > i am new to this group and i am beginner in this FPGA field so i need > ur help to find some material regarding FPGA i hope u people can help > me out > thank u www.google.comArticle: 122752
Hi N.V., N.V. Chandramouli schrieb: > We are also able to establish the connection to the virtex-4 Fx12 LC > development board, (the message log says so. ) but we are getting the > following error: > > ********************** > ERROR:iMPACT:1062 - Can only assign files to devices between positions > 1 to 2 > ********************** When trying to do - what? Updating the procesor bitstream? The message just tells you that there are only two devices on your JTAG chain (the Virtex and some flash memory) and you obviously have tried to program some other device. I guess you tried to upload an application image to your PPC inside the FPGA, but perhaps your design does not include the JTAG interface for that one? Greetings, TorstenArticle: 122753
Also www.xilinx.comArticle: 122754
On Aug 4, 1:04 pm, Eli Billauer <e...@billauer.co.il> wrote: > Hello, > > I would like to utilize a controller for a SINGLE data rate SDRAM > (Micron MT48LC16M16A2TG-75, to be specific). In the past I've used > Xilinx' MiG 1.4 to obtain a DDR2 controller, which I ended up pretty > happy with (after forgetting the via dolorosa to set it up...). Its > main benefit is a simple and convenient FIFO-based user interface. > > For some reason, I thought that MiG would create an SDR controller as > well (it's simpler, after all), but it turned out I'm very wrong: The > last piece of attention on Xilinx' behalf to SDR, which I've managed > to find, is xapp134. That paper, along with its HDL code, originates > in 1999, and is more or less the same ever since. The controller > offered is hence adapted to Virtex-I and Spartan-II, and is yucky is > several respects. > > Newer application notes (as well as MiG) relate to faster memory > classes (DDR, DDR2, QDR, you name it), with controllers eating up some > clock resources to solve timing problems. And all I wanted was a cheap > memory with reasonably simple access. > > Given the situation, I'm considering to create a DDR controller with > MiG for a memory with similar attributes (bus width, array size, etc) > and then hack it down to SDR. Since the command interface is the same, > that should leave me with changing the data flow, and make the burst > timing right. Not much fun, but hey, after debugging the MiG DDR > controller, I should survive this one as well. > > And here's the irony: I picked this SDRAM to make things simpler for > me. > > So before I start this little self torture, does anyone have a better > idea? > > Thanks, > Eli I have the same problems, just I want to SDR in an MB embedded system. Luckily I know that Xilinx OPB SDRAM controller sucks so the new Spartan3E boards will have DDR on board. If you need only 1kB FIFO style burst transfers than I can provide you with some working example. Cheers, GuruArticle: 122755
Eli Billauer <eli@billauer.co.il> writes: > Given the situation, I'm considering to create a DDR controller with > MiG for a memory with similar attributes (bus width, array size, etc) > and then hack it down to SDR. Since the command interface is the same, > that should leave me with changing the data flow, and make the burst > timing right. Not much fun, but hey, after debugging the MiG DDR > controller, I should survive this one as well. > > And here's the irony: I picked this SDRAM to make things simpler for > me. > > So before I start this little self torture, does anyone have a better > idea? Write one from scratch? SDR SDRAM is (as you rightly say) fairly straight-forward, especially if you don't need to maximise bandwidth, so you can have a simple state machine controlling it. I did one a very long time ago (my first bit of serious VHDL, so it can't have been that hard :-)... Alternatively, you could use a DDR controller and ignore every other byte :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 122756
If that's what you need, just use the method that uses an internal signal
tha hold the value that you want to output. Drive the output directly from
the internal signal. You can also read the internal signal to see what value
is driving the output.
The code snippet below gives an example of the above. This achieves the
same effect as using an inout signal.
port(...
output : out std_logic;
...
);
signal outValue : std_logic;
...
begin
...
process(clk)begin
if(clk'event and clk = '1')then
if(outValue = '0')then
...
end if;
end if;
end process;
...
output <= outValue
...
---Matthew Hicks
> Thanks for Your answer, Matthew
>
> But, I am not shure that I understood You well. How did You mean to
> combine input and output signal? I need one pin that in one moment
> sends high voltage on the output, and in the time that follows it
> reads the input from the same wire. I never used this method so I am
> very confused.
>
> Thanks again for Your answer
> Zoran
> Matthew Hicks wrote:
>
>> If this is for a half-duplex bus application, I think it is prefered
>> to have
>> two signals, one input and one output and to combine them at the top
>> level
>> with the appropriate buffers, instead of a single input/output
>> signal. That
>> way, it is clear what is being sent out and that is being brought in.
>> If
>> the inout is just so you can read a value that you are outputting,
>> then it
>> is best to use an internal signal that holds the value to output.
>> This means
>> that you can both drive a value on the line and read the value at the
>> same
>> time.
>> ---Matthew Hicks
>>
>>> Hi,
>>> I start work on some project involving FPGA and I have to define
>>> port
>>> as bidirectional (inut-output).
>>> I know that in VHDL there is keyword "inout" when defining port, but
>>> I
>>> don't know what detirminats that this kind defined port would be
>>> input
>>> or output.
>>> Thanks for any kind of help
>>> Zoran
Article: 122757Can anyone tell me how to command the plb_ddr core to put my external ddr sdram into self refresh mode? Thanks, ClarkArticle: 122758
I am now preparing the project: encryption data stored in the SATA
disk. I want to realize a device placed between the pc and SATA disk
as following:
PC SATA controller <-----> FPGA board <---------> SATA disk
I planed to use the SATA phy chip on the FPGA board to receive and
send the SATA signal. However, I found it's difficult to buy the SATA
phy. Whether I can use the FPGA chip to cope with the SATA signal
directly? Any suggestion is appreciated.
Article: 122759On 3 aug, 23:48, "John_H" <newsgr...@johnhandwork.com> wrote: > "Dolphin" <Karel.Dep...@gemidis.be> wrote in message > > news:1185955958.976050.126800@o61g2000hsh.googlegroups.com... > > > > > Hello, > > > We have implemented a variable phase shift in a spartan 3E device. The > > phase shift can be set with a register. Normally the PSDONE signal > > should go high when a phase shift is performed. This happens but takes > > a long time (several minutes). The datasheet says : > > > "The phase adjustment might require as many as 100 CLKIN > > cycles plus 3 PSCLK cycles to take effect, at which point the > > DCM's PSDONE output goes High for one PSCLK cycle. > > This pulse indicates that the PS unit completed" > > > However it seems that our design is much slower... > > The DCM that does the phase shift gets its clock from another DCM. > > Could it be that there is too much jitter on this clock? > > > Anybody had a similar problem? > > > Thanks and best regards, > > Karel Deprez > > Sorry I missed your post - business travel for a couple days. > > My experience with the Spartan 3E shows that under some circumstances, the > PSDONE is delayed. I was doing a significant number of phase tweaks back > and forth under some conditions with one source behaving quite different > than another (different designs, same effective signal). It seems - from > discussions with people deep within Xilinx while pursuing these troubles - > the phase shift is held off because the "Input clock is jittery with some > special jitter pattern. The skew filter kicks in, managing DLL updates > based on short term avg of input phase. Variaple updates are also delayed > with other DLL updates. > > I'd suggest you call the apps hotline and indicate you're having troubles > with the PSDONE arriving in a timeliy manner, and that you'd like "a back > door code to turn off skew filter (using a -g option in)." You'll need to > provide the exact DCM location you are using for that option. > > "Then PSEN->PSDONE cycles will be roughly 10 deterministic cycles." > > While it was suggested that I could discontinue the -g option once I > debugged the problem, the "problem" as I saw it was the DCM wasn't working > for my input signal. I never changed the option back, but we are currently > troubleshooting around that same front end. > > It may be the very nature of the jitter on the DCM feeding your second DCM > is why there are troubles getting the skew filter to cooperate. > > In my own measurements, I ran a histogram of the number of cycles it took > for my system to generate PSDONE. The results suggested that - in my > circumstance - the deterministic data sheet values were not reliable. With > the specific -g option, the system worked and worked solid. What was most > fun was watching the DCM lose lock (without saying so) when I'd retry the > PSEN after not receiving it for too long at the same cycle the PSDONE > asserts (512 cycles later, for one timeout setting). By just retrying the > PSEN, I'd eventually see the original PSDONE but when they tripped on each > other in this strange situation, there might be lock troubles. The > unreported lock loss was always preceeded by the PSEN reissue coincident > with PSDONE report. I don't know if the inverse was true (it probably was > not, given the number of delays extending this far). > > - John_H Hi John, I've passed your information to the Xilinx support. Thanks end best regards, KarelArticle: 122760
I use Cyclone II to implement image processing. There are a CMOS image sensor, a FPGA chip, and a SRAM on my board. I meet a new problem when I try to optimize my design. In my old instance, I use the same clock when image capture (storage), image display, and image processing. This clock, which is named "pclk", has a frequency of 24MHz. It is slow. The frequency of image capture and display cannot be changed because of the requirement of other device. So I want to increase the frequency of image processing. It involves SRAM reading, writing, and data processing. I use a PLL to acquire a clock of 72MHz. This is the problem. SRAM will also be read when image capture, and written when display. That means the clock, the address bus and data bus will be switched between the state of image capture/display and image process. Actually, I use two blocks: one for image capture/display and another for image process. And I use BUS MUX to switch address bus and data bus. Meanwhile, I use LPM MUX to switch the two clock of different frequency. Unfortunately, the instance does not meet timing. In Timing Analyzer Summary, it reports, Clock setup: 'pclk' has a slack of -4.152ns and Clock hold: 'pclk' has a slack of -4.216ns. What should I do to solve this problem? Best Regards, X.Y.Article: 122761
Zoran, Sounds like you want something like this: inoutpin <= outputsignal when enable = '1' else 'Z'; inputsignal <= inoutpin; When enable is '1', outputsignal controls the output and inputsignal will be same as outputsignal. When enable is '0', inoutpin is not driven from FPGA and inputsignal will be controlled by an external device driving inoutpin. -JeffArticle: 122762
On 6 Aug., 16:16, IDDLife <xing.starw...@gmail.com> wrote: > I am now preparing the project: encryption data stored in the SATA > disk. I want to realize a device placed between the pc and SATA disk > as following: > PC SATA controller <-----> FPGA board <---------> SATA disk > > I planed to use the SATA phy chip on the FPGA board to receive and > send the SATA signal. However, I found it's difficult to buy the SATA > phy. Whether I can use the FPGA chip to cope with the SATA signal > directly? Any suggestion is appreciated. there is NO NEED todo such thing as Silicon Image has specialized SoCs for exactly this purpose. the FPGA solution would cost 10x the price of the specialized ASSP AnttiArticle: 122763
On 6 Aug, 15:16, IDDLife <xing.starw...@gmail.com> wrote: > I am now preparing the project: encryption data stored in the SATA > disk. I want to realize a device placed between the pc and SATA disk > as following: > PC SATA controller <-----> FPGA board <---------> SATA disk > > I planed to use the SATA phy chip on the FPGA board to receive and > send the SATA signal. However, I found it's difficult to buy the SATA > phy. Whether I can use the FPGA chip to cope with the SATA signal > directly? Any suggestion is appreciated. SATA phy are a nightmare to get hold of in small quantities, I found. Apparently some of the Virtex series can do SATA directlyish (IIRC theres a small circuit needed for OOB data) with their rocketIO stuff. Several companies offer IP for either ends of SATA. Your best bet may be the lattice ecp2m series (although I believe they are either not- released or damn-hard-to-locate-in-sub-10k-quantities ;)). I've only really messed with Xilinx stuff so thats all I can say. How compliant do you need it to be? Good luck, anyway..Article: 122764
On Aug 4, 12:37 pm, "N.V. Chandramouli" <mouli1...@gmail.com> wrote: > ERROR:iMPACT:1062 - Can only assign files to devices between positions > 1 to 2 If you are trying to download from XPS, perhaps you need to edit the download script in etc/download.cmd Alan Nishioka From Iwo.Mergler@soton.sc.philips.com Mon Aug 06 09:31:12 2007 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!nx01.iad01.newshosting.com!newshosting.com!novia!newsfeed.yul.equant.net!lon04-news-philips!53ab2750!not-for-mail Message-Id: <gvujo4-hld.ln1@c2968.soton.sc.philips.com> From: Iwo Mergler <Iwo.Mergler@soton.sc.philips.com> Subject: Re: bidirectional pin Newsgroups: comp.arch.fpga References: <1186341732.470294.316820@w3g2000hsg.googlegroups.com> Lines: 35 Organization: Not organised User-Agent: KNode/0.9.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Date: Mon, 06 Aug 2007 17:31:12 +0100 NNTP-Posting-Host: 161.85.127.140 X-Complaints-To: newsmaster@rain.fr X-Trace: lon04-news-philips 1186418890 161.85.127.140 (Mon, 06 Aug 2007 16:48:10 GMT) NNTP-Posting-Date: Mon, 06 Aug 2007 16:48:10 GMT Xref: prodigy.net comp.arch.fpga:134659 X-Received-Date: Mon, 06 Aug 2007 12:47:38 EDT (newsdbm02.news.prodigy.net) Zorjak wrote: > Hi, > I start work on some project involving FPGA and I have to define port > as bidirectional (inut-output). > I know that in VHDL there is keyword "inout" when defining port, but I > don't know what detirminats that this kind defined port would be input > or output. > Physically, a bidirectional port is a device with three internal connections - 'in', 'out' and 'oe'. When 'oe' is active, the value of 'out' is driven on the pin, otherwise the output driver is off. At any time, you can read the current pin value on the 'in' signal. When you drive the pin, you read back the value you are driving (output mode), when you are not driving the pin, you read back the pin state as determined by external circuitry. In VHDL, if you set the signal value to 'Z', you disable the output driver. At that point you can read the external value from the signal. It is common to map the VHDL inout signal into the three separate signals somewhere at the top of your VHDL hierarchy, as Mathew and Jeff have pointed out. Kind regards, IwoArticle: 122765
SATA, Has been characterized and verified on Virtex 5 GTP transceivers. We are preparing the report for publication. Get with your FAE for more details, AustinArticle: 122766
On Aug 6, 4:04 am, makhan <mansoor.nas...@gmail.com> wrote: > On Aug 6, 7:43 am, EEngineer <mari...@gmail.com> wrote: > > > > > > > On Aug 5, 7:34 am, fpgauser <fpgaengineerfrankf...@arcor.de> wrote: > > > > Do you need real time access, or more debug information? > > > > I would take a serial connection (open cores has them) and an > > > intelligent PC COM software. There are several which are able to > > > completely receive large data streams. So there is not much work to > > > do. Possibly you need a level converter like the MAX x232. You may > > > also want to transform the rams into dual port mems to easier access > > > them. > > > For now 115kbits/s would be OK for me as the design I am testing needs > > to send a content of 16Kb BRAM data at a time, transfer time of > > several seconds would be fine. But when I expand my design USB > > transfer would be much better but I am not sure yet how much more > > complicated would be to make use of the USB port on my FPGA. > > > -Dan > > Hi, > > You might want to consider using chipscope pro, provided if you have > BRAMs for its storage. Chipscope will store your signals in real time > (at FPGAs clock speed) and after capturing, display them on its > analyser. You will be severly limited by the amount of BRAM though. > Given enough block ram you can store upto 16k samples of a signal. If > you insert single logic analyser core (ILA core), then you can store > upto 256 signals for display later. You can trigger your signals at > any combination or desired point. > I have been using chipscope before, evaluation version, I found out that it works up to 16K samples which was exactly what I needed. The problem was that the whole procedure was tedious for the amount of tests I wanted to perform. I needed to transform the downloaded data file with matlab in order to get the desired format so I could calculate PSNR. Chipscope is good for debugging where you have to watch many signals (you can capture up to 256 at a time) but it is not convenient to download the data from the FPGA. > Putting USB in a system is a complete new project with its > complexities. You will need an external protocol negotiator (since you > wouldn't want to write your own IP). So a microcontroller with all the > issues resolved may offer a solution and USB data in form of FIFOs > which can then be interfaced with the FPGA for data readout. You will > require a PCB redesign in that case. Cypress, Microchip etc. offer > microcontrollers with USB hardwired USB Protocol resolvers inside. > I guess that Ethernet interface requires similar steps to implement as USB? Maybe I will just go for open cores and UART then, and do the faster interfaces later down do road, when I need faster data rates. -Dan > Hope this helps. > > Mak- Hide quoted text - > > - Show quoted text -Article: 122767
"austin" <austin@xilinx.com> wrote in message news:f97j08$gtp2@cnn.xilinx.com... > SATA, > > Has been characterized and verified on Virtex 5 GTP transceivers. > > We are preparing the report for publication. > > Get with your FAE for more details, > > Austin Way to go Xilinx! I also look forward to the report.Article: 122768
Any Ideas?Article: 122769
Actually, you can use TCL to control ChipScope for data IO. If you don't need huge amounts of data, this is the easiest to implement and less all-around hassel way of doing it. It runs in a command window even, no GUI required. Dump the data to a file, or shared memory, or send it out on a socket, and Matlab won't know the difference. ---Matthew Hicks > On Aug 6, 4:04 am, makhan <mansoor.nas...@gmail.com> wrote: > >> On Aug 6, 7:43 am, EEngineer <mari...@gmail.com> wrote: >> >>> On Aug 5, 7:34 am, fpgauser <fpgaengineerfrankf...@arcor.de> wrote: >>> >>>> Do you need real time access, or more debug information? >>>> >>>> I would take a serial connection (open cores has them) and an >>>> intelligent PC COM software. There are several which are able to >>>> completely receive large data streams. So there is not much work to >>>> do. Possibly you need a level converter like the MAX x232. You may >>>> also want to transform the rams into dual port mems to easier >>>> access them. >>>> >>> For now 115kbits/s would be OK for me as the design I am testing >>> needs to send a content of 16Kb BRAM data at a time, transfer time >>> of several seconds would be fine. But when I expand my design USB >>> transfer would be much better but I am not sure yet how much more >>> complicated would be to make use of the USB port on my FPGA. >>> >>> -Dan >>> >> Hi, >> >> You might want to consider using chipscope pro, provided if you have >> BRAMs for its storage. Chipscope will store your signals in real time >> (at FPGAs clock speed) and after capturing, display them on its >> analyser. You will be severly limited by the amount of BRAM though. >> Given enough block ram you can store upto 16k samples of a signal. If >> you insert single logic analyser core (ILA core), then you can store >> upto 256 signals for display later. You can trigger your signals at >> any combination or desired point. >> > I have been using chipscope before, evaluation version, I found out > that it works up to 16K samples which was exactly what I needed. The > problem was that the whole procedure was tedious for the amount of > tests I wanted to perform. I needed to transform the downloaded data > file with matlab in order to get the desired format so I could > calculate PSNR. Chipscope is good for debugging where you have to > watch many signals (you can capture up to 256 at a time) but it is not > convenient to download the data from the FPGA. > >> Putting USB in a system is a complete new project with its >> complexities. You will need an external protocol negotiator (since >> you wouldn't want to write your own IP). So a microcontroller with >> all the issues resolved may offer a solution and USB data in form of >> FIFOs which can then be interfaced with the FPGA for data readout. >> You will require a PCB redesign in that case. Cypress, Microchip etc. >> offer microcontrollers with USB hardwired USB Protocol resolvers >> inside. >> > I guess that Ethernet interface requires similar steps to implement as > USB? > Maybe I will just go for open cores and UART then, and do the faster > interfaces later down do road, when I need faster data rates. > -Dan > >> Hope this helps. >> >> Mak- Hide quoted text - >> >> - Show quoted text - >>Article: 122770
On Aug 6, 12:31 pm, Iwo Mergler <Iwo.Merg...@soton.sc.philips.com> wrote: > Zorjak wrote: > > Hi, > > I start work on some project involving FPGA and I have to define port > > as bidirectional (inut-output). > > I know that in VHDL there is keyword "inout" when defining port, but I > > don't know what detirminats that this kind defined port would be input > > or output. > > Physically, a bidirectional port is a device with > three internal connections - 'in', 'out' and 'oe'. > > When 'oe' is active, the value of 'out' is driven > on the pin, otherwise the output driver is off. At > any time, you can read the current pin value on the > 'in' signal. > > When you drive the pin, you read back the value you > are driving (output mode), when you are not driving > the pin, you read back the pin state as determined > by external circuitry. > > In VHDL, if you set the signal value to 'Z', you disable > the output driver. At that point you can read the external > value from the signal. > > It is common to map the VHDL inout signal into the > three separate signals somewhere at the top of your > VHDL hierarchy, as Mathew and Jeff have pointed out. > > Kind regards, > > Iwo Zoran, I agree with Jeff and Iwo, see Jeff's code above. One thing that I would add is when the signal value is set to 'Z' it means 'High impedance mode' - you are not driving that pin from inside the FPGA in that case, but rather you are able to sense what signal is coming to that pin from the outside towards the inside of the FPGA. Hope this helps, DanArticle: 122771
X.Y. wrote:
I use two blocks: one for image capture/display and another
> for image process. And I use BUS MUX to switch address bus and data
> bus. Meanwhile, I use LPM MUX to switch the two clock of different
> frequency. Unfortunately, the instance does not meet timing. In Timing
> Analyzer Summary, it reports, Clock setup: 'pclk' has a slack of
> -4.152ns and Clock hold: 'pclk' has a slack of -4.216ns.
If I had to actually switch the clock
rather than use the preferred clock enables,
I would make separate capture and process
entities and run timing separately.
A clean switch-over must be guaranteed
somehow by design. Maybe handled by software.
--- Mike Treseler
Article: 122772I have a design that instantiates four copies of a module and I am using Xilinx's AREA_GROUP constraint to partition each instantiation into its own 1/8th sector of the FPGA. I ran across a few problems. One, how do I convey these constraints to Synplify (v8.8) for my final implementation run? I tried xc_area_group constraints on each top-level instance name, but either my format is wrong or it just doesn't feel the need to respect them, because they get placed in rectangular fashion around the center of the FPGA. On a similar note, would it be better to use RLOC constraints for what I am trying to do instead? My main problem is in ISE 9.1.03 when attempting to Map the design. I get the error message below at phase 1.1. I also listed the contents of my .ucf file below. I don'y get this error when "Resource Sharing" is turned on. I still get the error though even when "Use RLOC" is off. Any suggestions? ERROR:Place:293 - The following 13 components are required to be placed in a specific relative placement form. The required relative coordinates in the RPM grid (that can be seen in the FPGA Editor) are shown in brackets next to the component names. Due to placement constraints it is impossible to place the components in the required form. LUT FPU1/Madd_tmp_expAB_addsub0001_cy(1) (0, 0) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(1) (0, 0) FF FPU1/Madd_tmp_expAB_addsub0001_cy(1) (0, 0) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(3) (0, 1) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(3) (0, 1) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(5) (0, 2) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(5) (0, 2) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(7) (0, 3) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(7) (0, 3) LUT N14610 (0, 4) LUT N14610 (0, 4) LUT FPU1/Madd_tmp_expAB_addsub0001_cy(8) (0, 5) FF FPU1/Madd_tmp_expAB_addsub0001_cy(8) (0, 5) NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 40 ns HIGH 50 %; INST "FPU1/*" AREA_GROUP = FPU1Group; AREA_GROUP "FPU1Group" RANGE = SLICE_X0Y0:SLICE_X51Y63; AREA_GROUP "FPU1Group" RANGE = RAMB16_X0Y0:RAMB16_X1Y7; AREA_GROUP "FPU1Group" GROUP = CLOSED; AREA_GROUP "FPU1Group" PLACE = CLOSED; AREA_GROUP "FPU1Group" COMPRESSION = 0; INST "FPU2/*" AREA_GROUP = FPU2Group; AREA_GROUP "FPU2Group" RANGE = SLICE_X0Y64:SLICE_X51Y127; AREA_GROUP "FPU2Group" RANGE = RAMB16_X0Y8:RAMB16_X1Y15; AREA_GROUP "FPU2Group" GROUP = CLOSED; AREA_GROUP "FPU2Group" PLACE = CLOSED; AREA_GROUP "FPU2Group" COMPRESSION = 0; INST "FPU3/*" AREA_GROUP = FPU3Group; AREA_GROUP "FPU3Group" RANGE = SLICE_X0Y128:SLICE_X51Y191; AREA_GROUP "FPU3Group" RANGE = RAMB16_X0Y16:RAMB16_X1Y23; AREA_GROUP "FPU3Group" GROUP = CLOSED; AREA_GROUP "FPU3Group" PLACE = CLOSED; AREA_GROUP "FPU3Group" COMPRESSION = 0; INST "FPU4/*" AREA_GROUP = FPU4Group; AREA_GROUP "FPU4Group" RANGE = SLICE_X0Y192:SLICE_X51Y255; AREA_GROUP "FPU4Group" RANGE = RAMB16_X0Y24:RAMB16_X1Y31; AREA_GROUP "FPU4Group" GROUP = CLOSED; AREA_GROUP "FPU4Group" PLACE = CLOSED; AREA_GROUP "FPU4Group" COMPRESSION = 0; ---Matthew HicksArticle: 122773
On Aug 6, 12:00 pm, Alan Nishioka <a...@nishioka.com> wrote: > On Aug 4, 12:37 pm, "N.V. Chandramouli" <mouli1...@gmail.com> wrote: > > > ERROR:iMPACT:1062 - Can only assign files to devices between positions > > 1 to 2 > > If you are trying to download from XPS, perhaps you need to edit the > download script in etc/download.cmd > > Alan Nishioka Dear Alan Nishioka, thank you for the suggestion . May I know how can I modify the download script , to effect the downloading bitstream from xps itself. what is the other procedure if any to download . which one might be easier to understand and implement for me as a neophyte. thanks and regards vijayArticle: 122774
On Aug 6, 6:34 am, Torsten Landschoff <t.landsch...@gmx.de> wrote: > Hi N.V., > > N.V. Chandramouli schrieb: > > > We are also able to establish the connection to the virtex-4 Fx12 LC > > development board, (the message log says so. ) but we are getting the > > following error: > > > ********************** > > ERROR:iMPACT:1062 - Can only assign files to devices between positions > > 1 to 2 > > ********************** > > When trying to do - what? Updating the procesor bitstream? The message > just tells you that there are only two devices on your JTAG chain (the > Virtex and some flash memory) and you obviously have tried to program > some other device. > > I guess you tried to upload an application image to your PPC inside > the FPGA, but perhaps your design does not include the JTAG interface > for that one? > > Greetings, Torsten thank you for the suggestion Mr, Torsten. i remember to have enabled jtag interface for the PPC on which I am downloading the software, but still I am having problems downloading the bitstream.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z