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Hi, Has anyone used more than 4 clocks in the virtex. If so did you have any problems using the secondary global routing resources. I have used up all the 4 global buffers and have to use another clock for part of my design. Thanks, HannahArticle: 25201
<rant deleted> Though the Xilinx 'special' reader seems to have some undesirable issues (and shouldn't exist in the first place....in my opinion), overall, having PDF versions of data sheets is marvelous. Having them on-line, able to print out JUST the sheets I need, or even having them searchable is far far far more efficient than the old printed data book. Also, latest revisions are far easier to get than to wait for next years data book... I, for one, have no problem with on-line PDF documentation...and I do still like the printed data books, and believe they should be still be made available. There are times that having the data book next to you in the lab is good. The latest Acrobat reader allows you to print out double sided documents, you have to print the even pages, in reverse order, then put them back in the paper input tray, and print the odd pages. Make sure you put them in the right direction. It works great for me. I think calling someone names, and then expecting them to listed, doesn't usually work well. Your issues certainly have merit, but would probably be better received with a little more tact.Article: 25202
Well we found a solution but it was a hack. Unfortunately, all we got back from Xilinx tech support was a BSDL file which did not work as described. What we had to do was do take that BSDL file that they sent us and do a text search and replace for XC2S200 and replace it with XCV200!!! What a hack! Oh well, it seems to be up and running. Hopefully Xilinx will do a fix to their JTAG programmer softare in their service pack 3. KevinArticle: 25203
"Matthew S. Staben" wrote: > On Mon, 28 Aug 2000 18:34:39 -0700, Jon Kirwan wrote: > > >On Fri, 25 Aug 2000 19:22:18 -0700 (PDT), "Matthew S. Staben" > ><mstaben@poboxes.com> wrote: > > [snip] > > >One problem I've observed is the feelings that some folks have over > >them. I discussed a recent case where a company had an NDA in hand > >that they believed allowed them power they didn't frankly have. In > >the process of trying to force the issue, they demolished important > >relationships that they needed. > > > >The court never got involved. But bad feelings abounded over little. > > Jon, > > Another point I'd like to make obvious is how restricting a set of signed NDAs could > be at subsequent interviews. > > Q: "Well, I signed this one there, and this other one elsewhere. Do these NDA > documents screw me here?" > A: "Well, sign this NDA and I'll send these over to our corporate attorney and we'll > figure something out." > > Matt I am not having an easy time imagining how an NDA signed for the purposes of an interview at one company would cause a difficulty interviewing or signing an NDA (for the purposes of the interview) at another company. Do you have a fairly concrete example of how such a difficulty would come about? Typically at an interview you talk about your own skills and substantial experiences that would relate to the potential job. What company specific information someone might give to you at one interview would seem far afield of the information you are expected to provide about yourself at another interview. Regards, Neil NelsonArticle: 25204
John Larkin wrote: > > Greg, > > supplementary rant: I just *hate* it when a PDF file, on CD or online, > has a file name that has nothing to do with the part itself. On the > Xilinx CD, all the file names are nonsense, and you have to go through > an HTML page or something to find things. This is crazy! TI is notorious for that. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25205
rickman wrote: > > I am not board layout engineer, but one rule that should always work to > give you good signals on a board trace is to use very short point to > point traces. The round trip delay is about 1 nS per foot. With a edge > time of .5 to 1 nS the round trip time needs to be less than this. So > you get about 3 to 4 inches of trace as a maximum before you need to > worry about terminations, etc. In the "Rule Of Thumb" department, I use the equation in Johnson/Graham's _High Speed Digital Design_: l = Tr/D where l = length of rising edge in inches, Tr = rise time, ps, and D = delay, ps/in They also give delays for FR4. An trace in FR4 has a delay of about 140-180 ps. I then ran the board through Hyperlynx BoardSim, and it told me what my problems were! -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25206
Greetings This is semimonthly announcement of Verilog FAQ. Verilog FAQ is located at http://www.angelfire.com/in/verilogfaq/ Alternate Verilog FAQ is an attempt to gather the answers to most Frequently Asked Questions about Verilog HDL in one place. It also contains list of publications, services, and products. Alternate Verilog FAQ is divided into three logical parts. Part 1 : Introduction and misc. questions Part 2 : Technical Topics Part 3 : Tools and Services What's New section outlines the changes in different versions and announcements. Links connects you to related informative links in internet. Your suggestions to make this FAQ more informative are welcome. Rajesh Bawankule (Also Visit Verilog Center : http://www.angelfire.com/in/rajesh52/verilog.html ) Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25207
"K. Orthner" wrote: > Most FPGA's don't have latches available for use. Usually FPGA's consist > of combinational logic element (Such as LUTs), and Flip-Flops. > > It is possible to use a latch in your design, and it will synthesize, but > it's rather inefficient, because the synthesis tool "creates" the latch out > of normal logic elements. It really depends on the architecture of the FPGA how a latch is generated. Often a simple D latch only takes up 1 CLB. Latches are most often used to buffer data and control lines. Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "New 24 bit CPU" http://www.jetnet.ab.ca/users/bfranchuk/index.htmlArticle: 25208
Neil Nelson wrote: > > Another point I'd like to make obvious is how restricting a set of signed NDAs could > > be at subsequent interviews. > > > > Q: "Well, I signed this one there, and this other one elsewhere. Do these NDA > > documents screw me here?" > > A: "Well, sign this NDA and I'll send these over to our corporate attorney and we'll > > figure something out." > > > > Matt > > I am not having an easy time imagining how an NDA signed for the purposes of an > interview at one company would cause a difficulty interviewing or signing an NDA > (for the purposes of the interview) at another company. Do you have a fairly > concrete example of how such a difficulty would come about? Typically at an > interview you talk about your own skills and substantial experiences that would > relate to the potential job. What company specific information someone might give > to you at one interview would seem far afield of the information you are expected to > provide about yourself at another interview. > > Regards, > > Neil Nelson The concern is not that you could not interview with other companies. The concern is that by promising not to disclose information to others, you may be limited as to what you can work on for a new company. Certainly it is best if you don't have any restrictions. But just by working on a similar product, you can provide the appearance that you have disclosed information if the product ends up being very similar to what the NDA covered. The worst possible scenario was what I encountered where the NDA covered an unlimited range of information that was not identified. Then you have no idea of what you should not discuss or possibly work on. I believe at least one post in this long thread gave an example of a situation of an NDA preventing an engineer from working on a certain project in the new company. The new company chose to prevent the appearance of a violation of the NDA. Certainly you can see where this can be a limiting factor to your career. It may not cost you a job, or it won't get you fired, but it makes you less useful and flexible to your employer. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25209
Andy Peters wrote: > > rickman wrote: > > > > I am not board layout engineer, but one rule that should always work to > > give you good signals on a board trace is to use very short point to > > point traces. The round trip delay is about 1 nS per foot. With a edge > > time of .5 to 1 nS the round trip time needs to be less than this. So > > you get about 3 to 4 inches of trace as a maximum before you need to > > worry about terminations, etc. > > In the "Rule Of Thumb" department, I use the equation in > Johnson/Graham's _High Speed Digital Design_: > > l = Tr/D > > where > > l = length of rising edge in inches, > Tr = rise time, ps, and > D = delay, ps/in > > They also give delays for FR4. An trace in FR4 has a delay of about > 140-180 ps. > > I then ran the board through Hyperlynx BoardSim, and it told me what my > problems were! Phil pointed out a typo on my part. I did not mean to say that the round trip delay was 1 nS per foot of trace. I just meant that the speed was 1 nS per foot. Further he pointed out that the speed of signals on most PC boards is about half the speed of light or 2 nS per foot. So a round trip delay would be about 4 nS per foot. This gives about 2 inches before you need to worry about reflections. So keeping your traces shorter than 2 inches should prevent trace impedance problems. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25210
Andy Peters wrote: > > John Larkin wrote: > > > > Greg, > > > > supplementary rant: I just *hate* it when a PDF file, on CD or online, > > has a file name that has nothing to do with the part itself. On the > > Xilinx CD, all the file names are nonsense, and you have to go through > > an HTML page or something to find things. This is crazy! > > TI is notorious for that. That is because TI has always had numbers assigned to their documentation. They use this number for the file name. At least there is a reason to the scheme. SPRA is an app note, SPRU is a user manual, SPRS is a data sheet... I know this is not a lot, but it helps. They also use a letter at the end to indicate updated versions; SPRS087, SPRS087a, SPRS087b... Many companies leave it up to you to figure out if the data sheet has been updated. Xilinx used to make it hard, but now they seem to have a lettering version scheme. The Spartan II data sheets now seem to be ds001.pdf, ds001a.pdf, ds001b.pdf. Or did I put that on the names on my hard drive myself? I have considered starting a consulting business showing companies how to organize their web sites and data CDs so that users (engineers) can find the data they want easily and painlessly. I know that Xilinx is not the only company that doesn't do a great job of getting data to their customers. I have seen *MUCH* worse. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25211
Austin Franklin wrote: > I think calling someone names, and then expecting them to listed, doesn't > usually work well. Your issues certainly have merit, but would probably be > better received with a little more tact. I would agree with you if he had been writing to customer service or other engineers, but he was addressing the Xilinx CEO :-) -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25212
While, I kept a hold of the CD. I find that CD Databooks are worthless. Most of the time, If I need the part I goto the webpage and download it. I am forturnate to have a high bandwidth connection and hopeful that the Xilinx website is up. Another frustrating thing about CD's period, is that long delay when you hit windows explorer or searching for a file in a program. The delay comes from having to wait for the freaking CD-ROM player to spin up. Windows just sucks in this aspect (using NT 4.0 service pack whatever) Hell, it may be just the design of ultra cheap CD player that this high price corporate computer that I get has in it. But, it still sucks. -ralph Return Email Address is: ralphwat dot home at excite dot comArticle: 25213
Thanks for your comments (and I'm sure the thread will continue for a while) on the Xilinx DataSource CD. Based on the feedback, we will avoid having the CD automatically start anything, and we'll strive to make the viewing and installation options clearer. In the meantime, you can hit <esc> after inserting the current CD, or select Exit once the initial presentation ends. There are a couple alternatives to installing the viewer program. One is to open the databook.pdf file at the root of the CD, which contains the complete Data Book as a single Acrobat PDF file. It's a large file, but works well off the CD and allows you to quickly move between products. Another alternative is to open the root index.htm file, which will then link to all the files on the CD, with navigation similar to that on our web site. This page has links to both the single-PDF data book file, and links to individual PDF files for each product. Also note that the hard-copy Data Book is still available, and we have no plans to stop printing them. You can request a copy, which contains the DataSource CD, by using the form at http://www.xilinx.com/forms/literature.htm. Thanks again for your comments and for kicking off the thread, wherever it may take us. We may not be able to respond to every comment, but the input is appreciated! Victor the Cleaner wrote: > Rant or not, this is the right forum for it, and I can't believe > that this isn't a bigger issue across our industry. What scares > me to death is the possibility that otherwise-intelligent people > who agree with me are keeping quiet because they're afraid of > being seen as "resistant to new technology", regardless of how > misplaced or misapplied that technology might be. If you agree, > please circulate freely. > > jl > > (sent yesterday to databook@xilinx.com and Xilinx's CEO) > > I don't know which semi-literate, multimedia-infatuated moron is > responsible for the so-called "databook on CD" I'm forced to deal > with right now, but you people had better get over it and get back > to paper. > > ... > > I look forward to your reply. > > Jonathan Levine > Canada Connect Corp. > Calgary Marc Baker Xilinx Applications (408) 879-5375Article: 25214
rickman wrote: > Neil Nelson wrote: > > > Another point I'd like to make obvious is how restricting a set of signed NDAs could > > > be at subsequent interviews. > > > > > > Q: "Well, I signed this one there, and this other one elsewhere. Do these NDA > > > documents screw me here?" > > > A: "Well, sign this NDA and I'll send these over to our corporate attorney and we'll > > > figure something out." > > > > > > Matt > > > > I am not having an easy time imagining how an NDA signed for the purposes of an > > interview at one company would cause a difficulty interviewing or signing an NDA > > (for the purposes of the interview) at another company. Do you have a fairly > > concrete example of how such a difficulty would come about? Typically at an > > interview you talk about your own skills and substantial experiences that would > > relate to the potential job. What company specific information someone might give > > to you at one interview would seem far afield of the information you are expected to > > provide about yourself at another interview. > > > > Regards, > > > > Neil Nelson > > The concern is not that you could not interview with other companies. > The concern is that by promising not to disclose information to others, > you may be limited as to what you can work on for a new company. > Certainly it is best if you don't have any restrictions. But just by > working on a similar product, you can provide the appearance that you > have disclosed information if the product ends up being very similar to > what the NDA covered. > > The worst possible scenario was what I encountered where the NDA covered > an unlimited range of information that was not identified. Then you have > no idea of what you should not discuss or possibly work on. > > I believe at least one post in this long thread gave an example of a > situation of an NDA preventing an engineer from working on a certain > project in the new company. The new company chose to prevent the > appearance of a violation of the NDA. Certainly you can see where this > can be a limiting factor to your career. It may not cost you a job, or > it won't get you fired, but it makes you less useful and flexible to > your employer. Matt's meaning then was that a job seeker had worked for several different companies (not just interviewed), each with an NDA such that when interviewing for a new job the total area of concern for these previous NDAs had the appearance (possibly substance) of covering areas of the new job. The one post you may be talking about in the last paragraph sounds like Jon's post where the result went against the NDA company's claim. I.e., the company thought the NDA applied, but it did not. In Jon's case the NDA was not the direct problem but rather it was the NDA company's interpretation of claims an NDA gave them that was the problem. Though this is an NDA related problem, it appears to be secondary, and not one we are directly concerned with. However, if it is a general concern, we perhaps need to note that it is a somewhat related but separate concern requiring a correspondingly different discussion or treatment. But the cumulative effect of NDAs as they reduce employment potential has at least the appearance of being a concern. Generally one is more employable with increasing experience as that experience is of the kind useful to a potential employer. E.g., if I had worked for Intel on new chip technology, I should be worth a fair amount to Advanced Micro Devices (AMD) who would have a similar interest. It would not be proper for Intel to restrict my employment potential by essentially removing the advantages of my experience, but Intel would want to restrict technical advantages it has that are relatively secret, that they have spent considerable resources on finding and developing from being handed to AMD on a silver platter. It would seem proper to notify the new company of existing NDA agreements a job seeker has, and hopefully has a copy of, if they think it is important. But I doubt any NDA requires you to notify the NDA company of who you may choose to work for, what the new company's business is, and certainly the new company has no agreement to tell any previous employer which of their prior employees they have hired. Balancing the interests between the NDA company and the prior employee (now a job seeker) could become difficult, but it seems to me that the job seeker is initially ahead in the potential of getting a good job as the NDA company would not normally know what the job seeker is doing, a prior NDA is not in the interests of a new company and rather points to a class of skills that should be of interest to them. A generally worded NDA tends toward being ineffective in that the NDA company would need to show, if they were to make a subsequent claim against a prior employee, that the prior employee transferred company specific information that was damaging to the NDA company. E.g., Intel could not require an NDA against chip technology in general and then enforce it because there are a large number of organizations involved in chip technology and much of chip technology is public domain. Such an NDA would need to be construed to covering specific Intel chip technology that if transferred would damage Intel, which requires Intel, if they were to make a claim, that specific chip technology was transferred by a specific individual, and that such a transfer was damaging to Intel. This will not be an easy case to make. It would be easier for an NDA company to make it worthwhile for employees to stay than attempting such a legal quagmire. But finally, I think we need a better concrete example that illustrates the suggested problem. Jon's example rather argues how _ineffective_ an NDA can be. Regards, Neil NelsonArticle: 25215
John Larkin wrote: > > Well, I want to do a really cool image-processing gadget, and I'll > need an FPGA with 300 I/O pins or so. Peter Alfke was kind enough to > send me a couple of sample Xilinx BGA parts. I showed them to my > manufacturing people and actually escaped with my life. > Myself I would redesign the project to use 6 chips of 50 pins each. Then they would fit in nice cheap 84 pin PLCC sockets with nice cheap FPGA's. The best bet would be to make a small daughter pcb with the FPGA and ROM?. The smaller board would permit easier inspection and manufacturing because of the smaller size. The PCB also would permit brain transplants when it was time to upgrade the product. Good Luck with what you have. Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "New 24 bit CPU" http://www.jetnet.ab.ca/users/bfranchuk/index.htmlArticle: 25216
Marc Matthey wrote:
> Hello Tomek,
>
> I use MaxPlus II to simulate after synthesis a project but it works only
> for Altera FPGA. I save design in an EDIF file for reload it in MaxPlus
> II. But you can use ModelSim for others projects. So, after synthesis if
> you can simulate verilog or vhdl files.
> If you want to have the timing, you can save an SDF file that contains
> timing informations. When you load your verilog or VHDL file in ModelSim
> you can choose to link the design with a SDF file.
>
> Marc
Its a little bit more complicated than that if you are using a ``grown-up''
simulator such as ModelSim.
(1) Make sure your synthesis tool is setup to output a post-synthesis
simulation
Verilog or VHDL file.
(2) Find out what the file is called, where it is and then compile it.
(3) Some synth tools include models for the primitive elements in the
post-synth netlist [Synplify] and others rely on vendor libs [FPGA Express
?]. If its the latter you will have
to compile the libs as well.
(4) Not all synthesis tools generate SDF timing estimates. If yours doesn't
& you want to do
timing simulation then you will have to place&route the design and then
generate a post-route Verilog/VHDL netlist + SDF file. You might also have
to compile & use a different primitive library.
Note: For FPGAs post-route simulation is really most useful for finding bugs
in the Vendors tools. Post-synthesis simulation, good timing constraints
during place & route, and a thorough static timing analysis are usually good
enough.
(5) Then find all the bugs the Vendors have carefully placed in their libs &
post-route netlist generators.
Good luck
Article: 25217This is a multi-part message in MIME format. --------------CADCB5E28F4FAF03F23A92B8 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Certainly Data books (On paper ) do wonders. U can use Highlighters on them ! :) Cheers Anup rickman wrote: > Just to stick my two cents worth in... > > I do like data books. I also like PDF files. I do not like any of the > data book CDs I have gotten from any companies. A few come close by > duplicating their web pages, but the mixing of HTML and PDF is not > really the right answer either. > > So my vote is for the support of both paper on new products which I read > like a text book, and PDF files on old products which I refer to as > reference material. Certainly there is nothing wrong with distributing > PDF files by CD. But there is little right with the way it is done. > Leave off the install software and the "viewers". > > Victor the Cleaner wrote: > > > > Rant or not, this is the right forum for it, and I can't believe > > that this isn't a bigger issue across our industry. What scares > > me to death is the possibility that otherwise-intelligent people > > who agree with me are keeping quiet because they're afraid of > > being seen as "resistant to new technology", regardless of how > > misplaced or misapplied that technology might be. If you agree, > > please circulate freely. > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com --------------CADCB5E28F4FAF03F23A92B8 Content-Type: text/x-vcard; charset=us-ascii; name="anup.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for anup Content-Disposition: attachment; filename="anup.vcf" begin:vcard n:Anup Kumar;Raghavan tel;home:+61-7-38761962 tel;work:+61-7-33658849 x-mozilla-html:TRUE url:www.elec.uq.edu.au/~anup org:University of Queensland;Computer Science & Electrical Engineering version:2.1 email;internet:anup@elec.uq.edu.au adr;quoted-printable:;;47/401, Dept. of CSEE, UQ, =0D=0A=0D=0A;St.Lucia, Brisbane ;Queensland;4072;Australia fn:Anup end:vcard --------------CADCB5E28F4FAF03F23A92B8--Article: 25218
Philip Freidin wrote: > >By touching (with my hand) the input trace & pins I am able to get a clean > >input. But I can not be shipped with the product. > > Well, you could be shipped with one instance, but that would restrict your > production run somewhat. Depending on if only a finger is needed, the production run could range from 2 to 10. Another solution is to hire contractors. :-) rkArticle: 25219
Hi, I read some directives such as _SUPERBEL, _PINMAP in the CFG section of instance configurations in the xdl. What do they mean? Is there a document with a list of these directives available? Are they only markers inserted by synthesis tools? What do I do with them if I'm going to modify the xdl file? can I just take them away? Also, is there a document explaining how the routing wires in Virtex are named in the xdl file? like the terms OUT_E7, S0_G_B3... it would be nice to know this. Thanks. Any help is very much appreciated. William /* -------- William Chow : "WHO SAYS YOU CAN'T DO IT?!" -------- */ Email = choww@eecg.utoronto.ca || choww@ugsparc0.eecg.utoronto.caArticle: 25220
6.4 Gbits per second? Each way? I can name that tune with 32 wires! Total. 16 wires, each direction. each direction has 8 differential pairs, each running 850 Mbits with pseudo-Sonet data format (includes scrambling). In an FPSC device, the Lucent ORT8850. It also features a sync fifo to remove routing skew, AND clock and data recovery macros on each pair. AND on chip termination resistors (100 Ohms). High quality twinax cable will run without buffering for about 50 feet. PCB differential traces will work as far as you can make 'em. Completely plug and play, it only needs a clock input of 106.25 MHz which is multiplied up on chip to 850 Mhz. it also has about 400K gates of programmable logic. The internal FPGA interface sees only a parallel 64 bit bus clocked at 106.25 Mhz, and the data formating, serialization, scrambling, framing and de-skewing is all handled by an asic core lashed onto the FPGA block. It also supports 8b/10b coding, but you then have to accept the 25% bandwidth penalty that goes with it. I like it.. John McCluskey Lucent Microelectronics Steven DeLong wrote: > I have an application that requires the connection of a large amount of > I/O between multiple FPGAs on a single PCB. The application requires one > type of device to fan in/out to 8 each of a second type of device. Each > connection requires about 6.4 Gbit of bandwidth in each direction. > > One connection scheme could use two 32 bit buses (one bus in each > direction) between each of the eight devices and the one device. The bus > bits would each run at 200 Mb/s. That's 64 single ended > drivers/receivers on each of the eight devices and 512 single ended > drivers/receivers on the other device. > > Does anyone have any experience with anything similar to the above > and/or large amounts of high-speed interconnect between chips? What type > of I/O was used (LVTTL, LVDS, HSTTL, etc.) What, if any type of > terminations were used? Any other suggestions? > > I would like to avoid external terminations and reduce as much as > possible the number of physical routes between the devices because of > PCB real estate limitations.Article: 25221
I have a Verilog design I inherited that was developed in Xilinx Foundation (takes about 1300 FFs, 1400 LUTs in virtex) and I notice that Foundation synthesizes this (supposedly with Synopsys FPGA Express under the hood) in about 2 minutes, but Synopsys FPGA Compiler II (on a Unix Sun Ultra Sparc w/ 1 Gbyte of RAM) crashes when I synthesize the whole design top-down ..... and synthesizes in 45 minutes (with errors) if I do bottom-up synthesis. I thought FCII was supposed to be the state-of-the-art synthesis tool, with more features than FE and the same 'engine' as FE. Any ideas why FCII would be performing so poorly compared to FE? Are there special switches or settings that need to be turned on? -- ============================== William Lenihan lenihan3weNOSPAM@earthlink.net ==============================Article: 25222
Latch can be synthesis, but, generaly you must not because they disable all possibility for futur testability as JTAG... so compilers don't like it. In FPGA architecture you can simuate latch with memory element like ram by instanciating RAM element... show apply note that you can find on xilinx web-site. But generaly, if you have latch, you may have some troubles in your design. Paul Tomasz Brychcy <T.Brychcy@pz.zgora.pl> a écrit dans le message : 8oj093$bfm$1@okapi.ict.pwr.wroc.pl... > Hello, > > Why after writing a synthesizable project we have to write in this way that > latches was the least in the project. Latches are not synhesis efficient, if > yes will tell me why? > > Tomek > > > -- > Department of Electrical Metrology > Technical University of Zielona Gora > > T.Brychcy@sensor.ime.pz.zgora.pl > > >Article: 25223
Tim Hove wrote: > > Hi All > I'm a software developer with a little hardware problem. An An embedded > computer we had ordered from a private konsultant is newer gonna show. > Therefore I'm looking for a replacement with specification that won't force > us to change the current design dramaticly. For this purpose I need an > embedded PC using a FPGA as I/O expansion. Does anyone know if such a > product exists?? Tim, What way are you driving the interface, through an ISA or PCI bus? If you're using the PCI bus it's not trivial, there are tight timing constraints to meet and your layout is critical. The easiest way of implementing this is to get hold of a core with FPGA layout and pin allocation and board placement and routing info. If you get hold of such a core and follow the constraints given the design should work OK. These cores are available from a number of sources, I'd start with the FPGA vendor (Xilinx/Altera or whoever). It's then a matter of interfacing with the PCI core in your FPGA to implement the SPI bus, but this shouldn't be too difficult, it's a fairly simple bus. I'm sure that most devices big enough to implement the PCI interface would have enough space to add the SPI bus. A much simpler way of doing it would be to design an ISA interface. This is a very simple bus, I can't remember the details, but a web search should come up trumps. Implementing the SPI bus off the ISA bus isn't to hard a problem for someone with experience designing FPGAs. Having said that, if you're just starting to look at FPGA's it's not trivial. > Further; how big a FPGA would I have to get to run a SPI Bus??. > In case you can't tell, I don't know much about FPGA's. > Any help is very welcome. If you're _really_ stuck it would probably be best to outsource this design. Someone who's competant should be able to provide a prototype in a few weeks. Nial.Article: 25224
Hi,
I have a problem concerning the usage of Foundation 2.1i, SYNOPSIS,
Virtex300 and Block RAM. The RAM is initialized with attribute INIT_00
...
The initialization with attributes (INIT_00, ..) works fine after
Implementation (timing simulation). But after Synthesis (without
Implementation) the Ram isn't initialized
and the simulator doesn't show any changes (all mem locations at 0). It
seems like synthesis ignores the attributes.
A second problem:
How can I force SYNOPSIS to use Virtex's block ram. The code fragment
for SYNPLICITY looks like this:
architecture block_ram of block_ram is
type mem_t is array (0 to 31) of std_logic_vector(199 downto 0);
signal bk_ram : mem_t;
attribute syn_ramstyle of bk_ram : signal is "block_ram"; -- key to
force usage of block ram in virtex devices. (synplify tool)
:
begin
:
bk_ram(conv_integer(ADDR_i)) <= D_i;
:
How can above code be adapted to SYNOPSIS?
THANKS Gerhard
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