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On Feb 1, 1:55=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > gm <g...@nomail.com> wrote: > > I haven't touched FPGAs or VHDL since the university years so I was > > thinking to get a starter board in order to get back to the path. I did > > find some cheap boards out there but I am not sure if I could burn > > something like a 32-bit RISC soft core on that. > (snip) > > Also good features would be VGA,PS/2,ethernet. Thanks > > I recently got a Digilent Spartan3E board, which was the > XC3S500E. =A0There are many boards with VGA, serial, and PS/2 > keyboard, but not so many with ethernet. > You can upgrade to the xc3s1200e for only $20. I only wish they had used spartan 3a's so you could upgrade to the 3800 dsp. Those chips are actually cheaper than the 3e1200Article: 137876
On Jan 27, 12:50=A0am, secure...@gmail.com wrote:
> Hi,
>
> I have to make a PCB using BGA pinout for FPGA.
>
> What brand of software do you use ?
>
> Place Route manually or automatically ?
>
> Which plans to use and how ?
>
> For the width of the tracks ?
>
> Thanks.
>
> Kappa
Kappa,
Without high tech boards, this is a real pain. To use 1.0mm pitch
bga's, you can't really go courser than 6mil trace/space. Catch is
that you need to use 12 mil vias with 24 mil pads and 36 mil annular
rings or you won't be able to fit the vias in between the balls. Most
houses won't let you do this on there discounted runs. I've gotten pcb-
pool to do it, but i think there patience is running thin, they
usually have to run my board 3 times to get one that passes e-testing.
Next problem is, that while power is easy. You can really only escape
the outer 5 balls using 4 routing layers(6 total, including power).
This means that to get more i/o, your chip size increases linearly
instead of the square root like it should for bga's. If you need more
than 256 or so i/o's. You need more layers or micro vias. Both of
which are very expensive.
Good luck,
Jon pry
Article: 137877jonpry@gmail.com wrote: (snip, I wrote) >> I recently got a Digilent Spartan3E board, which was the >> XC3S500E. ?There are many boards with VGA, serial, and PS/2 >> keyboard, but not so many with ethernet. > You can upgrade to the xc3s1200e for only $20. I only wish they had > used spartan 3a's so you could upgrade to the 3800 dsp. Those chips > are actually cheaper than the 3e1200 It looks like the NEXYS2 has the 500 and 1200 option, with the latter $40 more. I don't see that option for the Spartan3E, though maybe it was discontinued. There is some hint on the Xilinx web pages of a 1600E option for the Spartan3E board, but I don't see where to buy that one. If you have the equipment, you could remove the 500E and install a 1200E or 1600E (I believe they come in the right package). -- glenArticle: 137878
"Hal Murray" <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote in message news:8b6dnTriW4qjWRjUnZ2dnUVZ_qLinZ2d@megapath.net... >>Could you create a high watermark signal in the FIFO when there is >>room for around 4 more words in the FIFO? If so you will have plenty >>of time to propagate a pipelined "clock enable" signal to your >>datapath with a moderate amount of fan-out for every level of >>pipelining in your CE signal. > Most FIFOs have an almost-full signal. It's needed for things > like this. That's the practice I've been using (granted, my processing pipeline is more like 10 deep instead of 50). Depending on the size of your FIFO, this may be the easiest way to go. If your FIFO is already something like 128 or more deep, then setting the almost full flag down to 70 or so is easy. This is the signal you tie to your "block" signal to freeze processing. You do need then a (registered) "data valid" to propagate down with your data to keep everybody sane, but you probably have that already. Your only concern is that when almost full finally clears it will take you at least 50 clocks to get data flowing again. My last FIFO fed a hard DAC, so running it dry was a concern. My latest system uses a large SDRAM swing buffer as a FIFO; the latency I need to worry about is in the controlling computer's interrupt handler. Good luck, MartyArticle: 137879
I'm using CORE generated block ram (ROM, actually) with the width of 12 bits and ISE 10.1 creates a 16bit wide bus and gives me a warning for upper 4 bits (which I don't need): WARNING PhysDesignRules:1109 - Blockcheck:Dangling BLOCKRAM_BLOCKRAMA output. Pin OUT12-15 of comp ROM/B6.A is not connected. How can I remove the warnings? I think I can safely ignore them, but I don't like warnings.. TIAArticle: 137880
On Sun, 01 Feb 2009 11:25:50 -0800, Mike Treseler wrote: >What if you just clock disabled the last stage? Wouldn't that mean that the next-to-last stage would overrun and its output data would be lost? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 137881
On Feb 1, 4:46=A0pm, aleksa <aleks...@gmail.com> wrote: > I'm using CORE generated block ram (ROM, actually) > with the width of 12 bits and ISE 10.1 creates > a 16bit wide bus and gives me a warning > for upper 4 bits (which I don't need): > > WARNING PhysDesignRules:1109 - Blockcheck:Dangling > BLOCKRAM_BLOCKRAMA output. Pin OUT12-15 of comp > ROM/B6.A is not connected. > > How can I remove the warnings? > > I think I can safely ignore them, > but I don't like warnings.. The obvious way it to connect it to something that won't matter, like or them together and connect to a pin. I realize that the hardware only supports powers of two (actually plus a bit for each byte). Does the core generator support arbitrary widths just so you get what you need and *don't* have warnings? When I programmed in C, I would get warnings when I was doing something that might be a mistake and I could always code it "properly" to get rid of the warnings. It seems like synthesis doesn't give you that much flexibility. There are things that get coded correctly and are what I need, but throw warnings that I have to read and verify are not important. RickArticle: 137882
jonpry@gmail.com wrote: > You can upgrade to the xc3s1200e for only $20. I only wish they had > used spartan 3a's so you could upgrade to the 3800 dsp. Those chips > are actually cheaper than the 3e1200 It seems that there was a Spartan3E board with the 3E1600 but it is now discontinued. https://www.digilentinc.com/Products/Detail.cfm?NavTop=2&NavSub=431&Prod=S3E1600 It looks amazingly similar to the 3E500 board, so I wonder why it is discontinued. -- glenArticle: 137883
On 2009-02-01, FredrikH <fredrik.holmsten@gmail.com> wrote: > Hi, > > I recently started to look for an mp3 encoding and decoding IP, but to > my surprise I cannot find anything suitable or anything at all for > that matter. > > By various reasons I?m kind of stuck to the Xilinx range of FPGAs so I > naturally started out by having a look at their cores and 3rd party > cores listed at their webpage, but there are only full blown MPEG-2 > and MPEG-4 cores and I only want an MPEG-1 Layer 3 core. > > I also had a look at opencores.org, but that search was also > fruitless. So, is it really that bad? Is there nothing to buy or at > least start from? Do you have a processor like MicroBlaze running in your FPGA already? If so, could you use a software MP3 decoder/encoder? If you were using Nios II in Altera I would point to the Spirit DSP homepage which has an MP3 decoder capable of operating at only 22 MHz in a Nios II IIRC. (Possibly with some sort of custom instructions.) Perhaps they have a solution for MicroBlaze as well if you call them? (Don't forget the licensing fees for MP3 if you are doing this for a commercial product. Perhaps Vorbis is a better solution from that point of view?) Anyway, if the software solution is not a good idea you may be interested in some information about an MP3 decoding core I developed together with a friend: It uses 2370 LUTs, 1048 flip-flops, 1 DSP48 block and 22 RAMB16. The maximum clock frequency is 201 MHz in a Virtex-4 (speedgrade 12), but 19.6 MHz is enough to decode MP3 files. It is still a processor though, but one which is somewhat optimized for MP3 decoding. I would guess that an MP3 decoding core will not be much smaller than this. If you use some sort of caching scheme for your data you may be able to reduce the number of block-rams though. My final advice: If necessary, use a soft-core processor for this. If you already have one in your project, great. If not, add one. I guess that you will not be able to save much area by using a dedicated MP3 decoding core compared to using a soft processor core. (Although the equation changes if you are aiming for low power consumption, especially in an ASIC.) /AndreasArticle: 137884
On Feb 2, 1:21=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > jon...@gmail.com wrote: > > You can upgrade to the xc3s1200e for only $20. I only wish they had > > used spartan 3a's so you could upgrade to the 3800 dsp. Those chips > > are actually cheaper than the 3e1200 > > It seems that there was a Spartan3E board with the 3E1600 > but it is now discontinued. > > https://www.digilentinc.com/Products/Detail.cfm?NavTop=3D2&NavSub=3D431&P= ... > > It looks amazingly similar to the 3E500 board, so I wonder > why it is discontinued. > > -- glen it was too good for the price, so they discontinued it! if it sells to good, then you have to re-stock too often and who wants that? solution is simple: stop selling the problematic item! AnttiArticle: 137885
Jonathan Bromley wrote: > On Sun, 01 Feb 2009 11:25:50 -0800, Mike Treseler wrote: > >> What if you just clock disabled the last stage? > > Wouldn't that mean that the next-to-last stage > would overrun and its output data would be lost? Yes, but maybe the data source is continuous and we are dropping packets in any case. -- Mike TreselerArticle: 137886
Hey guys, I've just put an image processing design onto my Nexys 2 (S3E500) and have started using ChipScope for the first time to suss it all out. To my suprise, my FVAL and LVAL signals seem to be all over the shop. In the picture, ports 5 and 6 are just random pixels, as they are behaving as expected: toggling around for 320 clocks, asserted low for 80. This matches the supposed LVAL timing on the camera data sheet. Unfortunately, port 1 is LVAL, and as you can see it maintains some sense of order, but is certainly not clean. It is up/toggling for the 320 clocks, then generally low for the 80. FVAL, at the top, should be high for all of this, but like LVAL toggles around. Initially I expected that the lines are absorbing some noise, since I have it hooked up with a custom crimp header adapter (since the Nexys doesn't have an MDR26 of course). The confusing part then, is that LVAL toggles religiously when FVAL is de-asserted. The camera is a JAI Pulnix TM 6740 CL http://farm4.static.flickr.com/3461/3246699944_d48f6270e6.jpg?v=0 http://farm4.static.flickr.com/3297/3245872695_ea8267b993.jpg?v=0 Grabs aren't great but hopefully they shed some light. Any ideas on what could be the problems?Article: 137887
1 more things I should have added: I have used XAPP485 to do the deserializing of the stream.Article: 137888
Hi, just some questions: Is the analog video output working correctly? Is the camera configured properly? Do you have noise on the external sync input? In the first picture FVAL is going low four times with three different durations. Is that a sampling problem, or is there a meaning behind it? The toggling of the LVAL signal during FVAL-low phases looks strange, but may be part of the cameras design. You should ask pulnix for detailed specs of their FVAL/LVAL/DVAL structure. The second picture looks good as far as FVAL stays high, while LVAL is going low. Of course there's lot's of noise in the signal. Is your power supply working correctly and stable enough for this camera? Is your camera Link cable properly terminated? Are there other noise sources? e.g. Ground loops, bad (noisy) FPGA power supply, insufficent power capacitors, noisy working area? Regards Eilert reganireland@gmail.com schrieb: > Hey guys, > > I've just put an image processing design onto my Nexys 2 (S3E500) and > have started using ChipScope for the first time to suss it all out. To > my suprise, my FVAL and LVAL signals seem to be all over the shop. > > In the picture, ports 5 and 6 are just random pixels, as they are > behaving as expected: toggling around for 320 clocks, asserted low for > 80. This matches the supposed LVAL timing on the camera data sheet. > Unfortunately, port 1 is LVAL, and as you can see it maintains some > sense of order, but is certainly not clean. It is up/toggling for the > 320 clocks, then generally low for the 80. > > FVAL, at the top, should be high for all of this, but like LVAL > toggles around. Initially I expected that the lines are absorbing some > noise, since I have it hooked up with a custom crimp header adapter > (since the Nexys doesn't have an MDR26 of course). The confusing part > then, is that LVAL toggles religiously when FVAL is de-asserted. > > The camera is a JAI Pulnix TM 6740 CL > > http://farm4.static.flickr.com/3461/3246699944_d48f6270e6.jpg?v=0 > http://farm4.static.flickr.com/3297/3245872695_ea8267b993.jpg?v=0 > > Grabs aren't great but hopefully they shed some light. > > Any ideas on what could be the problems?Article: 137889
On 1 =AAubat, 13:46, aleksa <aleks...@gmail.com> wrote: > I'm using CORE generated block ram (ROM, actually) > with the width of 12 bits and ISE 10.1 creates > a 16bit wide bus and gives me a warning > for upper 4 bits (which I don't need): > > WARNING PhysDesignRules:1109 - Blockcheck:Dangling > BLOCKRAM_BLOCKRAMA output. Pin OUT12-15 of comp > ROM/B6.A is not connected. > > How can I remove the warnings? > > I think I can safely ignore them, > but I don't like warnings.. > > TIA Core generator is only a GUI helping you to do the jobs easily. For the ROM you generate Core Generator uses the built-in block rams of width 16. If you want a width of 12 the remaining 4 bits will be unconnected as expected. I agree that checking all of the warnings are annoying but sometimes these warnings are life saving. Like in this case it warns you that 4 pins are unconnected. Imagine that you forgot to connect a clock enable pin, this "unconnected things" warning, you will see that, will save your life. But the answer of your question is I don't know if there is a way to disable these warnings :) --enesArticle: 137890
Hi Ehsan, you don't have to worry much about the fan out. The synthesis tool takes care of it. If you give a timing constraint the synthesis tool works out how to duplicate the CE driving circuits to meet that requirement. That might cost some LUTs but that should be neglectable in a 30x50 Pipeline design. If you want to be sure about this, read the infos in the synthesis report or check the results in the fpga-editor. Have a nice synthesis Eilert Ehsan schrieb: > Hi, > > I'm trying to implement a design on the Xilinx FPGA which is heavily > pipelined, let say 50 stages, and each stage has a data width of > aorund 30 bits. Now, I want to halt the pipeline or "freeze" it at > some instances. One way would be to tie up all the clock enable > signals of those registers and then control the pipleline using this > clock_enable signal. However, I'm affraid about that control signal's > fan-out (probably something around 1500). > > Do you think it's a good design practice? Any suggestions or similar > experience? > > BTW, Will using the clock-enable signal of FFs affect the amount of > consumed resources? Or they are simply built-in features that we can > choose either to use or not to use? >Article: 137891
I have wrote the following code in verilog (using the reading_dna.vhd
file on the xilinx site) to run the picoblaze code that I found
online. I synthesized the code, produced, and send a .bit using ISE
10.1 to the Spartan 3an, however, the LCD screen doesn't display
anything. Can someone run this and check if there is something
wrong ?
module lcdtest(lcd_d,
lcd_rs,
lcd_rw,
lcd_e,
j2_30,
j2_26,
j2_22,
j2_14,
clk);
input clk; // 50MHz clock
output reg [7:0] lcd_d ; // lcd output
output reg lcd_rs;
output reg lcd_rw;
output reg lcd_e;
output j2_30;
output j2_26;
output j2_22;
output j2_14;
wire [9:0] address; // wires to connect uC address lines
to ROM
wire [17:0] instruction; // wires to connect uC data lines,
to ROM
wire [7:0] out_port; // wires to connect uC output port
to the LED flipflops
wire [7:0] port_id;
wire write_strobe;
wire read_strobe;
wire interrupt;
wire interrupt_ack;
wire reset = 0;
wire lcd_rw_control;
wire [7:0] lcd_output_data;
//instantiate the picoblaze mC
kcpsm3 mcu( address, instruction, port_id, write_strobe, out_port,
read_strobe, in_port, interrupt, interrupt_ack, reset, clk );
//instantiate the program rom
lcd rom(address, instruction, clk );
always @ (posedge clk)
begin
/
*----------------------------------------------------------------------------------------------------------------------------------
-- LCD interface
----------------------------------------------------------------------------------------------------------------------------------
--
-- The LCD will be accessed using the 8-bit mode.
-- lcd_rw is '1' for read and '0' for write */
// 8-bit LCD data output address 40 hex.
if (port_id[6])
begin
if(lcd_rw)
lcd_d <= out_port;
else
lcd_d <= 8'bz; // -- use read/write control to enable output
buffers.
end
//-- LCD controls at address 20 hex.
if (port_id[5])
begin
lcd_rs <= out_port[2];
lcd_rw <= out_port[1]; //Control of read and write signal
lcd_e <= out_port[0];
end
end
endmodule
///////////////////////////////////////////////////////////////////////////////////////////
The .psm file that I complied can be found online, but I will include
it here:
http://forums.xilinx.com/xlnx/board/message?board.id=PicoBlaze&thread.id=147
;========================================================================
CONSTANT BIN2BCD_SCRATCHPAD, 24 ; change this to your preferred
location
CONSTANT MY_OUTPUT_PORT, 00 ; just for the usage example
ADDRESS 000
usage_example:
LOAD s0, D2
STORE s0, 24 ; this address is BIN2BCD_SCRATCHPAD+0. If only
there were expressions...
LOAD s0, 02
STORE s0, 25 ; this address is BIN2BCD_SCRATCHPAD+1. If only
there were expressions...
LOAD s0, 96
STORE s0, 26 ; this address is BIN2BCD_SCRATCHPAD+2. If only
there were expressions...
LOAD s0, 49
STORE s0, 27 ; this address is BIN2BCD_SCRATCHPAD+3. If only
there were expressions...
LOAD s0, 04 ; byte count of binary number
CALL bin2bcd
LOAD s1, 05 ; BCD byte count for 32-bit (incl. leading zeros)
loop_output:
SUB s2, 01 ; pre-decrement pointer
FETCH s0, (s2)
SR0 s0
SR0 s0
SR0 s0
SR0 s0
ADD s0, 30 ; add ASCII '0'
OUTPUT s0, MY_OUTPUT_PORT
FETCH s0, (s2)
AND s0, 0F
ADD s0, 30 ; add ASCII '0'
OUTPUT s0, MY_OUTPUT_PORT
SUB s1, 01
JUMP NZ, loop_output
stall:
JUMP stall
;----------------------------------------------------------
; bin2bcd
; By Udi Barzilai 2008
; You are free to use / modify / distribute this code
; PROVIDED AS IS WITHOUT ANY WARRANTY
; USE AT YOUR OWN RISK (if any)
;
; Arguments:
; s0: N = byte count to convert
; SCRATCHPAD(0 TO N-1) should contain binary bytes to convert, LSB at
lowest address
; SCRATCHPAD(N TO N+K-1) will contain BCD converted data, K=ceil
(N*5/4)
; Return:
; s2 and s3 point just after the last byte of BCD
;
bin2bcd:
LOAD s4, s0 ; N
LOAD s1, s0 ; N
SL0 s1 ; N*2
SL0 s1 ; N*4
SL0 s1 ; N*8
LOAD s5, s1 ; save N*8
ADD s1, s0 ; N*9
ADD s1, 03
SR0 s1
SR0 s1 ; ceil(N*9/4)
LOAD s3, BIN2BCD_SCRATCHPAD
ADD s3, s1
; point s2 at start of BCD and clear the bytes there
LOAD s2, BIN2BCD_SCRATCHPAD
ADD s2, s4
LOAD s0, 00
loop_clear_bcd:
STORE s0, (s2)
ADD s2, 01
COMPARE s2, s3
JUMP NZ, loop_clear_bcd
loop_shiftadjust:
; shift everything one bit to the left
LOAD s2, BIN2BCD_SCRATCHPAD
LOAD s1, 00
loop_shiftonce:
FETCH s0, (s2)
SR0 s1 ; fetch stored carry
SLA s0
SLA s1 ; store new carry
STORE s0, (s2)
ADD s2, 01
COMPARE s2, s3
JUMP NZ, loop_shiftonce
; test if we've shifted out all BIN bits
SUB s5, 01
RETURN Z ; done if N bits shifted
; adjust the BCD for the next shift
LOAD s2, BIN2BCD_SCRATCHPAD
ADD s2, s4
loop_adjust:
FETCH s0, (s2)
LOAD s1, s0
ADD s1, 03
TEST s1, 08
JUMP Z, dont_keep3
LOAD s0, s1 ; keep added 3
dont_keep3:
LOAD s1, s0
ADD s1, 30
TEST s1, 80
JUMP Z, dont_keep30
LOAD s0, s1 ; keep added 30
dont_keep30:
STORE s0, (s2)
ADD s2, 01
COMPARE s2, s3
JUMP NZ, loop_adjust
JUMP loop_shiftadjust
;========================================================================
///////////////////////////////////////////////
Article: 137892Hi, My design has modules like i2c controller, cpu, sram, gpio. I integrated all the above modules. This design is implemented in Spartan 3e based Digilent Basys board. The design when triggered, reads data from the externally connected I2C EEPROM, copies into SRAM in the design and then triggers the cpu to process the data and output the result on to the leds on board. When I configure the FPGA with the bit file(write the bit file into ROM on board/FPGA), the design works fine for the first time but when I push the FPGA reset button to reconfigure the FPGA, the design does not work. When I power the whole board off, wait for some time and then repeat the process, it works fine only for the first time. I tested the board with a simple counter and it is working fine. Does my design need a different treatment because it uses an externally connected I2C EEPROM? Please help. Thanks.Article: 137893
On Feb 1, 9:47=A0pm, John Adair <g...@enterpoint.co.uk> wrote: > Antti > > I don't think any boards supporting the next families will be > available generally for a some time but tomorrow might tell us > different. I expect we will be one the first to have such a product > but that's not giving anything away. > > Meanwhile it's worth pointing out to Euro and Dollar countries our > products are now much cheaper due to our currency and $400 goes a long > way. I would think we stand a chance of possibly doing something under > US$400 that might do an OpenSparc. It's more a question of whether the > full ISE is needed or Webpack can be used. Do you have a size for > OpenSparc? > > John Adair > Enterpoint Ltd. > Hi John, didnt you get the webex invitation? I know some Xilinx Alliance Partner members did not get it. But newertheless as Xilinx Alliance Partner member you should have more trust in Xilinx, that they do the things right. Xilinx has delayed the PR for the s6 for a looong time, and for one good reason: they still rememeber the mockup they had with previous new tecnology introduction. So unless its going to be another major disaster i would say Xilinx has maximum 3 to 4 months to actually deliver S-6 ES silicon AND basic Development boards as well. This is what i would say is time that the OP should wait before making a decision. If the S-6 does delays much more than that, i would almost second my wife who said after Electronica 2008 (based on my biased comments) Xilinx will be dead in a few years (actually she said nobody will care to remember them) it want be that, for sure.. but there is a limit of how many mistakes even a big company can do so i live in the hope that S-6 will be available shortly and not in 2012 AnttiArticle: 137894
Antti Indeed I did dial into a Webex last week and have had several briefings over the last year from all the major vendors but that isn't for this forum. We were very overdue for all of the new families especially the Spartan-6. I think they were probably delayed to conincide with the 25 years celebrations coming up next week. If you count all the Spartan-3 offerings as the same family it's been probably the longest running leading families they have ever had which is a testiment to how right they got the family. Looking forward to the roadmap that's coming I think FPGAs will move in new significant areas with these families and hopefully the rollout will be better than the Spartan-3 mess. John Adair Enterpoint Ltd. On 2 Feb, 09:18, Antti <Antti.Luk...@googlemail.com> wrote: > On Feb 1, 9:47=A0pm, John Adair <g...@enterpoint.co.uk> wrote: > > > > > > > Antti > > > I don't think any boards supporting the next families will be > > available generally for a some time but tomorrow might tell us > > different. I expect we will be one the first to have such a product > > but that's not giving anything away. > > > Meanwhile it's worth pointing out to Euro and Dollar countries our > > products are now much cheaper due to our currency and $400 goes a long > > way. I would think we stand a chance of possibly doing something under > > US$400 that might do an OpenSparc. It's more a question of whether the > > full ISE is needed or Webpack can be used. Do you have a size for > > OpenSparc? > > > John Adair > > Enterpoint Ltd. > > Hi John, > > didnt you get the webex invitation? I know some Xilinx Alliance > Partner members did not get it. > But newertheless as Xilinx Alliance Partner member you should have > more trust in Xilinx, that > they do the things right. Xilinx has delayed the PR for the s6 for a > looong time, and for one > good reason: they still rememeber the mockup they had with previous > new tecnology > introduction. So unless its going to be another major disaster i would > say Xilinx > has maximum 3 to 4 months to actually deliver S-6 ES silicon AND basic > Development > boards as well. This is what i would say is time that the OP should > wait before > making a decision. > > If the S-6 does delays much more than that, i would almost second my > wife who > said after Electronica 2008 (based on my biased comments) > Xilinx will be dead in a few years (actually she said nobody will care > to remember them) > it want be that, for sure.. > but there is a limit of how many mistakes even a big company can do > > so i live in the hope that S-6 will be available shortly and not in > 2012 > > Antti- Hide quoted text - > > - Show quoted text -Article: 137895
"gm" <gm@nomail.com> wrote in message news:gm3pto$ro$1@ulysses.noc.ntua.gr... > Hi to all > > I haven't touched FPGAs or VHDL since the university years so I was > thinking to get a starter board in order to get back to the path. I did > find some cheap boards out there but I am not sure if I could burn > something like a 32-bit RISC soft core on that. I mean how many logic > blocks (for example of the Xilinx architecture) would be needed for a > project like this, assuming that it is of the size of an OpenSPARC? Could > you suggest me a cheap board (up to $400) with some good features and > maybe an FPGA capable of hosting a good-sized core. Also good features > would be VGA,PS/2,ethernet. Thanks > > Best regards > GM I would suggest you also check out the excellent Leon core (Sparc V8 in VHDL). I just re-synthesised an old leon2.3.7 version and it fits easily in a 3S500E which you can find on most low-cost development boards. http://en.wikipedia.org/wiki/LEON Hans www.ht-lab.com constant conf : config_type := fpga_2k2k; # Info: [694]: Constraints file: leon_pci.pcf. # Info: [694]: Loading device for application Rf_Device from file '3s500e.nph' in environment D:\Xilinx\10.1\ISE. # Info: [694]: "leon_pci" is an NCD, version 3.2, device xc3s500e, package fg320, speed -5 # Info: [694]: Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius) # Info: [694]: Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts) # Info: [694]: Device speed data version: "PRODUCTION 1.27 2008-01-09". # Info: [694]: Design Summary Report: # Info: [694]: Number of External IOBs 101 out of 232 43% # Info: [694]: Number of External Input IOBs 5 # Info: [694]: Number of External Input IBUFs 5 # Info: [694]: Number of External Output IOBs 48 # Info: [694]: Number of External Output IOBs 48 # Info: [694]: Number of External Bidir IOBs 48 # Info: [694]: Number of External Bidir IOBs 48 # Info: [694]: Number of BUFGMUXs 1 out of 24 4% # Info: [694]: Number of RAMB16s 6 out of 20 30% # Info: [694]: Number of Slices 2773 out of 4656 59% # Info: [694]: Number of SLICEMs 36 out of 2328 1% # Info: [694]: Timing summary: # Info: [694]: --------------- # Info: [694]: Timing errors: 0 Score: 0 # Info: [694]: Constraints cover 724930 paths, 0 nets, and 20303 connections # Info: [694]: Design statistics: # Info: [694]: Minimum period: 29.424ns (Maximum frequency: 33.986MHz) # Info: [694]: Minimum input required time before clock: 1.117ns # Info: [694]: Minimum output required time after clock: 11.228ns # Info: [694]: Analysis completed Mon Feb 02 09:28:50 2009 # Info: [694]: --------------------------------------------------------------------------------Article: 137896
On Feb 2, 11:50=A0am, John Adair <g...@enterpoint.co.uk> wrote: > Looking forward to the roadmap that's coming I think FPGAs will move > in new significant areas with these families and hopefully the rollout > will be better than the Spartan-3 mess. > > John Adair > Enterpoint Ltd. yes, I hope it too. And I think the last thing Xilinx wants is to have the s-3 "mess" to happen a second time. and hey, its only a few hours til the "Everything Changes" !! California will wakeup soon, so the new web should come online, unless they have technical problems (webmaster on urgent maternity leave, etc) AnttiArticle: 137897
Hello, I'm implementing a autocorrelation function using a fft and ifft hard core (v6.0) on a Virtex5. When starting the fft, I see at the output that the result is reversed in the frequency domain. Example: The input signal is a sinus with a frequency of 2 Hz. As output signal I expect a dirac impuls at the beginning (imaginary). -> f(0)=0; f(1)=0; f(2)=1; f(3)=0; …; f(N-3)=0; f(N-2)=-1; f(N-1)=0; f(N)=0; (*) But I get: -> f(0)=0; f(1)=0; f(2)=-1; f(3)=0; …; f(N-3)=0; f(N-2)=1; f(N-1)=0; f(N)=0; Other input signals also get the same result, that the output is reversed. Can you please explain me why the output order is reversed? I have no explanation! Is it possible to reorder the output signal like (*)? Best regards, KrisArticle: 137898
On Mon, 2 Feb 2009 02:18:44 -0800 (PST), Antti <Antti.Lukats@googlemail.com> wrote: >On Feb 2, 11:50 am, John Adair <g...@enterpoint.co.uk> wrote: > >> Looking forward to the roadmap that's coming I think FPGAs will move >> in new significant areas with these families and hopefully the rollout >> will be better than the Spartan-3 mess. >> >> John Adair >> Enterpoint Ltd. > >yes, I hope it too. > >And I think the last thing Xilinx wants is to have the s-3 "mess" >to happen a second time. > >and hey, its only a few hours til the "Everything Changes" !! > >California will wakeup soon, so the new web should come >online, unless they have technical problems (webmaster >on urgent maternity leave, etc) http://www.xilinx.com/products/v6s6.htm It seems to be on now. - BrianArticle: 137899
Brian Drummond <brian_drummond@btconnect.com> wrote: ... > http://www.xilinx.com/products/v6s6.htm > It seems to be on now. Argh, no PQ208 option... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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