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Messages from 141850

Article: 141850
Subject: Re: xilinx mfs
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Mon, 13 Jul 2009 14:09:09 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 13, 11:50=A0pm, "hvo" <hai...@synrad.com> wrote:
> Hi,
>
> I am using a spartan 3an device to run a tftp server. =A0Once I transfer =
a
> file using tftp put, I don't know how to read the file back or determine
> where the file was saved to. =A0I am not sure how to use mfs_file_open.
> Could someone help?
>
> Thanks
> hv

MFS is memory file system
it uses part of system memory as if it is file system
read the docs...

Antti

Article: 141851
Subject: Re: Xilinx Spartan 3 DCM no output!
From: "MikeWhy" <boat042-nospam@yahoo.com>
Date: Mon, 13 Jul 2009 16:09:53 -0500
Links: << >>  << T >>  << A >>
"muse_ee" <brian.bubnash@gmail.com> wrote in message 
news:b9b61f51-2f7b-4b3e-a2b3-58848f6ffb06@n30g2000vba.googlegroups.com...
On Jul 13, 10:26 am, gabor <ga...@alacron.com> wrote:
> On Jul 13, 10:05 am, muse_ee <brian.bubn...@gmail.com> wrote:
>
>
>
> > On Jul 13, 3:45 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
>
> > > "muse_ee" <brian.bubn...@jhuapl.edu> writes:
> > > > Hi, I'm trying to learn how to use the DCM's frequency synthesis 
> > > > capability
> > > > to convert a 75MHz clock (on-board oscillator chip) into a 100MHz 
> > > > clock. I
> > > > used Xilinx Architecture wizard to generate the code and the clock
> > > > multiplication works correctly in timing simulation. When I get to 
> > > > the
> > > > bench to test however, I don't get a multiplied clock output - the 
> > > > line is
> > > > 0. I have a couple debug signals that tell me the following:
>
> > > > -75MHz, post BUFG looks fine (I see output from the FPGA)
> > > > -DCM Lock is 0
> > > > -Status(2 downto 0) are all 0.
>
> > > One thought - what does your reset to the DCM look like? It has a
> > > minimum pulse length documented in the datasheet for the part.
>
> > > Cheers,
> > > Martin
>
> > > --
> > > martin.j.thomp...@trw.com
> > > TRW Conekt - Consultancy in Engineering, Knowledge and 
> > > Technologyhttp://www.conekt.net/electronics.html
>
> > Thanks for the reply - I saw the minimum pulse length requirements and
> > so I put this reset pulse extender in. It ensures that any pulse
> > coming from the reset button lasts for at least 256 clock cycles
> > (overkill I know but this was put in well past the point of
> > desperation). I have tried pressing the reset button several minutes
> > after powering the FPGA to see if the clock was slow to stabilize for
> > some reason, but nothing I do seems to make the output from the DCM
> > vary from '0'. Below is my reset manager code:
>
> > rst_manager : process(clk,rstn)
> > variable cnt : std_logic_vector(7 downto 0);
> > variable r : std_logic;
> > constant ones : std_logic_vector(7 downto 0) := (others => '1');
> > begin
> > r := not rstn;
> > if r = '1' then
> > cnt := (others => '0');
> > rst <= '1';
> > elsif rising_edge(clk) then
> > if cnt = ones then
> > rst <= '0';
> > else
> > rst <= '1';
> > cnt := cnt + '1';
> > end if;
> > end if;
> > end process;
>
> What is your clock source? Are you sure it meets the input
> jitter requirements and frequency range requirements?

Thanks for the suggestion. I checked and clock source is a 75MHz
Pletronics clock oscillator, SM7745DW (jitter under 3pS RMS according
to datasheet). I believe that both parameters are within their
acceptable ranges.

=======
Did you see the earlier message regarding tying CLK_FB to CLK_0? UG331 
states: "The feedback input is required unless the Digital Frequency 
Synthesis outputs, CLKFX or CLKFX180, are used stand-alone." You do need the 
feedback if you're using the DLL. (I don't recall your relevant details, 
though.)



Article: 141852
Subject: Re: Xilinx Spartan 3 DCM no output!
From: "alan@nishioka.com" <alan@nishioka.com>
Date: Mon, 13 Jul 2009 16:12:40 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 10, 5:40=A0am, "muse_ee" <brian.bubn...@jhuapl.edu> wrote:
> Hi, I'm trying to learn how to use the DCM's frequency synthesis capabili=
ty
> to convert a 75MHz clock (on-board oscillator chip) into a 100MHz clock.
>
> I've tried the design on 2 different boards, ruling out defective
> hardware. I'm really scratching my head here so I'd greatly appreciate so=
me
> help from a Xilinx guru!

have you looked at the design with fpga_editor to verify everything
looks right?
have you checked that the pin you are looking at can toggle?
(*i've* never made a hw error, but i've heard it is possible)
is this a custom board or off the shelf hw?
perhaps you should post the entire vhdl file and ucf file.  there may
be something wrong elsewhere.

Article: 141853
Subject: Adder size vs Register size
From: Xesium <amirhossein.gholamipour@gmail.com>
Date: Mon, 13 Jul 2009 16:30:25 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
Hope you all are doing fine.
I'm wondering about something.
I know that in Xilinx FPGA architecture for every LUT, there is a Flip-
flop available for storing the output of that LUT.
This necessarily means that the area cost (in number of LUTs or
slices) of for example an 8-bit unregistered adder or a registered
adder is the same.

Is that correct?

Does it also mean that the area cost of an 8-bit register is the same
as the cost of an 8-bit adder?

I consider a carry ripple adder for which the area cost of the adder
is proportional to the bit-width of the adder.

Thanks beforehand for your reply.

Best,

Article: 141854
Subject: Re: About configuring FPGAs
From: mng <michael.jh.ng@gmail.com>
Date: Mon, 13 Jul 2009 18:24:44 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 10, 2:23=A0am, Ben <leowy...@gmail.com> wrote:
> I looked up the Xilinx Virtex 5 and Spartan3 configuration user guide,
> but it doesn't give a step-by-step procedure on how to configure the
> FPGA or connect them. Is there any place where I can find a specific
> design to refer to?

Are you sure you looked at the S3 configuration guide (UG332)? It has
a section titled "Master BPI mode". Also you might want to read the
"Sequence of Events" chapter.

Article: 141855
Subject: Re: Adder size vs Register size
From: rickman <gnuarm@gmail.com>
Date: Mon, 13 Jul 2009 20:52:31 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 13, 7:30=A0pm, Xesium <amirhossein.gholamip...@gmail.com> wrote:
> Hi,
> Hope you all are doing fine.
> I'm wondering about something.
> I know that in Xilinx FPGA architecture for every LUT, there is a Flip-
> flop available for storing the output of that LUT.
> This necessarily means that the area cost (in number of LUTs or
> slices) of for example an 8-bit unregistered adder or a registered
> adder is the same.
>
> Is that correct?

This is one of those questions that can only be answered by "it
depends".  I find that most of my designs use more LUTs than FFs.
That would imply that the number of FFs used is unimportant compared
to the number of LUTs.  Of course, there are some designs that use
more FFs than LUTs, but I find they are the exception.  In fact, some
economy FPGA lines don't provide a FF for *every* LUT.  The one I am
using right now has 3 FFs to 4 LUTs.


> Does it also mean that the area cost of an 8-bit register is the same
> as the cost of an 8-bit adder?

No, if you make that basic assumption that your design is LUT limited,
then the 8 bit register can likely be included for "free".  The LUT
and FF can be used independantly if the routing resources are not the
limiting factor... ***a very big if***

If you are pushing the density of an FPGA, most of them will be
limited by the routing resources before you run out of either FFs or
LUTs.  But it is *very* hard if not impossible to count the routing
resources used by your design, so assumptions have to be made.  The
classic one is to assume that a part is usable up to 80% density
without concern of routing restrictions.  I find you can often push a
design to 90% density if you are not pushing speed at all.

> I consider a carry ripple adder for which the area cost of the adder
> is proportional to the bit-width of the adder.
>
> Thanks beforehand for your reply.
>
> Best,

The easiest way to help your design fit an FPGA is to code the design
in small pieces and make sure each piece is being implemented
efficiently.

I'm not sure what is behind your question.  I sounds like you want to
adjust the architecture to minimize the size of the design.  That may
be a good intent, but it is much more important to assure that the
tools produce an efficient implementation.

Rick

Article: 141856
Subject: Re: Adder size vs Register size
From: Peter Alfke <alfke@sbcglobal.net>
Date: Mon, 13 Jul 2009 22:55:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 13, 4:30=A0pm, Xesium <amirhossein.gholamip...@gmail.com> wrote:
>
> I consider a carry ripple adder for which the area cost of the adder
> is proportional to the bit-width of the adder.

I suppose you mean a "ripple-carry" adder, where the carry control
signal ripples from one bit position to the next higher one.
Xilinx FPGAs have such a structure incorporated "for free". It
actually is more sophisticated and uses carry-look-ahead over several
bits, but that should not concern you.
As a result, you can build fairly wide adders, subtractors and
accumulators that are not limited by the carry propagation delay. It
is "fast enough".
More fundamentally:
When you use FPGAs of a given family and from a given vendor, you
cannot modify the basic architecture. It is what it is, and the basic
cost and performance are given.
It's not up to you to "optimize" cost (really area) at that low level.
I suppose you would not argue with Intel about their cache
implementation either...
Peter Alfke, Xilinx Applications.

Article: 141857
Subject: Re: Xilinx Spartan 3 DCM no output!
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Tue, 14 Jul 2009 08:28:46 +0100
Links: << >>  << T >>  << A >>
muse_ee <brian.bubnash@gmail.com> writes:

> Thanks for the reply - I saw the minimum pulse length requirements and
> so I put this reset pulse extender in. It ensures that any pulse
> coming from the reset button lasts for at least 256 clock cycles
> (overkill I know but this was put in well past the point of
> desperation). I have tried pressing the reset button several minutes
> after powering the FPGA to see if the clock was slow to stabilize for
> some reason, but nothing I do seems to make the output from the DCM
> vary from '0'. Below is my reset manager code:

I assume you're using the "raw" clock to clock this process, not the
(as-yet-non-existent) one from the DCM...  I've heard that's a possible
mistake to make, but obviously I've never done it myself (not a 2nd time
anyway :)

Can you bring your extended reset out to a pin to check it?

The idea of looking with FPGA editor is also a good one.  And check the
feedback!

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 141858
Subject: How to initialize a Rom with a list of coefficients
From: "tpvn2891" <tpvn2891@gmail.com>
Date: Tue, 14 Jul 2009 06:59:17 -0500
Links: << >>  << T >>  << A >>
Hi all,

I am a newbie. 

I hava a list of coefficients in a text file and want these to be loaded
into a ROM, but I don't know how to convert the text file into hex format.

Can anyone please help me to find out how to do this?

Thanks



Article: 141859
Subject: Master initialization problem with xilinx 32 bit pci master/target ipcore
From: "chai2m" <chai2m@gmail.com>
Date: Tue, 14 Jul 2009 06:59:21 -0500
Links: << >>  << T >>  << A >>
I am using 32 bit PCI master/target ipcore from Xilinx.
Xilinx ISE10.1.
http://www.xilinx.com/support/documentation/ip_documentation/pci_64_ug159.pdf


My problem is,  My user application(PCI IP core’s) should be the Master
and when it is trying to request 
the PCI bus, I found a situation that, I have to enable the master bit in
Command register(CSR2).
I tried the initiator write and self configuration write steps from the
pci tutorial, but I can not write into the command register.

When I generate the core from the IP Coregen, I have access to the
configuration space, like
Device ID, Base address registers etc. But I can not access Command
Register.

Can any one please tell me how can I initiate the master? Or Is there any
other way?

Thank you.




Article: 141860
Subject: Re: Generating a negated clock
From: "MM" <mbmsv@yahoo.com>
Date: Tue, 14 Jul 2009 09:56:39 -0400
Links: << >>  << T >>  << A >>
"Nemesis" <gnemesis2001@gmail.com> wrote
>
> Both clocks (CLK and CLK180) are required by a FIFO module.

Which FIFO module?


/Mikhail 



Article: 141861
Subject: Re: How to initialize a Rom with a list of coefficients
From: "maxascent" <maxascent@yahoo.co.uk>
Date: Tue, 14 Jul 2009 10:12:29 -0500
Links: << >>  << T >>  << A >>
If you are using Xilinx then use the core generator software to create a
rom. You can then specfiy the coef you want in a text file and the software
will create the rom for you. 

Jon

Article: 141862
Subject: Re: Generating a negated clock
From: Nemesis <nemesis@nowhere.invalid>
Date: 14 Jul 2009 16:26:07 GMT
Links: << >>  << T >>  << A >>
MM wrote:

> "Nemesis" <gnemesis2001@gmail.com> wrote
>>
>> Both clocks (CLK and CLK180) are required by a FIFO module.
>
> Which FIFO module?

I'm using a module written by the vendor of the boards that mounts the
FPGA.

-- 
I told my psychiatrist that everyone hates me. He said I was being
ridiculous - everyone hasn't met me yet.
 _  _                  _
| \| |___ _ __  ___ __(_)___
| .` / -_) '  \/ -_|_-< (_-<
|_|\_\___|_|_|_\___/__/_/__/ http://xpn.altervista.org


Article: 141863
Subject: Re: How to initialize a Rom with a list of coefficients
From: AndreasWallner <Andreas.Wallner.etm07@fh-joanneum.at>
Date: Tue, 14 Jul 2009 10:02:02 -0700 (PDT)
Links: << >>  << T >>  << A >>
Converting the coefficients to binary / hex should not be a problem in
e.g. C/C++ or any other programming/scripting language.
If you provide information about the source and target format you
need, I could post the neccessary code.

Regards,
Andreas

Article: 141864
Subject: Re: Xilinx Spartan 3 DCM no output!
From: muse_ee <brian.bubnash@gmail.com>
Date: Tue, 14 Jul 2009 10:49:09 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 14, 3:28=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
> muse_ee <brian.bubn...@gmail.com> writes:
> > Thanks for the reply - I saw the minimum pulse length requirements and
> > so I put this reset pulse extender in. It ensures that any pulse
> > coming from the reset button lasts for at least 256 clock cycles
> > (overkill I know but this was put in well past the point of
> > desperation). I have tried pressing the reset button several minutes
> > after powering the FPGA to see if the clock was slow to stabilize for
> > some reason, but nothing I do seems to make the output from the DCM
> > vary from '0'. Below is my reset manager code:
>
> I assume you're using the "raw" clock to clock this process, not the
> (as-yet-non-existent) one from the DCM... =A0I've heard that's a possible
> mistake to make, but obviously I've never done it myself (not a 2nd time
> anyway :)
>
> Can you bring your extended reset out to a pin to check it?
>
> The idea of looking with FPGA editor is also a good one. =A0And check the
> feedback!
>
> Cheers,
> Martin
>
> --
> martin.j.thomp...@trw.com
> TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w=
ww.conekt.net/electronics.html

Solved! You all will get a good laugh out of this one I'm sure - my
reset line didn't have a pullup installed, which was required for the
underlying circuit to work properly. Enabling the FPGA's internal
pullup solved the issue. Thanks to everyone who replied, it was very
much appreciated!

Brian

Article: 141865
Subject: Re: How to initialize a Rom with a list of coefficients
From: "tpvn2891" <tpvn2891@gmail.com>
Date: Tue, 14 Jul 2009 13:14:18 -0500
Links: << >>  << T >>  << A >>
>If you are using Xilinx then use the core generator software to create a
>rom. You can then specfiy the coef you want in a text file and the
software
>will create the rom for you. 
>
>Jon
>

Thanks Jon and Andreas,

I am using Quartus. The coefficients I can generate in any form by using
Matlab, then I can store these in a text file.

The problem is that I dont know how to convert a text file to hex file so
that can be used to initialize a rom.

Thank you,

TP

Article: 141866
Subject: Re: Adder size vs Register size
From: Amir <amirhossein.gholamipour@gmail.com>
Date: Tue, 14 Jul 2009 11:31:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
Rick and Peter,
Thanks so much for your replies. They are extremely informative
indeed.
This is part of my PhD research to optimize some filtering circuits
for the architecture of FPGAs. I'm in particular working on Xilinx
Virtex devices. There is this binary adder tree that I design which in
parallel adds some inputs. However since the frequency becomes very
low, I was thinking to insert some registers in between and make it a
pipeline. So I was concerned about the area. From your explanation and
looking at the detailed architecture of a CLB (Xilinx ds031, Page 21)
I realized that the FF can be used to store not just the output of the
corresponding LUT but also some other inputs to the slice. So in fact
if I use a LUT, it costs me nothing to also use the FF next to it.
However that FF can be used to store some other signals generated from
other LUTs.

So putting this next to what Rick said which says most of the designs
are LUT limited than FF limited, then I guess depending on the design,
it might cost me nothing to add registers to my design. Because my
design is already using the LUTs and assuming enough abandoned wires
(big assumption indeed) using the FFs in those slices I can also
implement my registers.
On the other hand it also might cost me some more slices to implement
the additional pipeline registers if there is not enough wire or not
enough free FFs in the slices where LUTs have already been used. Or
even simply because the tool couldn't handle the available resources.

Of course I understand what Peter is saying about the low level
handling of the tools and architecture. I understand that I don't have
much of flexibility at so low a level but I'm more concerned about the
possibilities based on the facts than really the ability to exactly do
it.


Did I get your points correctly?

Thanks a lot again,
Amir

On Jul 13, 10:55=A0pm, Peter Alfke <al...@sbcglobal.net> wrote:
> On Jul 13, 4:30=A0pm, Xesium <amirhossein.gholamip...@gmail.com> wrote:
>
>
>
> > I consider a carry ripple adder for which the area cost of the adder
> > is proportional to the bit-width of the adder.
>
> I suppose you mean a "ripple-carry" adder, where the carry control
> signal ripples from one bit position to the next higher one.
> Xilinx FPGAs have such a structure incorporated "for free". It
> actually is more sophisticated and uses carry-look-ahead over several
> bits, but that should not concern you.
> As a result, you can build fairly wide adders, subtractors and
> accumulators that are not limited by the carry propagation delay. It
> is "fast enough".
> More fundamentally:
> When you use FPGAs of a given family and from a given vendor, you
> cannot modify the basic architecture. It is what it is, and the basic
> cost and performance are given.
> It's not up to you to "optimize" cost (really area) at that low level.
> I suppose you would not argue with Intel about their cache
> implementation either...
> Peter Alfke, Xilinx Applications.


Article: 141867
Subject: Minimal size 1-bit adder....
From: Xesium <amirhossein.gholamipour@gmail.com>
Date: Tue, 14 Jul 2009 12:15:09 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
I'm wondering, using Xilinx CLB architecture, and hypothetically
assuming that we have direct control over the configuration bits and
detailed knowledge about the configuration, how can one minimally
design an adder which adds 15, 1-bit signals.

The result is 4 bits wide (it can be at most 1111 (=15)), so is it
possible to just use 4 LUTs (2 slices) to implement such a circuit?

I wrote a very basic VHDL code and after synthesizing it using ISE,
the result was 12 slices and 18 LUTs.

However I'm still wondering what is the best that can be achieved
theoretically based on the capabilities of the architecture.


Thanks beforehand for your replies and thoughts,
Amir

Article: 141868
Subject: Re: Minimal size 1-bit adder....
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Tue, 14 Jul 2009 20:25:19 +0100
Links: << >>  << T >>  << A >>
On Tue, 14 Jul 2009 12:15:09 -0700 (PDT), Xesium
<amirhossein.gholamipour@gmail.com> wrote:

>Hi,
>I'm wondering, using Xilinx CLB architecture, and hypothetically
>assuming that we have direct control over the configuration bits and
>detailed knowledge about the configuration, how can one minimally
>design an adder which adds 15, 1-bit signals.
>
>The result is 4 bits wide (it can be at most 1111 (=15)), so is it
>possible to just use 4 LUTs (2 slices) to implement such a circuit?

I don't think so.  I know how to do it in 9 LUTs.

Of course, a serial adder with 4 bit accumulator (better known 
as a "counter with count enable") would be the smallest...

I'll post the 9-LUT solution tomorrow unless someone comes
up with something better meanwhile.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 141869
Subject: Re: Minimal size 1-bit adder....
From: Muzaffer Kal <kal@dspia.com>
Date: Tue, 14 Jul 2009 12:51:43 -0700
Links: << >>  << T >>  << A >>
On Tue, 14 Jul 2009 12:15:09 -0700 (PDT), Xesium
<amirhossein.gholamipour@gmail.com> wrote:

>Hi,
>I'm wondering, using Xilinx CLB architecture, and hypothetically
>assuming that we have direct control over the configuration bits and
>detailed knowledge about the configuration, how can one minimally
>design an adder which adds 15, 1-bit signals.
>
>The result is 4 bits wide (it can be at most 1111 (=15)), so is it
>possible to just use 4 LUTs (2 slices) to implement such a circuit?
>
Assuming you're talking about 4 input LUTs, no it's not possible to do
what you want. LSB of the output depends on the values of all bits of
the input so a single LUT by just looking any of the 4 inputs can not
give the value of the LSB. Actually to be able to do it in a single
level, single LUT you need a 15 input LUT which no current FPGA has.

>I wrote a very basic VHDL code and after synthesizing it using ISE,
>the result was 12 slices and 18 LUTs.
>
>However I'm still wondering what is the best that can be achieved
>theoretically based on the capabilities of the architecture.

Unfortunately my level of algebra is not good enough to come up with
an theoretically optimal number but I'm sure this number can be
obtained for such a small problem if one is motivated enough.
-
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Article: 141870
Subject: Re: How to initialize a Rom with a list of coefficients
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Tue, 14 Jul 2009 15:03:13 -0500
Links: << >>  << T >>  << A >>

>The problem is that I dont know how to convert a text file to hex file so
>that can be used to initialize a rom.

A hex file is text.  Poke around a bit and find the specs
for the file format.  Then either write your stuff out in
that format or write a small program to convert from
what you have to want.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 141871
Subject: Re: Generating a negated clock
From: "MM" <mbmsv@yahoo.com>
Date: Tue, 14 Jul 2009 16:19:54 -0400
Links: << >>  << T >>  << A >>
"Nemesis" <nemesis@nowhere.invalid> wrote
>
> I'm using a module written by the vendor of the boards that mounts the
> FPGA.
>

1. Why don't you use Xilinx core? It will work happily with a single clock.
2. If you really need to invert a DCM CLKDIV clock it you can use a second 
DCM.

Also, take a look at the PMCD (Phase-Matched Clock Divider) V4 primitive.


/Mikhail 



Article: 141872
Subject: Problem with System ACE, can't get it to work with partitioned Card
From: AndreasWallner <Andreas.Wallner.etm07@fh-joanneum.at>
Date: Tue, 14 Jul 2009 13:46:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

I have a Problem getting the System ACE Controller to work.
I try it on a Spartan 3A DSP 1800 Board, to which I connected a
SystemACE Module from AVNet.

If I format the CF Card completly, and do not create any partitions
(the drive then only contains the FAT16).

If I try to create two partitions (with linux fdisk, one 64MB
Partition, and the second spanning the remaining card), format the
first one to FAT16 and copy the exact same files to the card the
System ACE board only displays an error and does not load the design.

Are there any special points to take into consideration?

Regards,
Andreas

Article: 141873
Subject: Re: How to implementa an FSM in block ram
From: Assaf <assafshacham@gmail.com>
Date: Tue, 14 Jul 2009 14:24:59 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 9, 11:01=A0pm, backhus <goo...@twinmail.de> wrote:
> in the map properties you find an option "Map Slice Logic into unused
> Block RAMs", wich is disabled by default.
> Enable it. :-)

This option (-bp) is defective. At least in in ISE 10.1.

For some weird reason it mapped a 2-LUT mux logic into a BRAM, and the
bit got stuck at zero. Simulation and even post-ngd simulation worked
perfectly, but the device didn't work. Took 3 days of my life to debug
this. Not touching this ever again.

Assaf

Article: 141874
Subject: Re: Adder size vs Register size
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 14 Jul 2009 21:37:18 +0000 (UTC)
Links: << >>  << T >>  << A >>
Amir <amirhossein.gholamipour@gmail.com> wrote:

< This is part of my PhD research to optimize some filtering circuits
< for the architecture of FPGAs. I'm in particular working on Xilinx
< Virtex devices. There is this binary adder tree that I design which in
< parallel adds some inputs. However since the frequency becomes very
< low, I was thinking to insert some registers in between and make it a
< pipeline. So I was concerned about the area. From your explanation and
< looking at the detailed architecture of a CLB (Xilinx ds031, Page 21)
< I realized that the FF can be used to store not just the output of the
< corresponding LUT but also some other inputs to the slice. So in fact
< if I use a LUT, it costs me nothing to also use the FF next to it.
< However that FF can be used to store some other signals generated from
< other LUTs.

Well, if the input to an FF is the output of an LUT, it will likely
route to the nearby LUT.  The next possibility is an output of a FF.
From what I have seen, chained FF often generate SRL16 instead.
 
< So putting this next to what Rick said which says most of the designs
< are LUT limited than FF limited, then I guess depending on the design,
< it might cost me nothing to add registers to my design. Because my
< design is already using the LUTs and assuming enough abandoned wires
< (big assumption indeed) using the FFs in those slices I can also
< implement my registers.

Yes.  For some designs, it takes additional FF to keep different
parts of the pipeline together.  Those are the ones that easily
become SRL16.

< On the other hand it also might cost me some more slices to implement
< the additional pipeline registers if there is not enough wire or not
< enough free FFs in the slices where LUTs have already been used. Or
< even simply because the tool couldn't handle the available resources.

-- glen 



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