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Messages from 138150

Article: 138150
Subject: Re: Recommended Xilinx USB JTAG cable?
From: emeb <ebrombaugh@gmail.com>
Date: Sat, 7 Feb 2009 19:46:29 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 7, 8:13=A0pm, John Eaton <nos...@spam.com> wrote:

> Digilent =A0(www.digilentinc.com) sells a nice usb to 6 pin cable for
> $37.95. =A0Problem is it only works with their windoze software. Would be
> nice if they supported linux.

I've got one of these and it works nicely (very fast) under WinXP,
although the driver application has a few limitations (can only
configure, not verify / readback). There is an open source app that
purports to drive this device here:

http://sourceforge.net/projects/xilprg

It's a few years out of date and the author seems to have dropped off
the face of the planet. I've tried this with my Digilent USB<->JTAG
cable and while it recognizes the device it can't seem to detect any
devices on the bus. Hanging a 'scope probe from the JTAG signals shows
that they're not moving, so I suspect there are still some issues. It
might be a good starting point for someone who knows more about this
than I do.

Eric (not the OP)

Article: 138151
Subject: Re: clk synchronization of reset signal
From: John Eaton <nospam@spam.com>
Date: Sat, 07 Feb 2009 19:55:19 -0800
Links: << >>  << T >>  << A >>
Muzaffer Kal wrote:
> On Fri, 6 Feb 2009 15:23:30 -0800 (PST), axr0284 <axr0284@yahoo.com>
> wrote:
> 
>> I would like to use the reset to reset my internal logic (Everything
>> is synchronously reset) but I am wondering if the external reset
>> signal need to go through the double buffer too before being sent to
>> the logic.
> Absolutely. Reset is definitely more sensitive to synchronization
> issues because it's usually distributed to a very large number of
> sinks and by its nature getting all blocks out of reset simultaneously
> is quite important so you should definitely synchronize reset to your
> internal clock(s).

This was true 30 or 40 years ago but is not true for todays designs. 
Back then when reset was released a component would self start and begin
"componenting". Everybody had to start at the same cycle.

Todays designs are usually embedded cpu based. When a modern component 
is released from reset it simply waits around for the cpu to set it up 
and enable it. All of it's flops stay in their reset state until the
cpu does something.

You don't have to release everybody on the same exact cycle. You only 
have to ensure that everybody is ready well before the cpu starts. You 
do this by distributing your reset around the chip and then delaying the 
cpu's start long enough  for the worst case component to be ready.

This can take a long time (milliseconds). FPGA's have to load. 
Repairable srams have to configure. Bist test have to run.



> 
>> If yes, then what do I use to reset my double buffer?
> 
> There is no need. As you know the reset will come active at some point
> early in the life of the circuit and the clock will be running, these
> registers will get loaded by the right values externally.
> 
> Actually this brings up a point. The standard two bit shift register
> and synchronous reset needs a clock to be active. What I like better
> is to use a synchronized asynchronous reset which gives you the better
> of the choices (in my opinion). You get to reset all your circuits
> asynchronously even with out a clock and release of the reset is done
> synchronously to your clock so you can make sure the timing is clean.
> In that case you can still use two registers in shift mode but you can
> connect the reset to the async reset input of these two flops only and
> use the output to async reset all your other flops. The input of the
> first flop should connect to high so when your external reset is
> activated (goes low) the output becomes low.
> 
> 

This is also what I use and recommend. But don't stop at two stages, 
bump it up to 10 or 20. That makes it easier to distribute the reset 
across a large chip.

Cliff Cummings of Sunburst Design has some papers on synchronous reset 
trees that show how to distribute your reset.



John Eaton






> Muzaffer Kal
> 
> DSPIA INC.
> ASIC/FPGA Design Services
> http://www.dspia.com

Article: 138152
Subject: C-NIT source
From: bereg <balazs.beregnyei@gmail.com>
Date: Sun, 8 Feb 2009 01:13:36 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi all,

I'm looking for the Verilog sources of c-nit processor. I's an
opencore project, but there are no c-nit files on the opencores.net,
and the related website (http://www.c-nit.net) can't help, it's only a
collection of links without content. Can anybody help me?

Thanks,
BB

Article: 138153
Subject: Re: PLDShell Plus V5.1
From: John Adair <g1@enterpoint.co.uk>
Date: Sun, 8 Feb 2009 03:38:05 -0800 (PST)
Links: << >>  << T >>  << A >>
These devices were based on the original Intel Flexlogic and were
generally good but did have the limitation of a 24V10 internal block
structures. A lot of designs struggled with the fan-in limitations and
the family didn't last long as an Altera product probably in part
because of this. From my scratchy memory I think use of these pretty
much died out about 10-12 years ago.

John Adair
Enterpoint Ltd.


On 8 Feb, 01:14, hartono.seti...@gmail.com wrote:
> Hi, I have lots (thousands) of Altera EPX880 (FlashLogic). This device
> is obsolete and the only software I know that can be used to design it
> is PLDShell Plus V5.1. =A0Anybody know where to download it please...???
> I contacted Altera they said they don't have it anymore...
>
> Thanks and best regards,
> Hart


Article: 138154
Subject: Re: Experiencing problems when moving an FPGA-based implementation to
From: mikej <mikej.swe@gmail.com>
Date: Sun, 8 Feb 2009 04:04:42 -0800 (PST)
Links: << >>  << T >>  << A >>
First of all you need to understand and simulate the code you are
converting. I suspect it is a memory controller of some sort? Without
knowing what the code does it is difficult to respond to your
questions.

As an FPGA and a ASIC engineer I can say you cannot expect code
written for an FPGA to just work in an ASIC. Most designs use the IO
functions extensively.

Look at the Xilinx library guide, it gives extensive documentation on
these primitives. If you look at the Unisim library from Xilinx you
can see the simulation models.

BUF* can be ignored but watch the skew and timing in the ASIC flow.

ODDR is an stage with two flip flops and a mux. If you are producing a
clock a common trick is to wire the two inputs to '1' and '0'. This
gives better control of the output clock phase, and it is time aligned
with other ODDR data pins - useful for talking to memories etc.
Sometimes the clock to the ODDR clock forward output is 90deg phase
shifted by a DCM or PLL so it is placed in the middle of the data eye.

The IDELAYCTRL module is not needed. It is used in the Xilinx to
calibrate the IDELAY delay lines using an external 200MHz reference
clock. It only makes sense to use this block if you are also using the
IDELAY blocks which are used to delay input signals by a programmable
delay.
/MikeJ

Article: 138155
Subject: offtnproblem during ise synthesis
From: GrIsH <grishkunwar@gmail.com>
Date: Sun, 8 Feb 2009 04:45:21 -0800 (PST)
Links: << >>  << T >>  << A >>
hi all i have been trying to synthesize a module in ise. but while
trying to assign the pins after generating ucf file following message
was displayed



loading device for application Rf_device from file ''v50 nph' in
environment C:\xilinx10.1\ise.
ERROR:HDLParsers:3562 pepExtractor.prj line1Expecting 'vhdl' or
'verilog' keyword found 'work'.

i really dont know what to do.
any suggestions would be highly appreciated.

thank you.

Article: 138156
Subject: Re: offtnproblem during ise synthesis
From: Alan Fitch <apfitch@invalid.invalid>
Date: Sun, 08 Feb 2009 12:52:46 +0000
Links: << >>  << T >>  << A >>
GrIsH wrote:
> hi all i have been trying to synthesize a module in ise. but while
> trying to assign the pins after generating ucf file following message
> was displayed
> 
> 
> 
> loading device for application Rf_device from file ''v50 nph' in
> environment C:\xilinx10.1\ise.
> ERROR:HDLParsers:3562 pepExtractor.prj line1Expecting 'vhdl' or
> 'verilog' keyword found 'work'.
> 
> i really dont know what to do.
> any suggestions would be highly appreciated.
> 
> thank you.

Try google, which gives you:

http://forums.xilinx.com/xlnx/board/message?board.id=ISE&thread.id=119

which says "don't have a space in your directory path",

regards
Alan

-- 
Alan Fitch
apfitch at ieee
dot org

Article: 138157
Subject: Re: C-NIT source
From: Antti <Antti.Lukats@googlemail.com>
Date: Sun, 8 Feb 2009 05:04:21 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 8, 11:13=A0am, bereg <balazs.beregn...@gmail.com> wrote:
> Hi all,
>
> I'm looking for the Verilog sources of c-nit processor. I's an
> opencore project, but there are no c-nit files on the opencores.net,
> and the related website (http://www.c-nit.net) can't help, it's only a
> collection of links without content. Can anybody help me?
>
> Thanks,
> BB

this happens when domain expires.
so the links are just some link-harvestor generated bs!?

it means the project is dead usually

Antti

Article: 138158
Subject: Re: Recommended Xilinx USB JTAG cable?
From: Arnim <clv.5.minral@spamgourmet.com>
Date: Sun, 08 Feb 2009 14:17:09 +0100
Links: << >>  << T >>  << A >>
Hi Eric,

You might want to have look at http://urjtag.org/ It's a command line
tool to control the JTAG chain. Apart from generic shifting, it contains
an SVF player for FPGA/CPLD configuration and features various
algorithms to program on-board flash and RAM.

> Given these, what do people recommend for programming their Xilinx 
> devices? I'd like the following: 1. Works close-to-out-of-the-box
> under linux

Yes, requires low-level libraries like libusb, libftdi, libftd2xx.

> 2. Cheap (<$250)

Software is open source. Supported USB based JTAG pods are from EUR30
upwards.

> 3. Non-horrible software that works under 32- and 64-bit OSes,
> ideally with source

Comes as source. Horrible or not is up to the user's impression :-)

> 4. the ability to get at the USERn registers from the FPGA, either 
> from the command line or an API.

Any JTAG register is accessible by generic instructions on the command
line. You can use special registers that aren't part of the vendor's
BSDL description.

> 5. ships out-of-the-box with the xilinx 2x7 2mm header for JTAG.

Supported USB pods:
- USB Blaster
- a variety of FT2232 based pods, preferably Amontec's JTAGkey and
  ARM-USB-OCD by Olimex
- very experimental Platform USB Cable / DLC9

There's no link to the A & X vendor software howsoever. Things like
ChipScope aren't covered at all. Just plain access to the JTAG interface.

Arnim

Article: 138159
Subject: Re: C-NIT source
From: John McCaskill <jhmccaskill@gmail.com>
Date: Sun, 8 Feb 2009 07:08:32 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 8, 3:13=A0am, bereg <balazs.beregn...@gmail.com> wrote:
> Hi all,
>
> I'm looking for the Verilog sources of c-nit processor. I's an
> opencore project, but there are no c-nit files on the opencores.net,
> and the related website (http://www.c-nit.net) can't help, it's only a
> collection of links without content. Can anybody help me?
>
> Thanks,
> BB


The Archive.org project takes snapshots of many web sites and lets you
look at them with their "WaybackMachine". They have copies of the c-
nit.net site:

http://web.archive.org/web/*/http://www.c-nit.net/

The April 2nd 2005 snapshot looks like the last copy that had any real
content:

http://web.archive.org/web/20050402121340/http://www.c-nit.net/

While Archive.org frequently does not archive download files, it did
get at least the Verilog code for the CPU:

http://web.archive.org/web/20050405042643/www.c-nit.net/src/cpu.v

Regards

John McCaskill
FasterTechnology.com

Article: 138160
Subject: Is this phase accumulator trick well-known???
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sun, 08 Feb 2009 17:02:41 +0000
Links: << >>  << T >>  << A >>
hi comp.arch.fpga,
(accidentally posted to comp.lang.vhdl 
a few moments ago- sorry)

The question - repeated after the explanation - 
is: here's what I think is a nifty trick; has
anyone seen it, or been aware of it, before?
I can't believe it's really new.

I have been messing around with baud rate generators
and suchlike - creating a pulse that's active for
one clock period at some required repetition rate -
and wanted to try a phase accumulator technique 
instead of a simple divider.  That makes it far 
easier to specify the frequency - it's simply the
phase-delta input value - and easily allows for
non-integral divide ratios, at the cost of one
master clock period of jitter.

The phase-accumulator produces pulses with a
repetition rate of 
  Fc * M / N 
where Fc is the master clock, M is the phase delta
and N is the counter's modulus.  However, to get
the huge convenience of specifying M as the required
frequency, I must make N be equal to the frequency
of Fc, and this is unlikely to be an exact power of 2.
So the phase accumulator works like this:

  on every clock pulse...
    if (acc < 0) then
      add := acc + N;
      output_pulse <= '1';
    else
      output_pulse <= '0';
    end if;
    acc := acc - M;  -- unconditionally

This is fine, but it means that on the "wrap-around"
clock cycle I must add either N-M to the accumulator;
if either M or N are variable, that costs me another
adder.

Today I came up with an intriguing (to me) alternative:
on the wrap-around cycle, add N to the accumulator;
on the immediately subsequent cycle, add (-2M); on
all other cycles, add (-M).  This is of course rather
easy to do since 2M is just a left shift.  A few 
trial synthesis runs convinced me that it will give
measurably better performance than the two-adder
version.  VHDL code is appended for anyone who wants
to play.

My question is: has this trick been published anywhere?
Or is it something that "those skilled in the art"
already know about?  I haven't seen it before, but that 
simply means I probably haven't looked hard enough.

Thanks!

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~ rate generator using novel wrap-around technique
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity rate_gen is
  -- Specify the master clock frequency as a generic.
  generic ( ref_Hz: positive := 50_000_000 );
  port
    ( clock : in  std_logic
    ; reset : in  std_logic  -- Synchronous reset.
    ; rate  : in  unsigned   -- Desired output frequency
    ; pulse : out std_logic  -- The output pulse train
    );
end;

architecture RTL of rate_gen is
begin
  process (clock)
    -- variable "count" is the accumulator
    variable count: integer range -2**rate'length to ref_Hz-1 := 0;
    -- variable "overflow" is the output pulse and wraparound marker
    variable overflow: std_logic := '0';
  begin
    if rising_edge(clock) then
      if reset = '1' then
        count := 0;
        overflow := '0';
      elsif count < 0 then
        overflow := '1';
        count := count + ref_Hz;
      elsif overflow = '1' then
        overflow := '0';
        count := count - (to_integer(rate) * 2);
      else
        overflow := '0';
        count := count - to_integer(rate);
      end if;
      pulse <= overflow;
    end if;
  end process;
end;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 138161
Subject: Re: PLDShell Plus V5.1
From: hartono.setiono@gmail.com
Date: Sun, 8 Feb 2009 10:00:51 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 8, 6:38=A0pm, John Adair <g...@enterpoint.co.uk> wrote:
> These devices were based on the original Intel Flexlogic and were
> generally good but did have the limitation of a 24V10 internal block
> structures. A lot of designs struggled with the fan-in limitations and
> the family didn't last long as an Altera product probably in part
> because of this. From my scratchy memory I think use of these pretty
> much died out about 10-12 years ago.
>
> John Adair
> Enterpoint Ltd.
You are right of course, I just think that at less than $0.2 a pc for
an 80 macro cells, 10 kbits ram option PLD, it's relatively cheap.
The problem is if you can really can use it or not...

Article: 138162
Subject: Re: Is this phase accumulator trick well-known???
From: Antti <Antti.Lukats@googlemail.com>
Date: Sun, 8 Feb 2009 10:12:03 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 8, 7:02=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> hi comp.arch.fpga,
> (accidentally posted to comp.lang.vhdl
> a few moments ago- sorry)
>
> The question - repeated after the explanation -
> is: here's what I think is a nifty trick; has
> anyone seen it, or been aware of it, before?
> I can't believe it's really new.
>
> I have been messing around with baud rate generators
> and suchlike - creating a pulse that's active for
> one clock period at some required repetition rate -
> and wanted to try a phase accumulator technique
> instead of a simple divider. =A0That makes it far
> easier to specify the frequency - it's simply the
> phase-delta input value - and easily allows for
> non-integral divide ratios, at the cost of one
> master clock period of jitter.
>
> The phase-accumulator produces pulses with a
> repetition rate of
> =A0 Fc * M / N
> where Fc is the master clock, M is the phase delta
> and N is the counter's modulus. =A0However, to get
> the huge convenience of specifying M as the required
> frequency, I must make N be equal to the frequency
> of Fc, and this is unlikely to be an exact power of 2.
> So the phase accumulator works like this:
>
> =A0 on every clock pulse...
> =A0 =A0 if (acc < 0) then
> =A0 =A0 =A0 add :=3D acc + N;
> =A0 =A0 =A0 output_pulse <=3D '1';
> =A0 =A0 else
> =A0 =A0 =A0 output_pulse <=3D '0';
> =A0 =A0 end if;
> =A0 =A0 acc :=3D acc - M; =A0-- unconditionally
>
> This is fine, but it means that on the "wrap-around"
> clock cycle I must add either N-M to the accumulator;
> if either M or N are variable, that costs me another
> adder.
>
> Today I came up with an intriguing (to me) alternative:
> on the wrap-around cycle, add N to the accumulator;
> on the immediately subsequent cycle, add (-2M); on
> all other cycles, add (-M). =A0This is of course rather
> easy to do since 2M is just a left shift. =A0A few
> trial synthesis runs convinced me that it will give
> measurably better performance than the two-adder
> version. =A0VHDL code is appended for anyone who wants
> to play.
>
> My question is: has this trick been published anywhere?
> Or is it something that "those skilled in the art"
> already know about? =A0I haven't seen it before, but that
> simply means I probably haven't looked hard enough.
>
> Thanks!
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> ~~ rate generator using novel wrap-around technique
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
>
> entity rate_gen is
> =A0 -- Specify the master clock frequency as a generic.
> =A0 generic ( ref_Hz: positive :=3D 50_000_000 );
> =A0 port
> =A0 =A0 ( clock : in =A0std_logic
> =A0 =A0 ; reset : in =A0std_logic =A0-- Synchronous reset.
> =A0 =A0 ; rate =A0: in =A0unsigned =A0 -- Desired output frequency
> =A0 =A0 ; pulse : out std_logic =A0-- The output pulse train
> =A0 =A0 );
> end;
>
> architecture RTL of rate_gen is
> begin
> =A0 process (clock)
> =A0 =A0 -- variable "count" is the accumulator
> =A0 =A0 variable count: integer range -2**rate'length to ref_Hz-1 :=3D 0;
> =A0 =A0 -- variable "overflow" is the output pulse and wraparound marker
> =A0 =A0 variable overflow: std_logic :=3D '0';
> =A0 begin
> =A0 =A0 if rising_edge(clock) then
> =A0 =A0 =A0 if reset =3D '1' then
> =A0 =A0 =A0 =A0 count :=3D 0;
> =A0 =A0 =A0 =A0 overflow :=3D '0';
> =A0 =A0 =A0 elsif count < 0 then
> =A0 =A0 =A0 =A0 overflow :=3D '1';
> =A0 =A0 =A0 =A0 count :=3D count + ref_Hz;
> =A0 =A0 =A0 elsif overflow =3D '1' then
> =A0 =A0 =A0 =A0 overflow :=3D '0';
> =A0 =A0 =A0 =A0 count :=3D count - (to_integer(rate) * 2);
> =A0 =A0 =A0 else
> =A0 =A0 =A0 =A0 overflow :=3D '0';
> =A0 =A0 =A0 =A0 count :=3D count - to_integer(rate);
> =A0 =A0 =A0 end if;
> =A0 =A0 =A0 pulse <=3D overflow;
> =A0 =A0 end if;
> =A0 end process;
> end;
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

Dear Jonathan

you wrote that you have made a few trial synthesis runs with the code
you appended.
can you tell what synthesis tool did you use?

How many LUT/ FF did you get for say Xilinx S-3 family as target
device?

I tried Xilinx XST and I have to admit I do not know how to make your
unmodified code to pass Xilinx synthesis without errors.
Maybe everybody else can do that, of course this is possible too - but
I prefer to use VHDL that is KNOWN for ME that
it passes synthesis for multiply FPGA vendor toolchains. If your code
is actually able to pass synthesis then it is not
yet known to me HOW.

Xilinx claims to dominate the FPGA market with 50% gloval share, so if
some VHDL is not working with Xilinx tools,
then the use of it already limited to < 50% (at least if we as per
Xilinx saying..)

Antti










Article: 138163
Subject: Re: Is this phase accumulator trick well-known???
From: Antti <Antti.Lukats@googlemail.com>
Date: Sun, 8 Feb 2009 10:27:08 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 8, 8:12=A0pm, Antti <Antti.Luk...@googlemail.com> wrote:
> On Feb 8, 7:02=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> wrote:
>
>
>
> > hi comp.arch.fpga,
> > (accidentally posted to comp.lang.vhdl
> > a few moments ago- sorry)
>
> > The question - repeated after the explanation -
> > is: here's what I think is a nifty trick; has
> > anyone seen it, or been aware of it, before?
> > I can't believe it's really new.
>
> > I have been messing around with baud rate generators
> > and suchlike - creating a pulse that's active for
> > one clock period at some required repetition rate -
> > and wanted to try a phase accumulator technique
> > instead of a simple divider. =A0That makes it far
> > easier to specify the frequency - it's simply the
> > phase-delta input value - and easily allows for
> > non-integral divide ratios, at the cost of one
> > master clock period of jitter.
>
> > The phase-accumulator produces pulses with a
> > repetition rate of
> > =A0 Fc * M / N
> > where Fc is the master clock, M is the phase delta
> > and N is the counter's modulus. =A0However, to get
> > the huge convenience of specifying M as the required
> > frequency, I must make N be equal to the frequency
> > of Fc, and this is unlikely to be an exact power of 2.
> > So the phase accumulator works like this:
>
> > =A0 on every clock pulse...
> > =A0 =A0 if (acc < 0) then
> > =A0 =A0 =A0 add :=3D acc + N;
> > =A0 =A0 =A0 output_pulse <=3D '1';
> > =A0 =A0 else
> > =A0 =A0 =A0 output_pulse <=3D '0';
> > =A0 =A0 end if;
> > =A0 =A0 acc :=3D acc - M; =A0-- unconditionally
>
> > This is fine, but it means that on the "wrap-around"
> > clock cycle I must add either N-M to the accumulator;
> > if either M or N are variable, that costs me another
> > adder.
>
> > Today I came up with an intriguing (to me) alternative:
> > on the wrap-around cycle, add N to the accumulator;
> > on the immediately subsequent cycle, add (-2M); on
> > all other cycles, add (-M). =A0This is of course rather
> > easy to do since 2M is just a left shift. =A0A few
> > trial synthesis runs convinced me that it will give
> > measurably better performance than the two-adder
> > version. =A0VHDL code is appended for anyone who wants
> > to play.
>
> > My question is: has this trick been published anywhere?
> > Or is it something that "those skilled in the art"
> > already know about? =A0I haven't seen it before, but that
> > simply means I probably haven't looked hard enough.
>
> > Thanks!
>
> > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > ~~ rate generator using novel wrap-around technique
> > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > library ieee;
> > use ieee.std_logic_1164.all;
> > use ieee.numeric_std.all;
>
> > entity rate_gen is
> > =A0 -- Specify the master clock frequency as a generic.
> > =A0 generic ( ref_Hz: positive :=3D 50_000_000 );
> > =A0 port
> > =A0 =A0 ( clock : in =A0std_logic
> > =A0 =A0 ; reset : in =A0std_logic =A0-- Synchronous reset.
> > =A0 =A0 ; rate =A0: in =A0unsigned =A0 -- Desired output frequency
> > =A0 =A0 ; pulse : out std_logic =A0-- The output pulse train
> > =A0 =A0 );
> > end;
>
> > architecture RTL of rate_gen is
> > begin
> > =A0 process (clock)
> > =A0 =A0 -- variable "count" is the accumulator
> > =A0 =A0 variable count: integer range -2**rate'length to ref_Hz-1 :=3D =
0;
> > =A0 =A0 -- variable "overflow" is the output pulse and wraparound marke=
r
> > =A0 =A0 variable overflow: std_logic :=3D '0';
> > =A0 begin
> > =A0 =A0 if rising_edge(clock) then
> > =A0 =A0 =A0 if reset =3D '1' then
> > =A0 =A0 =A0 =A0 count :=3D 0;
> > =A0 =A0 =A0 =A0 overflow :=3D '0';
> > =A0 =A0 =A0 elsif count < 0 then
> > =A0 =A0 =A0 =A0 overflow :=3D '1';
> > =A0 =A0 =A0 =A0 count :=3D count + ref_Hz;
> > =A0 =A0 =A0 elsif overflow =3D '1' then
> > =A0 =A0 =A0 =A0 overflow :=3D '0';
> > =A0 =A0 =A0 =A0 count :=3D count - (to_integer(rate) * 2);
> > =A0 =A0 =A0 else
> > =A0 =A0 =A0 =A0 overflow :=3D '0';
> > =A0 =A0 =A0 =A0 count :=3D count - to_integer(rate);
> > =A0 =A0 =A0 end if;
> > =A0 =A0 =A0 pulse <=3D overflow;
> > =A0 =A0 end if;
> > =A0 end process;
> > end;
> > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
> > --
> > Jonathan Bromley, Consultant
>
> > DOULOS - Developing Design Know-how
> > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> > The contents of this message may contain personal views which
> > are not the views of Doulos Ltd., unless specifically stated.
> > --
> > Jonathan Bromley, Consultant
>
> > DOULOS - Developing Design Know-how
> > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> > The contents of this message may contain personal views which
> > are not the views of Doulos Ltd., unless specifically stated.
>
> Dear Jonathan
>
> you wrote that you have made a few trial synthesis runs with the code
> you appended.
> can you tell what synthesis tool did you use?
>
> How many LUT/ FF did you get for say Xilinx S-3 family as target
> device?
>
> I tried Xilinx XST and I have to admit I do not know how to make your
> unmodified code to pass Xilinx synthesis without errors.
> Maybe everybody else can do that, of course this is possible too - but
> I prefer to use VHDL that is KNOWN for ME that
> it passes synthesis for multiply FPGA vendor toolchains. If your code
> is actually able to pass synthesis then it is not
> yet known to me HOW.
>
> Xilinx claims to dominate the FPGA market with 50% gloval share, so if
> some VHDL is not working with Xilinx tools,
> then the use of it already limited to < 50% (at least if we as per
> Xilinx saying..)
>
> Antti

ok, now i KNOW too

xilinx synthesis: 50mhz ref 9600 baud (fixed not variable), s3
FF:18
LUT 17
used Jons unmodifed code :)

Antti






Article: 138164
Subject: Re: Is this phase accumulator trick well-known???
From: Antti <Antti.Lukats@googlemail.com>
Date: Sun, 8 Feb 2009 11:17:12 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 8, 8:27=A0pm, Antti <Antti.Luk...@googlemail.com> wrote:
> On Feb 8, 8:12=A0pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
>
>
> > On Feb 8, 7:02=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> > wrote:
>
> > > hi comp.arch.fpga,
> > > (accidentally posted to comp.lang.vhdl
> > > a few moments ago- sorry)
>
> > > The question - repeated after the explanation -
> > > is: here's what I think is a nifty trick; has
> > > anyone seen it, or been aware of it, before?
> > > I can't believe it's really new.
>
> > > I have been messing around with baud rate generators
> > > and suchlike - creating a pulse that's active for
> > > one clock period at some required repetition rate -
> > > and wanted to try a phase accumulator technique
> > > instead of a simple divider. =A0That makes it far
> > > easier to specify the frequency - it's simply the
> > > phase-delta input value - and easily allows for
> > > non-integral divide ratios, at the cost of one
> > > master clock period of jitter.
>
> > > The phase-accumulator produces pulses with a
> > > repetition rate of
> > > =A0 Fc * M / N
> > > where Fc is the master clock, M is the phase delta
> > > and N is the counter's modulus. =A0However, to get
> > > the huge convenience of specifying M as the required
> > > frequency, I must make N be equal to the frequency
> > > of Fc, and this is unlikely to be an exact power of 2.
> > > So the phase accumulator works like this:
>
> > > =A0 on every clock pulse...
> > > =A0 =A0 if (acc < 0) then
> > > =A0 =A0 =A0 add :=3D acc + N;
> > > =A0 =A0 =A0 output_pulse <=3D '1';
> > > =A0 =A0 else
> > > =A0 =A0 =A0 output_pulse <=3D '0';
> > > =A0 =A0 end if;
> > > =A0 =A0 acc :=3D acc - M; =A0-- unconditionally
>
> > > This is fine, but it means that on the "wrap-around"
> > > clock cycle I must add either N-M to the accumulator;
> > > if either M or N are variable, that costs me another
> > > adder.
>
> > > Today I came up with an intriguing (to me) alternative:
> > > on the wrap-around cycle, add N to the accumulator;
> > > on the immediately subsequent cycle, add (-2M); on
> > > all other cycles, add (-M). =A0This is of course rather
> > > easy to do since 2M is just a left shift. =A0A few
> > > trial synthesis runs convinced me that it will give
> > > measurably better performance than the two-adder
> > > version. =A0VHDL code is appended for anyone who wants
> > > to play.
>
> > > My question is: has this trick been published anywhere?
> > > Or is it something that "those skilled in the art"
> > > already know about? =A0I haven't seen it before, but that
> > > simply means I probably haven't looked hard enough.
>
> > > Thanks!
>
> > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > > ~~ rate generator using novel wrap-around technique
> > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > > library ieee;
> > > use ieee.std_logic_1164.all;
> > > use ieee.numeric_std.all;
>
> > > entity rate_gen is
> > > =A0 -- Specify the master clock frequency as a generic.
> > > =A0 generic ( ref_Hz: positive :=3D 50_000_000 );
> > > =A0 port
> > > =A0 =A0 ( clock : in =A0std_logic
> > > =A0 =A0 ; reset : in =A0std_logic =A0-- Synchronous reset.
> > > =A0 =A0 ; rate =A0: in =A0unsigned =A0 -- Desired output frequency
> > > =A0 =A0 ; pulse : out std_logic =A0-- The output pulse train
> > > =A0 =A0 );
> > > end;
>
> > > architecture RTL of rate_gen is
> > > begin
> > > =A0 process (clock)
> > > =A0 =A0 -- variable "count" is the accumulator
> > > =A0 =A0 variable count: integer range -2**rate'length to ref_Hz-1 :=
=3D 0;
> > > =A0 =A0 -- variable "overflow" is the output pulse and wraparound mar=
ker
> > > =A0 =A0 variable overflow: std_logic :=3D '0';
> > > =A0 begin
> > > =A0 =A0 if rising_edge(clock) then
> > > =A0 =A0 =A0 if reset =3D '1' then
> > > =A0 =A0 =A0 =A0 count :=3D 0;
> > > =A0 =A0 =A0 =A0 overflow :=3D '0';
> > > =A0 =A0 =A0 elsif count < 0 then
> > > =A0 =A0 =A0 =A0 overflow :=3D '1';
> > > =A0 =A0 =A0 =A0 count :=3D count + ref_Hz;
> > > =A0 =A0 =A0 elsif overflow =3D '1' then
> > > =A0 =A0 =A0 =A0 overflow :=3D '0';
> > > =A0 =A0 =A0 =A0 count :=3D count - (to_integer(rate) * 2);
> > > =A0 =A0 =A0 else
> > > =A0 =A0 =A0 =A0 overflow :=3D '0';
> > > =A0 =A0 =A0 =A0 count :=3D count - to_integer(rate);
> > > =A0 =A0 =A0 end if;
> > > =A0 =A0 =A0 pulse <=3D overflow;
> > > =A0 =A0 end if;
> > > =A0 end process;
> > > end;
> > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
> > > --
> > > Jonathan Bromley, Consultant
>
> > > DOULOS - Developing Design Know-how
> > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> > > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> > > The contents of this message may contain personal views which
> > > are not the views of Doulos Ltd., unless specifically stated.
> > > --
> > > Jonathan Bromley, Consultant
>
> > > DOULOS - Developing Design Know-how
> > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> > > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> > > The contents of this message may contain personal views which
> > > are not the views of Doulos Ltd., unless specifically stated.
>
> > Dear Jonathan
>
> > you wrote that you have made a few trial synthesis runs with the code
> > you appended.
> > can you tell what synthesis tool did you use?
>
> > How many LUT/ FF did you get for say Xilinx S-3 family as target
> > device?
>
> > I tried Xilinx XST and I have to admit I do not know how to make your
> > unmodified code to pass Xilinx synthesis without errors.
> > Maybe everybody else can do that, of course this is possible too - but
> > I prefer to use VHDL that is KNOWN for ME that
> > it passes synthesis for multiply FPGA vendor toolchains. If your code
> > is actually able to pass synthesis then it is not
> > yet known to me HOW.
>
> > Xilinx claims to dominate the FPGA market with 50% gloval share, so if
> > some VHDL is not working with Xilinx tools,
> > then the use of it already limited to < 50% (at least if we as per
> > Xilinx saying..)
>
> > Antti
>
> ok, now i KNOW too
>
> xilinx synthesis: 50mhz ref 9600 baud (fixed not variable), s3
> FF:18
> LUT 17
> used Jons unmodifed code :)
>
> Antti

when found that the unmodifed code CAN pass synthesis well felt
stupid.
but it doesnt pass hdl compile for Xilinx ISIM simulator, or at least
i have
not found that trick yet. maybe the compile for sim trick is also
simple.
(for Jons unmodifed code)

so, my first remark ramains, i prefer write VHDL that does pass
synthesis/implementation + sim for multiply FPGA vendor tools.

Antti





Article: 138165
Subject: Re: Is this phase accumulator trick well-known???
From: Alan Fitch <apfitch@invalid.invalid>
Date: Sun, 08 Feb 2009 21:16:14 +0000
Links: << >>  << T >>  << A >>
Antti wrote:
> On Feb 8, 8:27 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>> On Feb 8, 8:12 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>>
>>
>>
>>> On Feb 8, 7:02 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
>>> wrote:
>>>> hi comp.arch.fpga,
>>>> (accidentally posted to comp.lang.vhdl
>>>> a few moments ago- sorry)
>>>> The question - repeated after the explanation -
>>>> is: here's what I think is a nifty trick; has
>>>> anyone seen it, or been aware of it, before?
>>>> I can't believe it's really new.
>>>> I have been messing around with baud rate generators
>>>> and suchlike - creating a pulse that's active for
>>>> one clock period at some required repetition rate -
>>>> and wanted to try a phase accumulator technique
>>>> instead of a simple divider.  That makes it far
>>>> easier to specify the frequency - it's simply the
>>>> phase-delta input value - and easily allows for
>>>> non-integral divide ratios, at the cost of one
>>>> master clock period of jitter.
>>>> The phase-accumulator produces pulses with a
>>>> repetition rate of
>>>>   Fc * M / N
>>>> where Fc is the master clock, M is the phase delta
>>>> and N is the counter's modulus.  However, to get
>>>> the huge convenience of specifying M as the required
>>>> frequency, I must make N be equal to the frequency
>>>> of Fc, and this is unlikely to be an exact power of 2.
>>>> So the phase accumulator works like this:
>>>>   on every clock pulse...
>>>>     if (acc < 0) then
>>>>       add := acc + N;
>>>>       output_pulse <= '1';
>>>>     else
>>>>       output_pulse <= '0';
>>>>     end if;
>>>>     acc := acc - M;  -- unconditionally
>>>> This is fine, but it means that on the "wrap-around"
>>>> clock cycle I must add either N-M to the accumulator;
>>>> if either M or N are variable, that costs me another
>>>> adder.
>>>> Today I came up with an intriguing (to me) alternative:
>>>> on the wrap-around cycle, add N to the accumulator;
>>>> on the immediately subsequent cycle, add (-2M); on
>>>> all other cycles, add (-M).  This is of course rather
>>>> easy to do since 2M is just a left shift.  A few
>>>> trial synthesis runs convinced me that it will give
>>>> measurably better performance than the two-adder
>>>> version.  VHDL code is appended for anyone who wants
>>>> to play.
>>>> My question is: has this trick been published anywhere?
>>>> Or is it something that "those skilled in the art"
>>>> already know about?  I haven't seen it before, but that
>>>> simply means I probably haven't looked hard enough.
>>>> Thanks!
>>>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>>> ~~ rate generator using novel wrap-around technique
>>>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>>> library ieee;
>>>> use ieee.std_logic_1164.all;
>>>> use ieee.numeric_std.all;
>>>> entity rate_gen is
>>>>   -- Specify the master clock frequency as a generic.
>>>>   generic ( ref_Hz: positive := 50_000_000 );
>>>>   port
>>>>     ( clock : in  std_logic
>>>>     ; reset : in  std_logic  -- Synchronous reset.
>>>>     ; rate  : in  unsigned   -- Desired output frequency
>>>>     ; pulse : out std_logic  -- The output pulse train
>>>>     );
>>>> end;
>>>> architecture RTL of rate_gen is
>>>> begin
>>>>   process (clock)
>>>>     -- variable "count" is the accumulator
>>>>     variable count: integer range -2**rate'length to ref_Hz-1 := 0;
>>>>     -- variable "overflow" is the output pulse and wraparound marker
>>>>     variable overflow: std_logic := '0';
>>>>   begin
>>>>     if rising_edge(clock) then
>>>>       if reset = '1' then
>>>>         count := 0;
>>>>         overflow := '0';
>>>>       elsif count < 0 then
>>>>         overflow := '1';
>>>>         count := count + ref_Hz;
>>>>       elsif overflow = '1' then
>>>>         overflow := '0';
>>>>         count := count - (to_integer(rate) * 2);
>>>>       else
>>>>         overflow := '0';
>>>>         count := count - to_integer(rate);
>>>>       end if;
>>>>       pulse <= overflow;
>>>>     end if;
>>>>   end process;
>>>> end;
>>>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>>> --
>>>> Jonathan Bromley, Consultant
>>>> DOULOS - Developing Design Know-how
>>>> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>>>> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
>>>> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>>>> The contents of this message may contain personal views which
>>>> are not the views of Doulos Ltd., unless specifically stated.
>>>> --
>>>> Jonathan Bromley, Consultant
>>>> DOULOS - Developing Design Know-how
>>>> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>>>> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
>>>> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>>>> The contents of this message may contain personal views which
>>>> are not the views of Doulos Ltd., unless specifically stated.
>>> Dear Jonathan
>>> you wrote that you have made a few trial synthesis runs with the code
>>> you appended.
>>> can you tell what synthesis tool did you use?
>>> How many LUT/ FF did you get for say Xilinx S-3 family as target
>>> device?
>>> I tried Xilinx XST and I have to admit I do not know how to make your
>>> unmodified code to pass Xilinx synthesis without errors.
>>> Maybe everybody else can do that, of course this is possible too - but
>>> I prefer to use VHDL that is KNOWN for ME that
>>> it passes synthesis for multiply FPGA vendor toolchains. If your code
>>> is actually able to pass synthesis then it is not
>>> yet known to me HOW.
>>> Xilinx claims to dominate the FPGA market with 50% gloval share, so if
>>> some VHDL is not working with Xilinx tools,
>>> then the use of it already limited to < 50% (at least if we as per
>>> Xilinx saying..)
>>> Antti
>> ok, now i KNOW too
>>
>> xilinx synthesis: 50mhz ref 9600 baud (fixed not variable), s3
>> FF:18
>> LUT 17
>> used Jons unmodifed code :)
>>
>> Antti
> 
> when found that the unmodifed code CAN pass synthesis well felt
> stupid.
> but it doesnt pass hdl compile for Xilinx ISIM simulator, or at least
> i have
> not found that trick yet. maybe the compile for sim trick is also
> simple.
> (for Jons unmodifed code)
> 
> so, my first remark ramains, i prefer write VHDL that does pass
> synthesis/implementation + sim for multiply FPGA vendor tools.
> 
> Antti
> 
> 
> 
> 

Hi Antti,
  I'm reasonably convinced that Jonathan has written good code (I should
state that I'm a colleague of his, so I'm biased!)

Over the last 6 months I have reported bugs in both Modelsim and
Active-HDL - both of which are more mature than isim. I would suggest
you just report a bug.

regards
Alan

P.S. To my great pleasure, both Mentor and Aldec were efficient in
fixing the bugs.

-- 
Alan Fitch
apfitch at ieee
dot org

Article: 138166
Subject: Re: Is this phase accumulator trick well-known???
From: "kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk>
Date: Sun, 08 Feb 2009 15:19:47 -0600
Links: << >>  << T >>  << A >>
Hi Jonathan,

I can't quite get your idea (You may have mistyped M,N)

This is what I do for phase accummulator(modulus not power of 2), 
e.g. modulus = 1600, increment = 869
------------------------------ 
if(modulo_adder < 1600)then
     modulo_adder <= modulo_adder + 869;
     overflow <= '0';
else
     modulo_adder <= modulo_adder + 869 - 1600; 
     overflow <= '1';
end if;
-------------------------------

Can you please express your idea in a numerical example. Sounds
interesting

kadhiem 


Article: 138167
Subject: Re: Is this phase accumulator trick well-known???
From: Antti <Antti.Lukats@googlemail.com>
Date: Sun, 8 Feb 2009 13:28:51 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 8, 11:16=A0pm, Alan Fitch <apfi...@invalid.invalid> wrote:
> Antti wrote:
> > On Feb 8, 8:27 pm, Antti <Antti.Luk...@googlemail.com> wrote:
> >> On Feb 8, 8:12 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> >>> On Feb 8, 7:02 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> >>> wrote:
> >>>> hi comp.arch.fpga,
> >>>> (accidentally posted to comp.lang.vhdl
> >>>> a few moments ago- sorry)
> >>>> The question - repeated after the explanation -
> >>>> is: here's what I think is a nifty trick; has
> >>>> anyone seen it, or been aware of it, before?
> >>>> I can't believe it's really new.
> >>>> I have been messing around with baud rate generators
> >>>> and suchlike - creating a pulse that's active for
> >>>> one clock period at some required repetition rate -
> >>>> and wanted to try a phase accumulator technique
> >>>> instead of a simple divider. =A0That makes it far
> >>>> easier to specify the frequency - it's simply the
> >>>> phase-delta input value - and easily allows for
> >>>> non-integral divide ratios, at the cost of one
> >>>> master clock period of jitter.
> >>>> The phase-accumulator produces pulses with a
> >>>> repetition rate of
> >>>> =A0 Fc * M / N
> >>>> where Fc is the master clock, M is the phase delta
> >>>> and N is the counter's modulus. =A0However, to get
> >>>> the huge convenience of specifying M as the required
> >>>> frequency, I must make N be equal to the frequency
> >>>> of Fc, and this is unlikely to be an exact power of 2.
> >>>> So the phase accumulator works like this:
> >>>> =A0 on every clock pulse...
> >>>> =A0 =A0 if (acc < 0) then
> >>>> =A0 =A0 =A0 add :=3D acc + N;
> >>>> =A0 =A0 =A0 output_pulse <=3D '1';
> >>>> =A0 =A0 else
> >>>> =A0 =A0 =A0 output_pulse <=3D '0';
> >>>> =A0 =A0 end if;
> >>>> =A0 =A0 acc :=3D acc - M; =A0-- unconditionally
> >>>> This is fine, but it means that on the "wrap-around"
> >>>> clock cycle I must add either N-M to the accumulator;
> >>>> if either M or N are variable, that costs me another
> >>>> adder.
> >>>> Today I came up with an intriguing (to me) alternative:
> >>>> on the wrap-around cycle, add N to the accumulator;
> >>>> on the immediately subsequent cycle, add (-2M); on
> >>>> all other cycles, add (-M). =A0This is of course rather
> >>>> easy to do since 2M is just a left shift. =A0A few
> >>>> trial synthesis runs convinced me that it will give
> >>>> measurably better performance than the two-adder
> >>>> version. =A0VHDL code is appended for anyone who wants
> >>>> to play.
> >>>> My question is: has this trick been published anywhere?
> >>>> Or is it something that "those skilled in the art"
> >>>> already know about? =A0I haven't seen it before, but that
> >>>> simply means I probably haven't looked hard enough.
> >>>> Thanks!
> >>>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> >>>> ~~ rate generator using novel wrap-around technique
> >>>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> >>>> library ieee;
> >>>> use ieee.std_logic_1164.all;
> >>>> use ieee.numeric_std.all;
> >>>> entity rate_gen is
> >>>> =A0 -- Specify the master clock frequency as a generic.
> >>>> =A0 generic ( ref_Hz: positive :=3D 50_000_000 );
> >>>> =A0 port
> >>>> =A0 =A0 ( clock : in =A0std_logic
> >>>> =A0 =A0 ; reset : in =A0std_logic =A0-- Synchronous reset.
> >>>> =A0 =A0 ; rate =A0: in =A0unsigned =A0 -- Desired output frequency
> >>>> =A0 =A0 ; pulse : out std_logic =A0-- The output pulse train
> >>>> =A0 =A0 );
> >>>> end;
> >>>> architecture RTL of rate_gen is
> >>>> begin
> >>>> =A0 process (clock)
> >>>> =A0 =A0 -- variable "count" is the accumulator
> >>>> =A0 =A0 variable count: integer range -2**rate'length to ref_Hz-1 :=
=3D 0;
> >>>> =A0 =A0 -- variable "overflow" is the output pulse and wraparound ma=
rker
> >>>> =A0 =A0 variable overflow: std_logic :=3D '0';
> >>>> =A0 begin
> >>>> =A0 =A0 if rising_edge(clock) then
> >>>> =A0 =A0 =A0 if reset =3D '1' then
> >>>> =A0 =A0 =A0 =A0 count :=3D 0;
> >>>> =A0 =A0 =A0 =A0 overflow :=3D '0';
> >>>> =A0 =A0 =A0 elsif count < 0 then
> >>>> =A0 =A0 =A0 =A0 overflow :=3D '1';
> >>>> =A0 =A0 =A0 =A0 count :=3D count + ref_Hz;
> >>>> =A0 =A0 =A0 elsif overflow =3D '1' then
> >>>> =A0 =A0 =A0 =A0 overflow :=3D '0';
> >>>> =A0 =A0 =A0 =A0 count :=3D count - (to_integer(rate) * 2);
> >>>> =A0 =A0 =A0 else
> >>>> =A0 =A0 =A0 =A0 overflow :=3D '0';
> >>>> =A0 =A0 =A0 =A0 count :=3D count - to_integer(rate);
> >>>> =A0 =A0 =A0 end if;
> >>>> =A0 =A0 =A0 pulse <=3D overflow;
> >>>> =A0 =A0 end if;
> >>>> =A0 end process;
> >>>> end;
> >>>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> >>>> --
> >>>> Jonathan Bromley, Consultant
> >>>> DOULOS - Developing Design Know-how
> >>>> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
> >>>> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> >>>> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
> >>>> The contents of this message may contain personal views which
> >>>> are not the views of Doulos Ltd., unless specifically stated.
> >>>> --
> >>>> Jonathan Bromley, Consultant
> >>>> DOULOS - Developing Design Know-how
> >>>> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
> >>>> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> >>>> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
> >>>> The contents of this message may contain personal views which
> >>>> are not the views of Doulos Ltd., unless specifically stated.
> >>> Dear Jonathan
> >>> you wrote that you have made a few trial synthesis runs with the code
> >>> you appended.
> >>> can you tell what synthesis tool did you use?
> >>> How many LUT/ FF did you get for say Xilinx S-3 family as target
> >>> device?
> >>> I tried Xilinx XST and I have to admit I do not know how to make your
> >>> unmodified code to pass Xilinx synthesis without errors.
> >>> Maybe everybody else can do that, of course this is possible too - bu=
t
> >>> I prefer to use VHDL that is KNOWN for ME that
> >>> it passes synthesis for multiply FPGA vendor toolchains. If your code
> >>> is actually able to pass synthesis then it is not
> >>> yet known to me HOW.
> >>> Xilinx claims to dominate the FPGA market with 50% gloval share, so i=
f
> >>> some VHDL is not working with Xilinx tools,
> >>> then the use of it already limited to < 50% (at least if we as per
> >>> Xilinx saying..)
> >>> Antti
> >> ok, now i KNOW too
>
> >> xilinx synthesis: 50mhz ref 9600 baud (fixed not variable), s3
> >> FF:18
> >> LUT 17
> >> used Jons unmodifed code :)
>
> >> Antti
>
> > when found that the unmodifed code CAN pass synthesis well felt
> > stupid.
> > but it doesnt pass hdl compile for Xilinx ISIM simulator, or at least
> > i have
> > not found that trick yet. maybe the compile for sim trick is also
> > simple.
> > (for Jons unmodifed code)
>
> > so, my first remark ramains, i prefer write VHDL that does pass
> > synthesis/implementation + sim for multiply FPGA vendor tools.
>
> > Antti
>
> Hi Antti,
> =A0 I'm reasonably convinced that Jonathan has written good code (I shoul=
d
> state that I'm a colleague of his, so I'm biased!)
>
> Over the last 6 months I have reported bugs in both Modelsim and
> Active-HDL - both of which are more mature than isim. I would suggest
> you just report a bug.
>
> regards
> Alan
>
> P.S. To my great pleasure, both Mentor and Aldec were efficient in
> fixing the bugs.
>
> --
> Alan Fitch
> apfitch at ieee
> dot org

Those who work with REAL FPGA's and tools from FPGA vendors sometimes
can not wait until the FGPA vendors fix their bugs.
i agree ISIM is not a much of a thing.

but still i try to write code that passes with most tools from the
FPGA vendors, in their current state.
not after they fix the bugs i report.

i dont argue that Jonathan writes CORRECT code as per LRM.
that doesnt make the code to pass FPGA vendors toolchains.
its unfortunate of course.


Antti






Article: 138168
Subject: Re: Is this phase accumulator trick well-known???
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sun, 08 Feb 2009 21:32:40 +0000
Links: << >>  << T >>  << A >>
On Sun, 8 Feb 2009 10:27:08 -0800 (PST), Antti wrote:

>ok, now i KNOW too

Aw, shucks, you found me out.  Sitting in my futuristic
bunker in a hollowed-out volcano, stroking my fluffy
white cat and letting out the occasional megalomaniac
cackle, I was thinking: BWAH HAH HAH At last I have
created something that could confuse even the great
Antti.  But it was not to be so :-)

>xilinx synthesis: 50mhz ref 9600 baud (fixed not variable), s3
>FF:18
>LUT 17

Yup.  With a constant rate input, XST does The Right Thing and
collapses all the constants.  With a variable input, you get
approximately 2X LUT-to-FF ratio because you can't fit a
3-input MUX and an adder bit into a single LUT (at least, 
not in Spartan-3... maybe when we have LUT6??? .....)

>used Jons unmodifed code :)

It simulates correctly too, although of course it needs to 
be wrapped in something that provides a signal to connect
to its unconstrained input port.  I haven't tried it with
ISIM just yet, but I believe the code is strictly VHDL-93
compliant and therefore it is NOT MY FAULT if some simulator
cannot handle it.  By contrast, if you can find a synthesis
tool that can't handle it then I'd be glad to know, because
my intent was to create portable synthesisable code.

Thanks
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 138169
Subject: Re: Is this phase accumulator trick well-known???
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sun, 08 Feb 2009 21:54:45 +0000
Links: << >>  << T >>  << A >>
On Sun, 08 Feb 2009 15:19:47 -0600, "kadhiem_ayob" wrote:

>This is what I do for phase accummulator(modulus not power of 2), 
>e.g. modulus = 1600, increment = 869
>------------------------------ 
>if(modulo_adder < 1600)then
>     modulo_adder <= modulo_adder + 869;
>     overflow <= '0';
>else
>     modulo_adder <= modulo_adder + 869 - 1600; 
>     overflow <= '1';
>end if;

Yes, exactly.  But if "869" is a variable (from an
input port) so that the rate is configurable, then
you have

  if (...overflow...) then
    modulo_adder <= modulo_adder + N;
  else
    modulo_adder <= modulo_adder + N - 1600;

The last line requires TWO adders, in addition to the
multiplexer created by the IF.  This causes a significant
performance hit.  That's what I was trying to fix.  I did
it by saying...

  if (...overflow...) then
    adder <= adder + N;
  else
    adder <= adder - 1600;  --oops, need to add extra N

So we modify the code like this:

  if (...overflow...) then
    adder <= adder + N;
  elsif (...there was an overflow on the previous clock...)
    adder <= adder + 2*N;  -- make up for the lost N
  else
    adder <= adder - 1600;

By the way, your code also implies a magnitude comparator,
whereas the less-than-zero test in my code can be done
merely by looking at the most significant bit of the
accumulator.  This saves both gates and levels of logic,
and is well worth the small additional trouble of 
allowing for signed arithmetic.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 138170
Subject: Re: Is this phase accumulator trick well-known???
From: Antti <Antti.Lukats@googlemail.com>
Date: Sun, 8 Feb 2009 14:00:16 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 8, 11:32=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Sun, 8 Feb 2009 10:27:08 -0800 (PST), Antti wrote:
> >ok, now i KNOW too
>
> Aw, shucks, you found me out. =A0Sitting in my futuristic
> bunker in a hollowed-out volcano, stroking my fluffy
> white cat and letting out the occasional megalomaniac
> cackle, I was thinking: BWAH HAH HAH At last I have
> created something that could confuse even the great
> Antti. =A0But it was not to be so :-)
>
> >xilinx synthesis: 50mhz ref 9600 baud (fixed not variable), s3
> >FF:18
> >LUT 17
>
> Yup. =A0With a constant rate input, XST does The Right Thing and
> collapses all the constants. =A0With a variable input, you get
> approximately 2X LUT-to-FF ratio because you can't fit a
> 3-input MUX and an adder bit into a single LUT (at least,
> not in Spartan-3... maybe when we have LUT6??? .....)
>
> >used Jons unmodifed code :)
>
> It simulates correctly too, although of course it needs to
> be wrapped in something that provides a signal to connect
> to its unconstrained input port. =A0I haven't tried it with
> ISIM just yet, but I believe the code is strictly VHDL-93
> compliant and therefore it is NOT MY FAULT if some simulator
> cannot handle it. =A0By contrast, if you can find a synthesis
> tool that can't handle it then I'd be glad to know, because
> my intent was to create portable synthesisable code.
>
> Thanks
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

ah forget ISIM not need make it pass that...

yes the code is most likely full vhdl-93 whatever and it passes
xilinx synthesis.. i may try Actel i am doing something where
the code be handy.

Ah, BTW, if you create hdl template from the unit with xilinx
it converts the unsigned to std_logic
so that has to be manually patched..
so this small code actually did trap 2 xilinx tool bugs...

i would possible not have posted my first response
but i was fighting a small stupid problem what happened
to be a really stupid issue.

an USB bootloader did not seem to work after small
change of code.

[3 days later]

i had all the time used file blinky.bin
from folder that contained blinky.c
assuming it to be my blink led binary (knwon good one)
but as i finally found out, my script converted
blinky.hex to BLINKER.BIN
and blinky.bin was 0 bytes long.

so when i did read back the flash after update
it looked like the update failed, nothing written.

actually it worked, but the update was 0 byte long.


good night everyone !

Antti















Article: 138171
Subject: Re: Is this phase accumulator trick well-known???
From: Glen Herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Sun, 08 Feb 2009 15:02:26 -0700
Links: << >>  << T >>  << A >>
Jonathan Bromley wrote:

> hi comp.arch.fpga,
> (accidentally posted to comp.lang.vhdl 
> a few moments ago- sorry)

> The question - repeated after the explanation - 
> is: here's what I think is a nifty trick; has
> anyone seen it, or been aware of it, before?
> I can't believe it's really new.

As far as I know, the usual system is to use a power of
two modulus and supply enough bits to get the required
accuracy.  It is then easy to take the top bit as
a (close enough to) 50% duty cycle clock.

> I have been messing around with baud rate generators
> and suchlike - creating a pulse that's active for
> one clock period at some required repetition rate -
> and wanted to try a phase accumulator technique 
> instead of a simple divider.  That makes it far 
> easier to specify the frequency - it's simply the
> phase-delta input value - and easily allows for
> non-integral divide ratios, at the cost of one
> master clock period of jitter.

> The phase-accumulator produces pulses with a
> repetition rate of 
>   Fc * M / N 
> where Fc is the master clock, M is the phase delta
> and N is the counter's modulus.  However, to get
> the huge convenience of specifying M as the required
> frequency, I must make N be equal to the frequency
> of Fc, and this is unlikely to be an exact power of 2.
> So the phase accumulator works like this:

>   on every clock pulse...
>     if (acc < 0) then
>       add := acc + N;
>       output_pulse <= '1';
>     else
>       output_pulse <= '0';
>     end if;
>     acc := acc - M;  -- unconditionally

> This is fine, but it means that on the "wrap-around"
> clock cycle I must add either N-M to the accumulator;
> if either M or N are variable, that costs me another
> adder.

Adders are pretty cheap in FPGAs.  It would take some
work to see if your method is a net savings.

> Today I came up with an intriguing (to me) alternative:
> on the wrap-around cycle, add N to the accumulator;
> on the immediately subsequent cycle, add (-2M); on
> all other cycles, add (-M).  This is of course rather
> easy to do since 2M is just a left shift.  A few 
> trial synthesis runs convinced me that it will give
> measurably better performance than the two-adder
> version.  VHDL code is appended for anyone who wants
> to play.

It seems to me that needs an additional MUX to
save an adder.  In 4LUT logic, I believe that
is pretty close to the same in CLBs.

> My question is: has this trick been published anywhere?
> Or is it something that "those skilled in the art"
> already know about?  I haven't seen it before, but that 
> simply means I probably haven't looked hard enough.

There are a large number of tricks that have been used
over the years to make computer arithmetic faster.  Many of
those tricks aren't as effective in FPGA logic, so new
ones will have to be developed.

-- glen


Article: 138172
Subject: Re: Is this phase accumulator trick well-known???
From: nospam <nospam@please.invalid>
Date: Sun, 08 Feb 2009 22:14:31 +0000
Links: << >>  << T >>  << A >>
"kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk> wrote:

>Hi Jonathan,
>
>I can't quite get your idea (You may have mistyped M,N)
>
>This is what I do for phase accummulator(modulus not power of 2), 
>e.g. modulus = 1600, increment = 869
>------------------------------ 
>if(modulo_adder < 1600)then
>     modulo_adder <= modulo_adder + 869;
>     overflow <= '0';
>else
>     modulo_adder <= modulo_adder + 869 - 1600; 
>     overflow <= '1';
>end if;
>-------------------------------

Where the 869 or 1600 are variable your code requires two adders and a 2
way mux. 

Jonathan's code avoids adding the increment on overflow cycles and makes up
by adding double the increment in the cycle following overflow. That
requires 1 adder and a 3 way mux. It won't work when the increment is more
than half the modulus. 

Well known trick or not I have no idea. 
-- 

Article: 138173
Subject: Re: Is this phase accumulator trick well-known???
From: Mike Treseler <mtreseler@gmail.com>
Date: Sun, 08 Feb 2009 15:12:19 -0800
Links: << >>  << T >>  << A >>
Jonathan Bromley wrote:

> It simulates correctly too, although of course it needs to 
> be wrapped in something that provides a signal to connect
> to its unconstrained input port. 

This may be the point that Antti missed,
as he mentioned "unmodified" code.
Without a wrapper or constraint, I wouldn't expect
elaboration to succeed:

# vsim -c rate_gen
# Loading /flip/usr1/modeltech/linux/../std.standard
# Loading /flip/usr1/modeltech/linux/../ieee.std_logic_1164(body)
# Loading /flip/usr1/modeltech/linux/../ieee.numeric_std(body)
# Loading work.rate_gen(rtl)#1
# ** Fatal: (vsim-3347) Port 'rate' is not constrained.

A minimal constraining modification like this:
 rate  : in  unsigned(15 downto 0)
proves that the code would sim ok, with a proper instance.

# vsim -c rate_gen
# Loading /flip/usr1/modeltech/linux/../std.standard
# Loading /flip/usr1/modeltech/linux/../ieee.std_logic_1164(body)
# Loading /flip/usr1/modeltech/linux/../ieee.numeric_std(body)
# Loading work.rate_gen(rtl)#1
VSIM 1> run
VSIM 2>


 -- Mike Treseler

Article: 138174
Subject: Re: Is this phase accumulator trick well-known???
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Sun, 08 Feb 2009 17:13:43 -0600
Links: << >>  << T >>  << A >>

>  if (...overflow...) then
>    modulo_adder <= modulo_adder + N;
>  else
>    modulo_adder <= modulo_adder + N - 1600;
>
>The last line requires TWO adders, in addition to the
>multiplexer created by the IF.  This causes a significant
>performance hit.  That's what I was trying to fix.  I did
>it by saying...


>So we modify the code like this:
>
>  if (...overflow...) then
>    adder <= adder + N;
>  elsif (...there was an overflow on the previous clock...)
>    adder <= adder + 2*N;  -- make up for the lost N
>  else
>    adder <= adder - 1600;

It looks like a 2 input mux with 2 adders vs
a 3 input mux with 1 adder.

The second adder can be pulled out and done ahead of time, aka pipelined.
If speed rather than space is your goal, that might be better.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.




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